Current Programmed Control o f a Single Phase Two-Switch Buck-Boost Power Factor Correction Circuit Gert K . Andersen, Frede Blaabjerg Aalborg University, Institute o f Energy Technolog y, Denmark [email protected]Abstract- This paper presents a new Current Pro- grammed Control (CPC) technique for the cascaded two switch buck-boost converter suitable as a low-cost Power Factor Correction (pfc) rectifier in a variable speed motor drive. This new CPC technique, which is an extension of the conventional CPC method, enables variable output dc- voltage and is therefore suitable in a Pulse Amplitude Mod- ulated (PAM) motor drive o r as an universal input power supply. The C PC method is very simple and requi res only a constant current reference without any changes at the tran- sition between boost and buck operating mode and the line current is practically unaffected by the topology mode shift. The presented control technique is verified by simulations and experimental results and compliance with IEC 61000-3- 2 class A is achieved. The experimental setup is based on a commercial CPC IC for dc-dc converters. I. INTRODUCTION EGULATIONS like IEC-61000-3-2 demand some sort R f input current shaping for single phase equipment [l]. Active current shaping is usually used in the power range around 2 kW in order to reduce the volume o f the conver ter and the converter usually consists of a conventional diode bridge followed by a dc-dc switch-mode converter which shapes the current. An active power factor correction (pfc) circuit with variable output dc-voltage as a supply in a low- cost adjustable speed induction motor drive is interesting from a drive-design point of view because there exists only high switching frequency in the rectifier. Th e pf c control technique in a low-cost motor drive must be simple and robust. There exist a variety of control techniques for switch mode converters and power factor correction circuits and most of these techniques are supported by commercial and avail- able ICs for th e basic converter topologies like boost, bu ck, buck-boost, push-pull, forward, flyback, sepic, kuk etc. [2], [3]. Different pfc control techniques are compared in [3]. Average Current Control (ACC) is relative immune to- wards noise because only average signals are used but ACC requi res a current refer ence generator which may be expen- siv e. CPC is inherently more sensitive towards noise and circuit layout must be done ver y careful ly but CP C is a sim- ple control technique which provides cycle-by-cycle current limiting, and t he use of a wave-shaping r eference generator can be omitted. Stability o f CP C has been subjected to in- tense study in the literature (cf. [2]-[12]) but stability is not an issue if the switch duty cycle is restricted into a range equal to one half of the switchin g period. This range can be 0 2 d 5 1/ 2 or 1/ 2 2 d 5 1 depending on the control strategy which will be shown later. Limit cycle, hysteresis or bang-bang current control is a simple technique which is sensitive towards noise in the same manner as CPC and this technique also requires two current reference genera- tors[l4]. In addition, hysteresis control, in its most simple structure, has a variable switching frequency. Borderline control is basically a hysteresis control technique where the lowe r boundary is zer o. In addition there exist some types o f cont rol techniques which requires no direct curr ent ref- erence and are therefore relative immune towards input voltage distortions[ 15 1, 161. Comp lian ce with IEC-61000 - 3-2 depends strongly on the choice of switching frequency and switching inductance for C PC whereas ACC and limit cycle control are able to comply with IEC-61000-3-2 re- gardless (practically) of the switching frequency and the switching inductor. A summary of these statements are listed in Table I. CPC is an interesting control method when costs and complexity must be minimized at the expense of line cur- rent performance. This paper describes a new simpl e C PC technique with constant command current and without ramp compensa- tion for the two-switch buck-boost pfc converter capable o f complying with IEC-6100 0-3-2. T he output dc-voltage can be varied by adjusting the command current and the application used here is a pfc dc voltage supply for a PAM inverter. Since no commercial IC exists for controlling this converter topology a control strategy based upon existing CPC ICs is developed and tested in the laboratory. 11. CURRENT ROGRAMMED ONTROL Current Programmed Control (C PC) has been descr ibed heavily in the literatu re (cf. [2] -[12])and the major issue has been the stability analysis because conventional CPC inherently becomes unstable, when the switch duty cycle is greater than 1/2. Ramp compensation can be added i n order to expand the range of stability. Fig. l a depicts the basic idea behind CPC for continuous conduction mode. The switch is turned on at the beginning of each switch- ing period and the switch is turned of f at the time instant when the inductor or switch current equals the command current IC. This kind of CPC is here denoted as Upper- Boundary-Current-Programmed-Control (UBCPC). 0-7803-6618-2/01/$10.00 0 2001 IEEE 350
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8/14/2019 Current Programmed Control of a Single Phase
Fig. 3. Simulated waveform at Vd,= 250 V. Top: rectified voltageMiddle:v,,,), dc-voltage ( v d , ) and converter mode (mode).
Inductor current ( i ~ ) nd bottom: duty cycles.
switch duty cycle also drops to zero.
steady-state
waveform \
r
(W+Z)T wT T t4
Perturbed
(W+i?))T wT T t
The average input current per switch period increases
from the zero crossing towards the point where the dc-
voltage and the rectified voltage becomes equal and the
converter shifts to buck mode. If UBCPC is used in the
buck mode then the average input current per switch pe-
riod will decrease when converter shifts from boost mode
introduces low order harmonics. If DBCPC is used in the
riod will continue to increase as it did in boost mode. Thus,:$ TTQp,,p ,A nQpDp Or _ im
Fig. 4. Definition of waveforms for a) UBCPC and b) DBCPC.
and the current at the switching instant i ~ ( w T )s
to buck mode if the same current command is used which i~ (urT )= i~(O)+m,wT * (1)
(2 )i ~ ( w T )i~(0)
w =buck mode then the average input current per switch pe- m,T
,--,, where i~(0)s the current at the beginning of the switchingAI VUWL w aiiu UYWA w mc UDGU ALL U U U D ~ auu U U L ~uvus . . m m. . . .. . I .. .. . . .respectively and the command current is constant then the
average input current per switch period will be unaffected
by the topology mode shift. Fig. 3 also shows the duty
cycles and it appears that the buck duty cycle decreases
smoothly from unity at the topology mode shift but the
buck switch duty cycle is higher than 1 / 2 in the entire
buck range. Conventional CPC without ramp compensa-
tion becomes unstable when the duty cycle exceeds 1 / 2 and
the next section will describe the stability in a generalized
manner regardless if UBCPC or DBCPC is used.
IV . STABILITY
The stability range of CPC is generalized here and the
derivations is based on the simple model as presented in [2].
This known model assumes constant current slopes and ne-
glects the effects of the modulator. The analysis assumes
that the current slopes (man,m, f f )and the command cur-
rent I , are constant during a switch period.
-
period 1 . i'he current at the end or the switching period
becomes
ZL(T) = i~(urT)+m,uT + (3 )
(4)
Thus in steady state (m , =M,, mu = Mu, = W,U =U ) he volt-second balance yields
(5)= M,WT+M,UT +
This equation shows the volt-second balance in steady
state, where the error is zero. In the ideal case the entire
range of switch duty cycle can be utilized without stability
problems but these ideal considerations are not sufficient in
reality because stability becomes a problem due to noise,delays and other nonideal effects.
The stability will be calculated and analysed by intro-
ducing a small perturbation ~ ( 0 )f the initial inductor
current i~(0)cf. Fig. 4). The current becomes
The slope before the switching instant is denoted m,and the slope after the switching instant is denoted mu
and, consequently, the corresponding duration are denoted
w and U respectively. Fig. 4 show the definition s of the
inductor current steady stat e and perturbed waveforms in iL(o)= I,(o) + E , l ( 0 ) where J E , ~ ( o ) J IIL(o)l (7)
UBCPC (Fig. 4a) and in DBCPC (Fig. 4b).
Where IL (O) is the ideal steady state inductor current
at the beginning and at the end of a switching switchingt first the ideal case is shown where the error is zero
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8/14/2019 Current Programmed Control of a Single Phase