Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 1 PSoC 3 / PSoC 5 101: Architecture Overview
Sep 09, 2014
Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 1
PSoC 3 / PSoC 5 101: Architecture Overview
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Section Objectives
Objectives, you will:• Understand the high-level architecture of PSoC 3 / PSoC 5• Understand the CPU, Digital, Analog & Programmable
Routing / Interconnect Subsystems
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PSoC 3 / PSoC 5 Platform Architecture
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CPU Subsystem
ARM Cortex-M3
• Industry’s leading embedded CPU company
• Broad support for middleware and applications
• Up to 80 MHz; 100 DMIPS
• Enhanced v7 ARM architecture:
• Thumb2 Instruction Set
• 16- and 32-bit Instructions (no mode switching)
• 32-bit ALU; Hardware multiply and divide
• Single cycle 3-stage pipeline; Harvard architecture
8051
• Broad base of existing code and support
• Up to 67 MHz; 33 MIPS
• Single cycle instruction execution
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CPU Subsystem
High Performance Memory
• Flash memory with ECC
• High ratio of SRAM to flash
• EEPROM
Powerful DMA Engine
• 24-Channel Direct Memory Access
• Access to all Digital and Analog Peripherals
• CPU and DMA simultaneous access to independent SRAM blocks
On-Chip Debug and Trace
• Industry standard JTAG/SWD (Serial Wire Debug)
• On chip trace
• NO MORE ICE
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CPU Subsystem
Clocking System
• Many Clock Sources• Internal Main Oscillator • External clock crystal input• External clock oscillator inputs• Clock doubler output• Internal low speed oscillator • External 32 kHZ crystal input• Dedicated 48 MHz USB clock• PLL output
• 16-bit Clock Dividers• 8 Digital• 4 Analog
• PSoC Creator Configuration Wizard• PSoC Creator auto-derive clocking source/dividers
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CPU Subsystem
Dedicated Communication Peripherals
• Full Speed USB device• 8 bidirectional data end points + 1 control end point• No external crystal required• Drivers in PSoC Creator for HID class devices
• Full CAN 2.0b• 16 RX buffers and 8 TX buffers
• I2C master or slave• Data rate up to 400 kbps• Additional I2C slaves may be implemented in UDB
array
• New peripherals will be added as family members are added to the platform: Ethernet, HS USB, USB Host…
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CPU Subsystem
Power Management
• Industry’s Widest Operating Voltage• 0.5V to 5.5V with full analog/digital capability
• High Performance at 0.5V• PSoC 3 @ 67 MHz; PSoC 5 @ 72 MHz
• 3 Power Modes (Active, Sleep and Hibernate)
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Designed for Low Power/Low Voltage
Integrated Analog, Digital and Communication Peripherals
Reduce external component counts and lower overall system power consumption
Universal Digital BlocksImplement features in
hardware that reduce CPU processing requirements,
lowering power consumption
Precise CPU frequenciesPLL allows 4,032 different frequencies; tunable power
consumption
On-board DMA ControllerDirect memory transfer between
peripherals offloads CPU operation, lowering power consumptionHighly configurable clock
treeFlexible, automated clock gating.
Cached OperationsExecution from flash memory is
improved by caching instructions (PSoC 5 only)
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Low Power Modes
Power modeCurrent
(PSoC 3)Current
(PSoC 5)Code
execution
Digital resources available
Analog resources available
Clock sources available
Wakeup sources
Reset sources
Active1.2 mA @ 6MHz
2 mA @ 6MHz
Yes All All All N/A All
Sleep 1 uA 2 uA No I2C ComparatorLow Speed and
32 kHz Osc
IO, I2C, RTC,
sleep timer, comparator
XRES, LVD, WDR
Hibernate 200 nA 300 nA No None None None IO XRES, LVD
Power Management Enabled in PSoC Creator
• Provides easy to use control APIs for quick power management
• Allows code and register manipulation for in-depth control
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Digital Subsystem
• Flexibility of a PLD integrated with a CPU
• Provides hardware capability to implement components from a rich library of pre-built, documented, and characterized components in PSoC Creator
• PSoC Creator will synthesize, place, and route components automatically.
• Fine configuration granularity enables high silicon utilization
• DSI routing mesh allows any function in the UDBs to communicate with any other on-chip function/GPIO pin with 8- to 32-bit data buses
Universal Digital Block Array (UDBs)
32-bit PWM
16-bit PWM
I2C Slave
SPI Master
LCD Segment Drive
UART #1
UART#2UART #3
16-bit Shift Reg.
GP Logic
GP Logic
GP Logic
GP Logic
GPLogic
GPLogic
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Digital Subsystem
• Provides nearly all of the features of a UDB based timer, counter, or PWM
• PSoC Creator provides easy access to these flexible blocks
• Each block may be configured as either a full featured 16-bit Timer, Counter, or PWM
• Programmable options• Clock, enable, reset, capture, kill from any pin
or digital signal on chip• Independent control of terminal count,
interrupt, compare, reset, enable, capture, and kill synchronization
• Plus• Configurable to measure pulse widths or
periods• Buffered PWM with dead band and kill
Optimized 16-bit Timer/Counter/PWM Blocks
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Analog Subsystem
• Flexible Routing: All GPIO are Analog Input/Output
• +/- 0.1% Internal Reference Voltage• Delta-Sigma ADC: Up to 20-bit resolution
• 16-bit at 48 ksps or 12-bit at 192 ksps• SAR ADC: 12-bit at 1 Msps• DACs: 8 – 10-bit resolution, current and
voltage mode• Low Power Comparators• Opamps (25 mA output buffers)• Programmable Analog Blocks
• Configurable PGA (up to x50), Mixer, Trans-Impedance Amplifier, Sample and Hold
• Digital Filter Block: Implement HW IIR and FIR filters
• CapSense Touch Sensing enabled
Configurable Analog System
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Programmable Routing/Interconnect
Input / Output System
Up to 4 separate I/O voltage domains
• Interface with multiple devices using one PSoC 3 / PSoC 5 device
• Three types of I/O
• GPIO, SIO, USBIO
• Any GPIO to any peripheral routing
• Wakeup on analog, digital or I2C match
• Programmable slew rate reduces power and noise
• 8 different configurable drive modes
• Programmable input threshold capability for SIO
• Auto and custom/lock-able routing in PSoC Creator
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PSoC 3 / PSoC 5 Platform Architecture
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Review
You should now:• Understand the high-level architecture of PSoC 3 / PSoC 5• Understand the CPU, Digital, Analog & Programmable
Routing / Interconnect Subsystems
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Lab 101:My First PSoC 3 Digital Design
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Lab Objectives
Objectives:• Blink an LED on the PSoC First Touch Kit• Experience the PSoC Creator Design Flow
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Step 1: Start PSoC Creator
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Step 2: Create a New Project
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Step 3: Place/Configure Digital Pin
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Step 3: Place/Configure Digital Pin
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Step 4: Configure PSoC I/O
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Step 5: Add main.c Code
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Step 5: Add main.c Code
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Step 6: Build Project
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Step 7: Program/Debug
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Step 8: Debug
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PSoC 3 / PSoC 5 101:PSoC Creator Design Flow
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Section Objectives
Objectives, you will be able to:• Follow the PSoC Creator Design Flow and develop projects• Find and use the tools available within the software IDE• Compile, build and program PSoC 3 / PSoC 5 applications• Debug PSoC 3 / PSoC 5 applications
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PSoC Creator Design Flow
Configure• Start a new project• Place components• Configure components• Connect components
Develop• Build hardware design and generate component APIs• Write application code utilizing component APIs• Compile, build and program
Debug• Perform in-circuit debug using PSoC Creator
Reuse• Capture working hardware/software designs as your own components for
future use
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Open PSoC Creator
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PSoC Creator Software
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Create a new project
Select the platform
Name the design
Select the device*
Select the sheet template*
* Optional steps
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PSoC Creator Design Canvas
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Component Catalog
Catalog FoldersAnalog
ADC
Amplifier
DAC
DigitalRegisters
Functions
Logic
Communication
Display
System
Catalog Preview
Datasheet access
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Adding Components to a Design
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Pins, Logic and Clock Components
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Component Configuration
Double-click to open component configuration dialogs
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Component Data Sheets
Contents:• Features
• General description of component
• When to use component
• Input/Output connections
• Parameters and setup
• Application Programming Interface
• Sample firmware source code
• Functional description
• DC and AC electrical characteristics
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Design-Wide Resource Manager (.cydwr)Clocks
Interrupts• Set priority and vector
DMA• Manage DMA channels
System• Debug, boot parameters, sleep
mode API generation, etc.
Directives• Over-ride placement defaults
Pins• Map I/O to physical pins and ports• Over-ride default selections
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Interrupts
Priority may be changed
Defaults to 7 (lowest priority)
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DMA
Priority may be changed
Defaults to 2 (0 & 1 can consume 100% of bandwidth)
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System
System settings
Debug settings
Voltage Configuration
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System Clocking Tree
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Clock Configurations
Clocks are allocated to slots in the clock tree• 8 digital, 4 analog
Clocks have software APIs
Reuse existing clocks to preserve resources
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Pin Editor
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Connecting Components
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Build Hardware Design
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Build Process
Generate a Configuration• Design Elaboration
• Netlisting
• Verilog
• Logic Synthesis
• Technology Mapping
• Analog Place and Route
• Digital Packing
• Digital Placement
• Digital Routing
• <…there’s more…>
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Build Process
API Generation
Compilation
Configuration Generation
Configuration Verification
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Development Files
Core Cypress Libraries (CyLib)
Registers, macros, types (cytypes)
Component addressing (cyfitter)
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Supported Compilers
Free Bundled compiler optionsPSoC 3: Cypress-Edition Keil™ CA51 Compiler Kit
PSoC 5: GNU/CodeSourcery Sourcery G++™ Lite
No code size restrictions, not board-locked, no time limit
Fully integrated including full debugging support
Upgrade, more optimization/compiler-support optionsPSoC 3: Keil CA51™ Compiler Kit
PSoC 5: Keil RealView® Microcontroller Development Kit
Higher levels of optimization
Direct support from the compiler vendor
Upgrade Compiler PricingSet and managed by our 3rd party partner, Keil
Already own these compilers? No need to buy another license!
Keil CA51 Compiler Kit ~$2,000
Keil RealView MDK ~$3,000-5,000
GNU
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Integrated Debugger
JTAG and SWD connection• All devices support debug
• MiniProg3 programmer / debugger
Control execution with menus, buttons and keys
Full set of debug windows• Locals, register, call stack, watch (4), memory (4)
• C source and assembler
• Components
Set breakpoints in Source Editor
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Debugger Windows
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MiniProg3
• Program PSoC 1 devices• Program/Debug PSoC 3 / PSoC 5 devices• Standard 50mil connector• nTRST/XRES pin is used as the device
reset (XRES) by default• nTRST is JTAG specific and rarely used
2x5 50mil ISSP/JTAG/SWD/ SWV/TracePort ribbon cable and connector
ISSP connector
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PSoC Development Kit (CY8CKIT-001)
• Supports all PSoC architectures via processor modules• Integrated support of all required and optional chip connections• MiniProg3 should not supply power to PSoC Development Kit
PSoC Processor Modules
3.3V, 5.0V and adjustable 1.8V–5.0V regulators
Independent digital, analog and IO supply rails (current measurement supported)
Three expansion ports support 28 IO each + 45 IO
RS-232
RF Module Radio header
USB for target
CapSense Slider & Buttons1 Pot, 2 buttons, 4 LEDs, 2x16 LCD
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Review
You should now be able to:•Follow the PSoC Creator Design Flow and develop projects•Find and use the tools available within the software IDE•Compile, build and program PSoC 3 / PSoC 5 applications•Debug PSoC 3 / PSoC 5 applications