CSH Consulting, LLC Signal Integrity Consulting June 2017 [email protected]. 603-494-9277 www.cshconsulting.net
CSH Consulting, LLC
Signal Integrity Consulting
June 2017
[email protected]. 603-494-9277www.cshconsulting.net
Overview
• High Speed Serial Channel Modeling– 25Gbps Ethernet, 56G PAM4, PCIe GenX, Fibre Channel, SAS, USB– Anything over 2Gb/s requiring frequency domain simulation and modeling.
• High Speed Memory Simulation– DDR2, DDR3, DDR4– Clock, Address, Data, Data Strobe– Buffer Strengths, On Die Termination, Topology, Waveform Integrity, Setup and Hold Mask
Evaluations for DQ and Command/Control/Address.– DQ Rx Eye Mask for DDR4
• Power Integrity Simulation– DC Analysis and Frequency Response Analysis of Power Planes– Decoupling Capacitor Optimization
• CAD Guidelines– Concise recommendations for PCB Layout based on Pre-Layout Simulations.
Simulation Capability
• Software Resources
–Keysight ADS
• Statistical Eye simulation using IBIS-AMI Models
–Ansys HFSS
•3D Modeling of structures (vias, AC Caps, BGAs, Connectors)
•3D Modeling of pcb etch.
•In-house automation ensures faster response and consistency
–Ansys SIwave
•Power Plane Voltage Drop simulation
•Power Plane Frequency analysis and decoupling capacitor optimization
–Apsim RLGC
•2D Modeling of PCB Transmission Lines
•Frequency-dependent W-elements
–HSpice
•Time Domain Simulation using IBIS and AMI.
•Frequency Domain Simulation
– Concatenation of S-Parameters
Channel Modeling - Process and Tools
• Link Models created in HSpice
–Cascaded S-parameters of connector, footprint, etch
• Connector Models
–Provided by Connector Vendor in Touchstone format.
• PCB Footprints
–Simulated in Ansoft HFSS
• Each one is different!
• PCB Etch Models
–Tabular W-element RLGC Models generated in Apsim RLGC.
–De-Embedded S-parameter Model generated in HFSS
BGA
PackageBGA Via
PCB
Etch
Transition
Via
Connector
FootprintConnector
Connector
Footprint
Backplane
Etch
BGA
Package
PCB
Etch
PCB
EtchAC Cap
Connector
FootprintConnector
Connector
Footprint
Passive Channel Design Drivers
• Insertion Loss
– Driven by PCB material property and via stubs.
• Return Loss
– Driven by Impedance mismatches mainly arising in component footprints.
• Crosstalk
– Unwanted electromagnetic coupling between traces, vias and connector
contacts.
• Skew
– Driven by routing, connector, and PCB laminate material.
• Common Mode Conversion and EMI
– Driven by unbalanced differential pairs in routing and connectors.
PCB Material Property Extraction From Measurements
Insertion Loss vs PCB and Cable Material
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0Loss Characteristic of 1m of Copper Medium
Frequency (GHz)
Magnitude (dB
)
26AWG EXD
Megtron-7NE RA
Megtron-7NE
Megtron-6 FlatBond
Length: 1m
Line Width: 6.5mil
Line Space: 8.5mil
Copper Weight: ½ oz
High Confidence Region (< 30dB)
Near Limit ( 30-40dB)
No Operation
Insertion Loss vs. Line Width
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-40
-38
-36
-34
-32
-30
-28
-26
-24
-22
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0Megtron 6 Insertion Loss: 40 inches
Frequency (GHz)
Magnitude (
dB
)
sdd12-5p5
sdd12-6p5
Crosstalk Sources
1. Between Differential Pair Traces
– Crosstalk Target < = -50dB
2. Between Vias in Footprint
– Simulate and Tune
• Antipad shapes
• Drill size
• Pad Size
• Backdrill Depth
3. Within Connectors
– Simulate and tune conductor geometry, plastic materials and return paths.
3h-5h
h
0 2 4 6 8 10
x 109
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0FEXT Contributors (GH2 Driven)
Frequency (Hz)
DC Blocking Capacitor Example
Oval Dogbone 51.0mil
Antipad Dia 51.0mil
Pad Dia 20.0mil
Drill Dia 9.8mil
Finished Dia 5.8mil
Anti Line Width 4.25mil
Line Space 11.5mil
EtchBack 0.1mil
Line Width 4.25mil
Layer Escape 8
Diff Port Zo 100
Thickness 61.4 mil
Layers 10
Df 0.01
Dk 3.8
Material Megtron-4
Adapt Freq. 10 GHz
Max Freq. 20 GHz
0
0 85
20
20
65
154
174
Cap 0402
Clearance Layer 2
DC Blocking Capacitor Example ResultsInsertion Loss, Return Loss and TDR
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-40
-35
-30
-25
-20
-15
-10
-5
0
Frequency (GHz)
Magnitude (
dB
)
Differential Insertion and Return Loss: Riser ACCap L8
-28.5dB @ 5.0GHz
Sdd12
Sdd11
Goal
0 0.1 0.2 0.3 0.485
90
95
100
105
Time (nS)
Ohm
s
92.6 to 104.8 ohms
TDR: Riser-ACCap-L8
Riser-ACCap-L8
IEEE 802.3ap KR (10Gbps): Insertion Loss and ILDChannel Example
0 2 4 6 8 10-70
-60
-50
-40
-30
-20
-10
0
Frequency (GHz)
Magnitude (
dB
)
-7.6dB @ 5.0GHz
Simulated Link-Sdd65
Simulated Link LS
IL Mask High
IL Mask Low
1 2 3 4 5 6-5
-4
-3
-2
-1
0
1
2
3
4
5
Frequency (GHz)
Magnitude (
dB
)
Range: 1.28 dB
IL Deviation Simulated-Sdd65
IL Deviation High
IL Deviation Low
IEEE 802.3ap KR (10Gbps): Return Loss and ICRChannel Example
10-1
100
101
-40
-35
-30
-25
-20
-15
-10
-5
0
Frequency (GHz)
Magnitude (
dB
)
-12.2dB @ 5.0GHz
Simulated Link-Sdd11
Return Loss Mask
10-1
100
0
10
20
30
40
50
60
70
80
Frequency (GHz)
Magnitude (
dB
)
ICR Pinout 1: Intel KR Riser to Denali 1p0 Channel Rx
37.3dB @ 5.0GHz
Next2x1, Next3x1, Fext1x1
Simulated Link
Simulated Link LS
ICR Mask
IEEE 802.3bj (25Gbps) Insertion and Return Loss Channel Example
sdd12=s16ptest.sdd(:,2,1); sdd11=s16ptest.sdd(:,2,2);
0 5 10 15 20 25-80
-70
-60
-50
-40
-30
-20
-10
0
Frequency (GHz)
Magnitude (
dB
)
-15.4dB @ 12.5GHz
Simulated Link
IL Mask
0 5 10 15 20 25-40
-35
-30
-25
-20
-15
-10
-5
0
Frequency (GHz)
Magnitude (
dB
)
-20.1dB @ 12.5GHz
Simulated Link
RL Mask
IEEE 802.3bj (25Gbps) Crosstalk and ICRChannel Example
0 5 10 15 20 25 30 35 40-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Fext1= 6,1. Fext2= 6,3. Fext3= 6,7.
Frequency (GHz)
Magnitude (
dB
)
Fext1
Fext2
Fext3
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0Insertion Loss and Crosstalk: Lepton 25G Examax Post Layout Channel
Frequency (GHz)
Magnitude (
dB
)
39.0dB @ 12.5GHz
Fext1x1, Fext2x1, Fext3x1
Sdd65
TotalXTK:RMS
Channel TDRChannel Example
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 575
80
85
90
95
100
105
110
Time (nS)
Ohm
s
Lepton 25G Examax Post Layout Channel
SIwave: Power Plane Voltage Drop
SIwave: Power Plane Impedance vs. Frequency
0.1 1 10 100 10000.001
0.01
0.1
1
10
100
1000
Frequency (MHz)
Impedance (
ohm
s)
Power Plane Impedance at U2. File: ..\Plane_Only_SYZ.xls
Goal: 0.080ohm @ 40.0MHz.
Plane Only
Plane With Caps
Goal
ADS Schematic:1 Million Bit-By-Bit Simulation
Statistical Eye: 25Gbps1 Million Bit-By-Bit Simulation
Statistical Eye: 6.25GbpsMeasurement vs. Simulation
Measurement
Simulation
(from LinkEye)
240mV
0.76UI
162mV0.70UI
DDR3 Address Path Topology Example
0.540”
Freescale P1021
U1
U2
N3
0.552”
U3
N3
U4
N3
0.160”
0.75V
39Ω
0Ω
1.446”
Micron v68a.ibs
Input Model: INPUT_1333
Zo
Layer
Width
40ohm
12
5.0mil
Zo
Layer
Width
40ohm
3
5.0mil
FreeScale P1021 IBIS Model: P1021 Ibis Model.ibs
Model: ddr3_drvr_40
L6 0.022” 0.022” 0.022”
Volts
MT41J64M16JT
DDR3-1333 AC150
VIHAC 900
VIHDC 850
VREF 750
VILDC 650
VILAC 600
tIS 190+75
tIH 140+50
1333 MT/s DDR3 Address/Clk Setup and Hold Margin