CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT III ...

CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN

UNIT III SYNCHRONOUS SEQUENTIAL LOGIC

Prof G ELANGOVAN Professor and Head

Department of Electrical and Electronics Engineering NPR College of Engineering and Technology

Natham, Dindigul Dist. 624 401

[email protected]

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• Sequential Circuits

• Storage Elements: Latches

• SR Latch

• D Latch

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Sequential Circuits • In sequential logic circuits, it consists of combinational

circuits to which storage elements are connected to form a feedback path.

• The storage elements are devices capable of storing binary information either 1 or 0.

• The information stored in the memory elements at any given time defines the present state of the sequential circuit.

• The present state and the external circuit determine the output and the next state of sequential circuits.

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The comparison bn. combinational and sequential circuits

S.No Combinational logic Sequential logic

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The output variable, at all times depends on the combination of input variables.

The output variable depends not only on the present input but also depend upon the past history of inputs.

2 Memory unit is not required

Memory unit is required to store the past history of input variables.

3 Faster in speed Slower than combinational circuits.

4 Easy to design Comparatively harder to design.

5 Eg. Parallel adder Eg. Serial adder

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Classification of Logic Circuits

• The sequential circuits can be classified depending on the timing of their signals:

Synchronous sequential circuits Asynchronous sequential circuits. • In synchronous sequential circuits, signals can affect the

memory elements only at discrete instants of time. • In asynchronous sequential circuits change in input signals

can affect memory element at any instant of time.

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S.No Synchronous sequential

circuits Asynchronous sequential

circuits

1 Memory elements are clocked Flip-Flops

Memory elements are either unclocked Flip-Flops or time delay elements.

2

The change in input signals can affect memory element upon activation of clock signal.

The change in input signals can affect memory element at any instant of time.

3 The maximum operating speed of clock depends on time delays involved.

Because of the absence of clock, it can operate faster than synchronous circuits.

4 Easier to design More difficult to design

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LATCHES

• A storage element in a digital circuit can maintain a binary state indefinitely, until directed by an input signal to switch states.

• Storage elements that operate with signal levels are referred to as latches .

• Those controlled by a clock transition are flip-flops .

• Latches are said to be level sensitive devices; flip-flops are edge-sensitive devices.

• The two types of storage elements are related because latches are the basic circuits from which all flip-flops are constructed.

• Latches are not practical for use as storage elements in synchronous sequential circuits.

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SR Latch

• The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates.

• It has two inputs labeled S for Set and R for Reset.

SR latch using NOR gates

• The two NOR gates are cross-coupled so that the output of NOR gate 1 is connected to one of the inputs of NOR gate 2 and vice versa.

• The latch has two outputs Q and Q’ and two inputs, set and reset.

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9

SR latch using NOR gates Logic Symbol

Logic Symbol

SR latch using NAND gates

S R Qn Qn+1 State 0 0

0 0

0 1

0 1

No Change (NC)

0 0

1 1

0 1

0 0

Reset

1 1

0 0

0 1

1 1

Set

1 1

1 1

0 1

x x

Indeterminate

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Set S

Reset R

Q

Q’

1

2

0

0

1

0

• Case 1: S= 0 and R= 0

Initially, Q= 1 and Q’= 0

Initially, Q= 0 and Q’= 1

• Case 2: S= 0 and R= 1

• Case 3: S= 1 and R= 0

• Case 4: S= 1 and R= 1

NOR Gate Truth Table

1

0

0

1

1 0

1 1

0

1

1

0

X

X

1

Truth Table SR Latch

0

1

0

1

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SR latch using NAND gates

• When S= 0 and R= 0, the output of both gates will produce 0. i.e., Qn+1= Qn+1’= 1.

• When S= 0 and R= 1, the latch is reset to 0.

• When S= 1 and R= 0, the latch is set to 1.

• When S= 1 and R= 1, the output, Qn+1 remains in its present state, Qn.

Gated SR Latch • In the SR latch, the output changes occur

immediately after the input changes i.e, the latch is sensitive to its S and R inputs all the time.

• A latch that is sensitive to the inputs only when an enable input is active. Such a latch with enable input is known as gated SR latch.

• The circuit behaves like SR latch when EN= 1. It retains its previous state when EN= 0

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SR Latch with enable input using NAND gates Logic Symbol

EN S R Qn Qn+1 State 1 1

0 0

0 0

0 1

0 1

No Change (NC)

1 1

0 0

1 1

0 1

0 0

Reset

1 1

1 1

0 0

0 1

1 1

Set

1 1

1 1

1 1

0 1

x x

Indeterminate *

0 0

x x

x x

0 1

0 1

No Change (NC)

Truth table of gated SR latch

• When S is HIGH and R is LOW, a HIGH on the EN input sets the latch. When S is LOW and R is HIGH, a HIGH on the EN input resets the latch.

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D Latch • In SR latch, when both inputs are same (00 or

11), the output either does not change or it is invalid.

• In many practical applications, these input conditions are not required.

• These input conditions can be avoided by making them complement of each other.

• This modified SR latch is known as D latch.

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• D input goes directly to the S input, and its complement is applied to the R input. Therefore, only two input conditions exists, either S=0 and R=1 or S=1 and R=0.

• D latch is called transparent latch

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D Latch Logic Symbol

When D is HIGH and EN is HIGH. Q goes HIGH. When D is LOW and EN is HIGH, Q goes LOW. When EN is LOW, the state of the latch is not affected by the D input.

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Sequential Circuits

Storage Elements: Latches

SR Latch

D Latch

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Department of Computer Science and Engineering NPR College of Engineering and Technology


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19


• Triggering of Flip-Flops

• Edge Triggered Flip-Flops

• SR Flip-Flops

• JK Flip-Flops

• D Flip-Flops

• T Flip-Flops

• Characteristic table and Characteristic equation of Flip-Flops

• Master-Slave JK Flip-Flop

• Excitation Table 20

Triggering of FLIP-FLOPS • The state of a Flip-Flop is switched by a momentary

change in the input signal. • This momentary change is called a trigger and the

transition it causes is said to trigger the Flip-Flop. • Clocked Flip-Flops are triggered by pulses. • A clock pulse starts from an initial value of 0, goes

momentarily to 1and after a short time, returns to its initial 0 value.

• Latches are controlled by enable signal, and they are level triggered, either positive level triggered or negative level triggered. The output is free to change according to the S and R input values, when active level is maintained at the enable input.

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Edge Triggered FLIP-FLOPS • Flip-Flops are synchronous bistable devices (has two

outputs Q and Q’). • Synchronous - The output changes state only at a

specified point on the triggering input (CLK), i.e., changes in the output occur in synchronization with the clock.

• An edge-triggered Flip-Flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock.

• The different types of edge-triggered Flip- Flops are— 1. S-R Flip-Flop, 2. J-K Flip-Flop, 3. D Flip-Flop, 4. T Flip-Flop.

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S-R Flip-Flop • The S and R inputs of the S-R Flip-Flop are called

synchronous • The circuit is similar to SR latch except enable

signal is replaced by clock pulse (CLK). • On the positive edge of the clock pulse, the

circuit responds to the S and R inputs.

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CLK S R Qn Qn+1 State 1 1

0 0

0 0

0 1

0 1

No Change (NC)

1 1

0 0

1 1

0 1

0 0

Reset

1 1

1 1

0 0

0 1

1 1

Set

1 1

1 1

1 1

0 1

x x

Indeterminate *

0 0

x x

x x

0 1

0 1

No Change (NC)

Truth table for SR Flip-Flop

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Input and output waveforms of SR Flip-Flop

J-K Flip-Flop • JK means Jack Kilby, (TI) Engineer, 1958.

• JK Flip-Flop has two inputs J(set) and K(reset).

• A JK Flip-Flop can be obtained from the clocked SR Flip-Flop by augmenting two AND gates as shown below.

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• The data input J and the output Q’ are applied to the first AND gate and its output (JQ’) is applied to the S input of SR Flip-Flop.

• Similarly, the data input K and the output Q are applied to the second AND gate and its output (KQ) is applied to the R input of SR Flip-Flop.

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J= K= 0

When J=K= 0, both AND gates are disabled. Clock pulse have no effect, hence the Flip-Flop output is same as the previous output.

J= 0, K= 1

When J= 0 and K= 1, AND gate 1 is disabled i.e., S= 0 and R= 1. This condition will reset the Flip-Flop to 0.

J= 1, K= 0

When J= 1 and K= 0, AND gate 2 is disabled i.e., S= 1 and R= 0. Therefore the Flip-Flop will set on the application of a clock pulse.

J= K= 0

When J=K= 1, it is possible to set or reset the Flip-Flop.

If Q is High, AND gate 2 passes on a reset pulse to the next clock.

When Q is low, AND gate 1 passes on a set pulse to the next clock.

Either way, Q changes to the complement of the last state i.e., toggle.

Toggle means to switch to the opposite state. The truth table of JK Flip-Flop is given below. 29

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1 CLK 2 3 4 5

J

K

Qn

1

1

0

D Flip-Flop • Like in D latch, in D Flip-Flop the basic SR Flip-

Flop is used with complemented inputs. The D Flip-Flop is similar to D-latch except clock pulse is used instead of enable input.

• To eliminate the undesirable condition of the indeterminate state in the RS Flip-Flop is to ensure that inputs S and R are never equal to 1 at the same time.

• This is done by D Flip-Flop. The D (delay) Flip-Flop has one input called delay input and clock pulse input. The D Flip-Flop using SR Flip-Flop is shown below.

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T Flip-Flop • The T (Toggle) Flip-Flop is a modification of the JK Flip-

Flop. • It is obtained from JK Flip-Flop by connecting both inputs J

and K together, i.e., single input. • Regardless of the present state, the Flip-Flop

complements its output when the clock pulse occurs while input T= 1.

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• When T= 0, Qn+1= Qn, ie., the next state is the same as the present state and no change occurs.

• When T= 1, Qn+1= Qn’, ie., the next state is the complement of the present state.

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Characteristic table and Characteristic equation

• A characteristic table defines the logical properties of a flip-flop by describing its operation in tabular form

• They define the next state as a function of the inputs and the present state.

• Q (t) refers to the present state. Q(t + 1) is the next state one clock period later.

• Q(t) denotes the state of the flip-flop immediately before the clock edge, and Q(t + 1) denotes the state that results from the clock transition.

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Qn J K Qn+1

0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0

36 Characteristic Table

K-map Simplification

Characteristic equation Qn+1= JQ’+ K’Q.

Qn D Qn+1

0 0 0 0 1 1 1 0 0 1 1 1

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Characteristic equation Qn+1= D.

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Characteristic equation Qn+1= TQn’+ T’Qn

Master-Slave JK Flip-Flop

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EXCITATION TABLE

• The characteristic table is useful for analysis and for defining the operation of the Flip-Flop.

• It specifies the next state (Qn+1) when the inputs and present state are known.

• The excitation or application table is useful for design process.

• It is used to find the Flip-Flop input conditions that will cause the required transition, when the present state (Qn) and the next state (Qn+1) are known.

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Present State

Next State

Inputs

Qn Qn+1 S R 0 0 0 x 0 1 1 0 1 0 0 1 1 1 x 0 41

SR Flip-Flop Excitation Table

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Present State

Next State

Inputs

Qn Qn+1 J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0

JK Flip-Flop Excitation Table

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Present State

Next State

Inputs

Qn Qn+1 D 0 0 0 0 1 1 1 0 0 1 1 1

D Flip-Flop Excitation Table

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Present State

Next State

Inputs

Qn Qn+1 T 0 0 0 0 1 1 1 0 1 1 1 0

T Flip-Flop Excitation Table

UNIT III SYNCHRONOUS SEQUENTIAL LOGIC Triggering of Flip-Flops

Edge Triggered Flip-Flops

SR Flip-Flops

JK Flip-Flops

D Flip-Flops

T Flip-Flops

Characteristic table and Characteristic equation of Flip-Flops

Master-Slave JK Flip-Flop

Excitation Table 45






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46


47

• Realization of One Flip-Flop using Other Flip-Flops – SR Flip-Flop to D Flip-Flop – SR Flip-Flop to JK Flip-Flop – SR Flip-Flop to T Flip-Flop – JK Flip-Flop to T Flip-Flop – JK Flip-Flop to D Flip-Flop – D Flip-Flop to T Flip-Flop – T Flip-Flop to D Flip-Flop

• Classification of Synchronous Sequential Circuit

SR Flip-Flop to D Flip-Flop

• Write the characteristic table for required Flip-Flop (D Flip-Flop).

• Write the excitation table for given Flip-Flop (SR Flip-Flop).

• Determine the expression for the given Flip-Flop inputs (S and R) by using K- map.

• Draw the Flip-Flop conversion logic diagram to obtain the required Flip- Flop (D Flip-Flop) by using the above obtained expression.

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SR Flip-Flop to JK Flip-Flop

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Inputs Present state

Next state

Flip-Flop Input

J K Qn Qn+1 S R 0 0 0 0 0 x 0 0 1 1 x 0 0 1 0 0 0 x 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 x 0 1 1 0 1 1 0 1 1 1 0 0 1

SR Flip-Flop to T Flip-Flop

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JK Flip-Flop to T Flip-Flop

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JK Flip-Flop to D Flip-Flop

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D Flip-Flop to T Flip-Flop

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T Flip-Flop to D Flip-Flop

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Classification of Synchronous Sequential Circuit

• Moore model: The output depends only on the present state of the Flip-Flops.

• Output appears only after the clock pulse is applied, i.e., it varies in synchronism with the clock input.

• Mealy model: The output depends on both the present state of the Flip-Flops and on the inputs.

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57

Moore model

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Mealy model

Difference between Moore and Mealy model

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Realization of One Flip-Flop using Other Flip-Flops SR Flip-Flop to D Flip-Flop SR Flip-Flop to JK Flip-Flop SR Flip-Flop to T Flip-Flop JK Flip-Flop to T Flip-Flop JK Flip-Flop to D Flip-Flop D Flip-Flop to T Flip-Flop T Flip-Flop to D Flip-Flop

Classification of Synchronous Sequential Circuit






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• Analysis of Clocked Sequential Circuits

• State Diagram

• State Table

• State Equation

• Analysis Procedure

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Analysis of Clocked Sequential Circuits

• The behavior of a sequential circuit is determined from the inputs, outputs and the state of its Flip-Flops.

• The outputs and the next state are both a function of the inputs and the present state.

• The analysis of a sequential circuit consists of obtaining a table or diagram from the time sequence of inputs, outputs and internal states.

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State Diagram • State diagram is a pictorial representation of a

behavior of a sequential circuit. • A state is represented by a circle and the transition

between states is indicated by directed lines connecting the circles.

• A directed line connecting a circle with circle with itself indicates that next state is same as present state.

• The binary number inside each circle identifies the state represented by the circle.

• The directed lines are labeled with two binary numbers separated by a symbol ‘/’.

• Input value / output value

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• Moore circuit, the directed lines are labeled with only one binary number representing the state of the input that causes the state transition.

• The output state is indicated within the circle, below the present state because output state depends only on present state and not on the input.

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State Table

• State table represents relationship between input, output and Flip-Flop states.

• It consists of three sections labeled present state, next state and output.

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• In case of Moore circuit, the output section has only one column since output does not depend on input

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State Equation

• The behavior of a clocked sequential circuit can be described algebraically by means of state equations.

• A state equation or transition equation specifies the next state as a function of the present state and inputs.

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Analysis Procedure

• The synchronous sequential circuit analysis is

summarizes as given below: 1. Assign a state variable to each Flip-Flop in the

synchronous sequential circuit. 2. Write the excitation input functions for each Flip-

Flop and also write the Moore/ Mealy output equations.

3. Substitute the excitation input functions into the bistable equations for the Flip-Flops to obtain the next state output equations.

4. Obtain the state table and reduced form of the state table.

5. Draw the state diagram by using the second form of state table. 69

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Example of sequential circuit

• It consists of two D flip-flops A and B, an input x and an output y .

State Equations

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Present State

Input Next State Output

A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0

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State Table First Form

Present State

Next State Output X = 0 X = 1 X = 0 X = 1

A B A B A B y y 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0

State Table Second Form

State Diagram

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00 10

11 01 1/0

0/1 1/0

1/0 1/0 0/1 0/1

0/0

Circuit diagram Equations State table State diagram

Flip-Flop Input Equations • Sequential circuit consists of flip-flops and gates.

• The part of the combinational circuit that generates external outputs is described algebraically by a set of Boolean functions called output equations .

• The part of the circuit that generates the inputs to flip-flops is described algebraically by a set of Boolean functions called flip-flop input equations or excitation equations .

• flip-flop input symbol to denote the input equation variable and a subscript to designate the name of the flip-flop output.

• For example, the following input equation specifies an OR gate with inputs x and y connected to the D input of a flip-flop whose output is labeled with the symbol Q

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Analysis with D Flip-Flops • The circuit to analyze is

described by the input equation

• No output equations are given, which implies that the output comes from the output of the flip-flop.

• The logic diagram is obtained from the input equation and is

• The next-state values are obtained from the state equation

• The expression specifies an odd function

• The circuit has one flip-flop and two states.

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Analysis with JK Flip-Flops • A state table consists of four sections: present state, inputs,

next state, and outputs. • The first two are obtained by listing all binary combinations.

The output section is determined from the output equations.

• The next-state values are evaluated from the state equations.

• For a D -type flip-flop, the state equation is the same as the input equation.

• The next-state values of a sequential circuit that uses JK - or T -type flip-flops can be derived as follows:

1. Determine the flip-flop input equations in terms of the present state and input variables.

2. List the binary values of each input equation. 3. Use the corresponding flip-flop characteristic table to

determine the next-state values in the state table.

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• Two JK flip-flops A and B and one input x, the circuit has no outputs

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• The characteristic equations for the flip-flops are obtained by substituting A or B for the name of the flip-flop, instead of Q :

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• Substituting the values of JA, KA and JB, KB from the input equations, we obtain the state equations for A and B :

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Analysis with T Flip-Flops

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• The characteristic equation

• It has two flip-flops A and B, one input x, and one output y and can be described algebraically by two input equations and an output equation:

• The next-state values for A and B

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Analysis of Clocked Sequential Circuits

State Diagram

State Table

State Equation

Analysis Procedure

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• State Reduction

• State Assignment

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State Reduction and Assignment • The state reduction is used to avoid the redundant

states in the sequential circuits.

• The reduction in redundant states reduces the number of required Flip- Flops and logic gates, reducing the cost of the final circuit.

• The two states are said to be redundant or equivalent, if every possible set of inputs generate exactly same output and same next state.

• When two states are equivalent, one of them can be removed without altering the input-output relationship.

• Since ‘n’ Flip-Flops produced 2n state, a reduction in the number of states may result in a reduction in the number of Flip-Flops.

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State a a b c d e f f g f g a

input 0 1 0 1 0 1 1 0 1 0 0

output 0 0 0 0 0 1 1 0 1 0 0

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Input sequence 0 1 0 1 0 1 1 0 1 0 0 Initial state a .

Present State

Next State Output

x = 0 x = 1 x = 0 x = 1

a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f g f 0 1

g a f 0 1

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• “Two states are said to be equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state.”

• When two states are equivalent, one of them can be removed without altering the input–output relationships.

e and g

are equal e e

d and f

are equal d

d d d

C and e

are nt equal

State Table Reducing the State Table Reduced State Table

Reduced State Diagram

State Assignment

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Determine a minimal state table equivalent furnished below

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Reduced State Table


State Reduction

State Assignment

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• Design Procedure

• Design using D Flip-Flops

• Design using SR Flip-Flops

• Design using JK Flip-Flops

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Design Procedure 1. The given problem is determined with a state

diagram.

2. From the state diagram, obtain the state table.

3. The number of states may be reduced by state reduction methods (if applicable).

4. Assign binary values to each state (Binary Assignment) if the state table contains letter symbols.

5. Determine the number of Flip-Flops and assign a letter symbol (A, B, C,…) to each.

6. Choose the type of Flip-Flop (SR, JK, D, T) to be used.

7. Using K-map or any other simplification method, derive the circuit output functions and the Flip-Flop input functions.

8. Draw the logic diagram. 94

• A sequential circuit has one input and one output. The state diagram is shown below. Design the sequential circuit with a) D-Flip-Flops, b) T Flip-Flops, c) RS Flip-Flops and d) JK Flip-Flops.

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The state table for the state diagram

State reduction

The state table shows that circuit goes through four states, therefore we require 2 Flip-Flops (number

of states= 2m, where m= number of Flip-Flops)

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Present State

Next State Output x = 0 x = 1 x = 0 x = 1

AB AB AB Y Y 00 00 10 0 1 01 11 00 0 0 10 10 01 1 0 11 00 10 1 0

Design using D Flip-Flops

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PS NS Inputs Qn Qn+1 D 0 0 0 0 1 1 1 0 0 1 1 1

Present state

Input Next state

Flip-Flop Inputs

Output

A B x A B DA DB Y 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0

Excitation table for D Flip-Flop

Circuit excitation table

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Logic diagram of given sequential circuit using D Flip-Flop


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Circuit Excitation Table

Excitation Table for T Flip-Flop

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Logic diagram of given sequential circuit using T Flip-Flop

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Design using SR Flip-Flops

Excitation table for SR Flip-Flop


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Logic diagram of given sequential circuit using SR Flip-Flop

Design using JK Flip-Flops

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PS NS Inputs Qn Qn+1 J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0


Excitation table for JK Flip-Flop

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Logic diagram of given sequential circuit using JK Flip-Flop

Design a clocked sequential machine using JK Flip-Flops for the state diagram shown in the figure. Use state reduction if possible. Make proper state assignment.

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Present State

Next State Output x = 0 x = 1 x = 0 x = 1

a a b 0 0 b c b 0 1 c a b 0 1 d a b 0 1

State Table

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Reduced State table

Binary Assignment

a= 00 b= 01 and c= 10

Reduced State Diagram

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PS NS Inputs Qn Qn+1 J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0

Excitation table for JK Flip-Flop


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Logic diagram of given sequential circuit using JK Flip-Flop


Design Procedure

Design using D Flip-Flops

Design using SR Flip-Flops

Design using JK Flip-Flops

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• Registers

• Shift Registers

• Universal Shift Registers

• Serial Transfer

• Serial Addition

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Registers • A register is a group of flip‐flops, each one of

which shares a common clock and is capable of storing one bit of information.

OR • A Register consists of a group of flip‐flops

together with gates that affect their operation. The flip‐flops hold the binary information, and the gates determine how the information is transferred into the register.

• An n ‐bit register consists of a group of n flip‐flops capable of storing n bits of binary information.

• For instance, a register used to store an 8-bit binary number must have 8 Flip-Flops.

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Shift Registers • A register is simply a group of Flip-Flops that can be

used to store a binary number. • The Flip-Flops must be connected such that the binary

number can be entered (shifted) into the register and possibly shifted out.

• A group of Flip-Flops connected to provide either or both of these functions is called a shift register

• The bits in a binary number (data) can be moved from one place to another in either of two ways.

• Shifting the data one bit at a time in a serial fashion, beginning with either the most significant bit (MSB) or the least significant bit (LSB). This technique is referred to as serial shifting.

• The second method involves shifting all the data bits simultaneously and is referred to as parallel shifting.

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i. Serial in- serial out SISO

ii. Serial in- parallel out SIPO

iii. Parallel in- serial out PISO

iv. Parallel in- parallel out PIPO

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Serial-In Serial-Out Shift Register

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Four bits 1010 being entered serially into the register

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Four bits 1010 being entered serially-shifted out of the register and replaced by all zeros

Serial-In Parallel-Out Shift Register

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Four bits 1111 being serially entered into the register

Parallel-In Parallel-Out Shift Register

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Parallel-In Serial-Out Shift Register

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0 0 0 0

0 0 0

1 1 1 1

X0 X1 X2 X3

1

1 1 1

0 0 0 0

Q0 Q1 Q2 0

• BI-DIRECTION SHIFT REGISTERS

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UNIVERSAL SHIFT REGISTERS

• A register capable of shifting in one direction only is a unidirectional shift register.

• One that can shift in both directions is a bidirectional shift register.

• If the register has both shifts and parallel‐load capabilities, it is referred to as a universal shift register.

1. A clear control to clear the register to 0.

2. A clock input to synchronize the operations.

3. A shift-right control to enable the shift right operation and the serial input and output lines associated with the shift right.

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4. A shift-left control to enable the shift left operation and the serial input and output lines associated with the shift left.

5. A parallel-load control to enable a parallel transfer and the n input lines associated with the parallel transfer.

6. ‘n’ parallel output lines. 7. A control line that leaves the information in the

register unchanged even though the clock pulses re continuously applied.

126 Function Table

127

0 0

0 0 0 0 A3 A2 A1 A0

0 1

1 1 1 1 IP A3 A2 A1

1 0

2 2 2 2 A2 A1 A0 IP

1 1

3 3 3 3 I3 I2 I1 I0

Serial Transfer

• The data path of a digital system is said to operate in serial mode when information is transferred and manipulated one bit at a time.

• Information is transferred one bit at a time by shifting the bits out of the source register and into the destination register.

• This type of transfer is in contrast to parallel transfer, whereby all the bits of the register are transferred at the same time.

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Serial transfer from register A to register B

Serial Addition

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Registers

Shift Registers

Universal Shift Registers

Serial Transfer

Serial Addition

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[email protected]

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• Counters

• Synchronous Binary Counter

• Synchronous Decade Counter / BCD Counter

• Synchronous UP/DOWN Counter

• Ripple Counters

• Modulus-N-Counters

• Binary Counter with Parallel Load

• Counter with Unused States

• Ring Counter

• Johnson Counter

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Counters • A counter is essentially a register that goes through a

predetermined sequence of binary states.

• The gates in the counter are connected in such a way as to produce the prescribed sequence of states.

• Counters are classified as

Asynchronous counters

Synchronous counters

• In asynchronous (ripple) counters, the first Flip-Flop is clocked by the external clock pulse and then each successive Flip-Flop is clocked by the output of the preceding Flip-Flop.

• In synchronous counters, the clock input is connected to all of the Flip-Flops so that they are clocked simultaneously.

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S.No

Asynchronous (ripple) counter

Synchronous counter

1 All the Flip-Flops are not clocked simultaneously.

All the Flip-Flops are clocked simultaneously.

2

The delay times of all Flip- Flops are added. Therefore there is considerable propagation delay.

There is minimum propagation delay.

3 Speed of operation is low Speed of operation is high.

4 Logic circuit is very simple even for more number of states.

Design involves complex logic circuit as number of state increases.

5 Minimum numbers of logic devices are needed.

The number of logic devices is more than ripple counters.

6 Cheaper than synchronous counters.

Costlier than ripple counters.

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136

1 CLK 2 3 4 5

Q0 1

1

0

2-Bit Synchronous Binary Counter

Q1 0

1 1 0 0

0 1 0 0


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138

4-Bit Synchronous Decade Counter / BCD Counter

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CLOCK Pulse Q3 Q2 Q1 Q0 Initially

1 2 3 4 5 6 7 8 9

10(recycles)

0 0 0 0 0 0 0 0 1 1 0

0 0 0 0 1 1 1 1 0 0 0

0 0 1 1 0 0 1 1 0 0 0

0 1 0 1 0 1 0 1 0 1 0

• FF0 (Q0) toggles on each clock pulse, so the logic equation for its J0 and K0 inputs is

J0= K0= 1 • FF1 (Q1) changes on the next clock pulse each time Q0

= 1 and Q3 = 0, so the logic equation for the J1 and K1 inputs is

J1= K1= Q0Q3’ • Flip-Flop 2 (Q2) changes on the next clock pulse each

time both Q0 = Q1 = 1. This requires an input logic equation as follows

J2= K2= Q0Q1 • FF3 (Q3) changes to the opposite state on the next

clock pulse each time Q0 = 1, Q1 = 1, and Q2 = 1 (state 7), or when Q0 = 1 and Q1 = 1 (state 9). The equation for this is as follows

J3= K3= Q0Q1Q2+ Q0Q3

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141

Synchronous UP/DOWN Counter • An up/down counter is a bidirectional counter, capable of

progressing in either direction through a certain sequence. • A 3-bit binary counter that advances upward through its

sequence (0, 1, 2, 3, 4, 5, 6, 7) • and then can be reversed so that it goes through the

sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1,0).

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J0= K0= 1

J1= K1= (Q0.UP) + (Q0’.DOWN)

J2= K2= (Q0. Q1.UP) + (Q0’.Q1’.DOWN)

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Ripple Counters • In a ripple counter, a

flip‐flop output transition serves as a source for triggering other flip‐flops.

• In other words, the C input of some or all flip‐flops are triggered, not by the common clock pulses, but rather by the transition that occurs in other flip‐flop outputs.

144 With T flip-flops With D flip-flops

MODULUS-N-COUNTERS

• The counter with ‘n’ Flip-Flops has maximum MOD number 2n.

• Find the number of Flip-Flops (n) required for the desired MOD number (N) using the equation 2n ≥ N

• A 3 bit binary counter is a MOD 8 counter. The basic counter can be modified to produce MOD numbers less than 2

n by allowing the counter to

skip those are normally part of counting sequence.

• n= 3 N= 8

145

MOD 5 Counter

2n

= N = 5

22 = 4 less than N

23 = 8 > N(5)

Therefore, 3 Flip-Flops are required.

MOD 10 Counter

2n

= N = 10

23 = 8 less than N

24 = 16 > N(10)

Therefore, 4 Flip-Flops are required. 146

• To construct any MOD-N counter, the following methods can be used.

1. Find the number of Flip-Flops (n) required for the desired MOD number (N) using the equation,

2n ≥ N. 2. Connect all the Flip-Flops as a required counter. 3. Find the binary number for N. 4. Connect all Flip-Flop outputs for which Q= 1

when the count is N, as inputs to NAND gate. 5. Connect the NAND gate output to the CLR input

of each Flip-Flop. When the counter reaches Nth state, the output

of the NAND gate goes LOW, resetting all Flip-Flops to 0. Therefore the counter counts from 0 through N-1.

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• MOD-10 counter reaches state 10 (1010). i.e.,

• Q3Q2Q1Q0= 1 0 1 0. The outputs Q3 and Q1 are connected to the NAND gate and the output of the NAND gate goes LOW and resetting all Flip-Flops to zero.

• Therefore MOD-10 counter counts from 0000 to 1001. And then recycles to the zero value

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Mod-10 Counter / BCD ripple counter

• The BCD counter is a decade counter, since it counts from 0 to 9.

• To count in decimal from 0 to 99, we need a two‐decade counter.

• To count from 0 to 999, we need a three‐decade counter.

• Multiple decade counters can be constructed by connecting BCD counters in cascade, one for each decade.

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Block diagram of a three‐decade decimal BCD counter

Binary Counter with Parallel Load

• Counters employed in digital systems quite often require a parallel‐load capability for

• transferring an initial binary number into the counter prior to the count operation.

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Function Table for the Counter Block Diagram

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Counter with Unused States • A circuit with n flip‐flops has 2n binary states. • There are occasions when a sequential circuit uses fewer

than this maximum possible number of states. • States that are not used in specifying the sequential circuit

are not listed in the state table. • In simplifying the input equations, the unused states may

be treated as don’t‐care conditions or may be assigned specific next states.

• It is important to realize that once the circuit is designed and constructed, outside interference during its operation may cause the circuit to enter one of the unused states.

• In that case, it is necessary to ensure that the circuit eventually goes into one of the valid states so that it can resume normal operation.

• Otherwise, if the sequential circuit circulates among unused states, there will be no way to bring it back to its intended sequence of state transitions.

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153

Ring Counter • A ring counter is a circular shift register with only one

flip‐flop being set at any particular time; all others are cleared.

• The single bit is shifted from one flip‐flop to the next to produce the sequence of timing signals.

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Johnson Counter • A k ‐bit ring counter circulates a single bit among

the flip‐flops to provide k distinguishable states.

• The number of states can be doubled if the shift register is connected as a switch‐tail ring counter.

• A switch‐tail ring counter is a circular shift register with the complemented output of the last flip‐flop connected to the input of the first flip‐flop.

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UNIT III SYNCHRONOUS SEQUENTIAL LOGIC Counters

Synchronous Binary Counter

Synchronous Decade Counter / BCD Counter

Synchronous UP/DOWN Counter

Ripple Counters

Modulus-N-Counters

Binary Counter with Parallel Load

Counter with Unused States

Ring Counter

Johnson Counter

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[email protected]

158


• HDL Models of Sequential Circuits

• Flip-Flops and Latches

• Sequential Circuit

• Registers and Counters

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HDL Models of Sequential Circuits

Behavioral Modeling in SSD

• There are two kinds of behavioral statements in Verilog HDL: initial and always.

• The initial behavior executes once beginning at time=0.

• The always behavior executes repeatedly and re-executes until the simulation terminates.

• A behavior is declared within a module by using the keywords initial or always, followed by a statement or a block of statements enclosed by the keywords begin and end.

160

• An example of a free-running clock initial begin clock = 1’b0;

repeat (30);

#10 clock = ~clock;

end initial begin clock = 1’b0;

#300 $finish;

end always #10 clock = ~clock

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• The always statement can be controlled by delays that wait for a certain time or by certain conditions to become true or by events to occur.

• This type of statement is of the form:

always @ (event control expression)

Procedural assignment statements

• The event control expression specifies the condition that must occur to activate the execution of the procedural assignment statements.

• The variables in the left-hand side of the procedural statements must be of the reg data type and must be declared as such.

• The statements within the block, after the event control expression, execute sequentially and the execution suspends after the last statement has executed.

• Then the always statement waits again for an event to occur.

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• Two kind of events: – Level sensitive

always @(A or B or Reset) will cause the execution if changes occur in A or B or Reset.

– Edge-triggered always @(posedge clock or negedge reset)will cause the

execution if the clock goes through a positive transition or if the reset goes through a negative transition.

• A procedural assignment is an assignment within an initial or always statement.

• There are two kinds of procedural assignments: blocking and non-blocking – Blocking assignments (executed sequentially in the order they are

listed in a sequential block)

• B = A

• C = B + 1

– Non-blocking assignments (evaluate the expressions on the right hand side, but do not make the assignment to the left hand side until all expressions are evaluated.

• B <= A

• C <= B + 1 163

Flip-Flops and Latches

module D_latch(Q,D,control);

output Q;

input D,control;

reg Q;

always @(control or D)

if(control) Q = D; //Same as: if(control=1)

endmodule 164

165

//D flip-flop

module D_FF (Q,D,CLK);

output Q;

input D,CLK;

reg Q;

always @(posedge CLK)

Q = D;

endmodule

//D flip-flop with asynchronous reset.

module DFF (Q,D,CLK,RST);

output Q;

input D,CLK,RST;

reg Q;

always @(posedge CLK or negedge RST)

if (~RST) Q = 1'b0; // Same as: if (RST = 0)

else Q = D;

endmodule

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//T flip-flop from D flip-flop and gates

module TFF (Q,T,CLK,RST);

output Q;

input T,CLK,RST;

wire DT;

assign DT = Q ^ T ;

//Instantiate the D flip-flop

DFF TF1 (Q,DT,CLK,RST);

endmodule

//JK flip-flop from D flip-flop and gates

module JKFF (Q,J,K,CLK,RST);

output Q;

input J,K,CLK,RST;

wire JK;

assign JK = (J & ~Q) | (~K & Q);

//Instantiate D flipflop

DFF JK1 (Q,JK,CLK,RST);

endmodule

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// Functional description of JK // flip-flop

module JK_FF (J,K,CLK,Q,Qnot);

output Q,Qnot;

input J,K,CLK;

reg Q;

assign Qnot = ~ Q ;

always @(posedge CLK)

case({J,K})

2'b00: Q = Q;

2'b01: Q = 1'b0;

2'b10: Q = 1'b1;

2'b11: Q = ~ Q;

endcase

endmodule

• Here the flip-flop is described using the characteristic table rather than the characteristic equation.

• The case multiway branch condition checks the 2-bit number obtained by concatenating the bits of J and K.

• The case value ({J,K}) is evaluated and compared with the values in the list of statements that follow.

//Positive Edge triggered DFF with Reset

module DFF(CLK,RST,D,Q);

input CLK,RST,D;

output Q;

reg Q;

always@(posedge CLK or posedge RST)

if (RST) Q<=0;

else Q<=D;

endmodule

168

Sequential Circuit

169

//Mealy state diagram for the circuit

module Mealy_mdl (x,y,CLK,RST);

input x,CLK,RST;

output y;

reg y;

reg [1:0] Prstate,Nxtstate;

parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;

always@(posedge CLK or negedge RST)

if (~RST) Prstate = S0; //Initialize to state S0

else Prstate = Nxtstate; //Clock operations

170

always @(Prstate or x) //Determine next state case (Prstate) S0: if (x) Nxtstate = S1; S1: if (x) Nxtstate = S3; else Nxtstate = S0; S2: if (~x)Nxtstate = S0; S3: if (x) Nxtstate = S2; else Nxtstate = S0; endcase always @(Prstate or x) //Evaluate output case (Prstate) S0: y = 0; S1: if (x) y = 1'b0; else y = 1'b1; S2: if (x) y = 1'b0; else y = 1'b1; S3: if (x) y = 1'b0; else y = 1'b1; endcase endmodule

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172

//Moore state diagram module Moore_mdl (x,AB,CLK,RST); input x,CLK,RST; output [1:0]AB; reg [1:0] state; parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11; always @(posedge CLK or negedge RST) if (~RST) state = S0; //Initialize to state S0 else case(state) S0: if (~x) state = S1; S1: if (x) state = S2; else state = S3; S2: if (~x) state = S3; S3: if (~x) state = S0; endcase assign AB = state; //Output of flip-flops endmodule

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174

//Structural description of sequential circuit

module Tcircuit (x,y,A,B,CLK,RST);

input x,CLK,RST;

output y,A,B;

wire TA,TB;

//Flip-flip input equations

assign TB = x,

TA = x & B;

//Output equation

assign y = A & B;

//Instantiate T flip-flops

T_FF BF (B,TB,CLK,RST);

T_FF AF (A,TA,CLK,RST);

endmodule

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176

//T flip-flop

module T_FF (Q,T,CLK,RST);

output Q;

input T,CLK,RST;

reg Q;

always@(posedge CLK or negedge RST)

if(~RST) Q=1'b0;

else Q=Q^T;

endmodule

//Stimulus for testing seq. cir

module testTcircuit;

reg x,CLK,RST; //inputs for circuit

wire y,A,B; //output from circuit

Tcircuit TC(x,y,A,B,CLK,RST); initial begin RST = 0; CLK = 0; #5 RST = 1; repeat (16) #5 CLK = ~CLK; end initial begin x = 0; #15 x = 1; repeat (8) #10 x = ~ x; end endmodule

HDL for Registers and Counters • Registers and counters can be described in HDL at

either the behavioral or the structural level.

• In the behavioral, the register is specified by a description of the various operations that it performs similar to a function table.

• A structural level description shows the circuit in terms of a collection of components such as gates, flip-flops and multiplexers.

• The various components are instantiated to form a hierarchical description of the design similar to a representation of a logic diagram

177

//Behavioral description of Universal shift register module shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr); input s1,s0; //Select inputs input lfin, rtin; //Serial inputs input CLK,Clr; //Clock and Clear input [3:0] Pin; //Parallel input output [3:0] A; //Register output reg [3:0] A; always @ (posedge CLK or negedge Clr) if (~Clr) A = 4'b0000; else case ({s1,s0}) 2'b00: A = A; //No change 2'b01: A = {rtin,A[3:1]}; //Shift right 2'b10: A = {A[2:0],lfin}; //Shift left //Parallel load input 2'b11: A = Pin; endcase endmodule 178

//Structural description of Universal shift register

module SHFTREG (I,select,lfin,rtin,A,CLK,Clr);

input [3:0] I; //Parallel input

input [1:0] select; //Mode select

input lfin,rtin,CLK,Clr; //Serial input,clock,clear

output [3:0] A; //Parallel output

//Instantiate the four stages

stage ST0 (A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);

stage ST1 (A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);

stage ST2 (A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);

stage ST3 (A[3],rtin,A[2],I[3],A[3],select,CLK,Clr);

endmodule

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//One stage of shift register

module stage(i0,i1,i2,i3,Q,select,CLK,Clr);

input i0,i1,i2,i3,CLK,Clr;

input [1:0] select;

output Q;

reg Q,D;

//4x1 multiplexer

always @ (i0 or i1 or i2 or i3 or select)

case (select)

2'b00: D = i0;

2'b01: D = i1;

2'b10: D = i2;

2'b11: D = i3;

endcase

180

//D flip-flop

always@(posedge CLK or negedge Clr)

if (~Clr) Q = 1'b0;

else Q = D;

endmodule

//Binary counter with parallel load

module counter (Count,Load,IN,CLK,Clr,A,CO);

input Count,Load,CLK,Clr;

input [3:0] IN; //Data input

output CO; //Output carry

output [3:0] A; //Data output

reg [3:0] A;

assign CO = Count & ~Load & (A == 4'b1111);

always @(posedge CLK or negedge Clr)

if (~Clr) A = 4'b0000;

else if (Load) A = IN;

else if (Count) A = A + 1'b1;

else A = A; // no change, default condition

endmodule

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//Ripple counter

module ripplecounter(A0,A1,A2,A3,Count,Reset);

output A0,A1,A2,A3;

input Count,Reset;

//Instantiate complementing flip-flop

CF F0 (A0,Count,Reset);

CF F1 (A1,A0,Reset);



endmodule

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//Complementing flip-flop with delay

//Input to D flip-flop = Q'

module CF (Q,CLK,Reset);

output Q;

input CLK,Reset;

reg Q;

always@(negedge CLK or posedge Reset)

if(Reset) Q=1'b0;

else Q=#2 (~Q);//Delay of 2 time units

endmodule

//Stimulus for testing ripple counter module testcounter; reg Count; reg Reset; wire A0,A1,A2,A3; //Instantiate ripple counter ripplecounter RC (A0,A1,A2,A3,Count,Reset); always #5 Count = ~Count; initial begin Count = 1'b0; Reset = 1'b1; #4 Reset = 1'b0; #165 $finish; end endmodule

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HDL Models of Sequential Circuits

Flip-Flops and Latches

Sequential Circuit

Registers and Counters

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End of Unit III

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CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT III ...

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