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UNIT I OVERVIEW & INSTRUCTIONS

1. Define Moores Law

The one constant for computer designers is rapid change, which is driven largely by MooresLaw. It states that integrated circuit resources double every 1824 months.

2. Define Transistor, VLSITransistor: An on/off switch controlled by an electric signal.Very large-scale integrated (VLSI) circuit: A device containing hundreds of thousands to

millions of transistors.

3. Define the term Silicon crystal ingot, Wafer.A rod composed of a silicon crystal that is between 8 and 12 inches in diameter and about 12to 24 inches long is called Silicon crystal ingot.

Wafer: A slice from a silicon ingot no more than 0.1 inches thick, used to create chips.

4. What is meant by response time?It is also called execution time. The total time required for the computer to complete a task,including disk accesses, memory accesses, I/O activities, operating system overhead, CPU

execution time, and so on.

5. What is meant by throughput?It is also called bandwidth. It is the measure of performance; it is the number of taskscompleted per unit time.

6. What is CPU Time? What are the two types?CPU execution time also called CPU time. The actual time the CPU spends computing for aspecific task.User CPU time : The CPU time spent in a program itself.

System CPU time: The CPU time spent in the operating system performing tasks on behalf ofthe program.

7. Explain the term clock cycles per instruction (CPI).CPI means average number of clock cycles per instruction for a program or program

fragment.

8. Define the term instruction mix.A measure of the dynamic frequency of instructions across one or many programs

9. Define the term wordThe natural unit of access in a computer, usually a group of 32 bits; corresponds to the size of

a register in the MIPS architecture.

10. What is address, data transfer instruction?

Address means a value used to delineate the location of a specific data element within amemory array.

A command that moves data between memory and registers is called data transfer instruction.
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11. List the MIPS Fields op: Basic operation of the instruction, traditionally called the opcode.

rs: Th e fi rst register source operand. rt: Th e second register source operand.

rd: Th e register destination operand. It gets the result of the operation.

shamt: Shift amount.it will not be used until then, and hence the field contains zero funct: Function. Th is fi eld, oft en called the function code, selects the specific

variant of the operation in the op fi eld.

12. Define AND , ORAND : A logical bitby- b it operation with two operands that calculates a 1 only if there is a 1in both operands.

OR : A logical bit-bybit operation with two operands that calculates a 1 if there is a 1 ineither operand.

13. Define NOT,NOR

NOT: A logical b it-bybit operation with one operand that inverts the b its; that is, it replacesevery 1 with a 0, and every 0 with a 1.

NOR: A logical bit-bybit operation with two operands that calculates the NOT of the OR of

the two operands. That is, it calculates a 1 only if there is a 0 in both operands.

14. What is the use of control unit operation?

The control unit of a processor performs two tasks:(1) It causes the processor to step through a series of micro-operations in the proper sequence,

based on the program being executed, and (2) it generates the control signals that cause eachmicro-operation to be executed.

15. What are the four registers in Fetch cycle?1. Memory address registers (MAR)

2. Memory buffer register (MBR)3. Program counters (PC)

16. List the most common addressing techniques:

Immediate

Direct Indirect Register

Register indirect Displacement

Stack

17. Define Stack.

A stack is a linear array of locations. It is sometimes referred to as a pushdown list or last-in-first-out queue. The stack is a reserved block of locations. Items are appended to the top of

the stack so that, at any given time, the block is partially filled. Associated with the stack is apointer whose value is the address of the top of the stack.

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UNIT II ARITHMETIC OPERATIONS

1. How addition & subtraction carried out?Digits are added bit by bit from right to left, with carries passed to the next digit to the left,

just do by hand. Subtraction uses addition: the appropriate operand is simply negated beforebeing added.

2. When can overflow occur in addition?When adding operands with different signs, overflow cannot occur. The reason is the sum

must be no larger than o ne of the operands. For example, _10 _ 4 _ _6. Since the operands fitin 32 bits and the sum is no larger than an operand, the sum must fi t in 32 bits as well.

Therefore, no overflow can occur when adding positive and negative operands.

3. When can overflow occur in subtraction?When we subtract a negative number from a positive number and get a negative result, orwhen we subtract a positive number from a negative number and get a positive result. Such a

ridiculous result means a borrow occurred from the sign bit.

4. What are the two kinds of MIPS arithmetic instructions?

Add (add), add immediate (addi), and subtract (sub) cause exceptions on overflow. Add unsigned (addu), add immediate unsigned (addiu), and subtract unsigned (subu) do notcause exceptions on overflow.

5. Define Arithmetic Logic Unit (ALU)

ALU is a Hardware that performs addition, subtraction, and usually logical operations suchas AND and OR.

6. Define ExceptionIt is also called interrupt on many computers. An unscheduled event that disrupts program

execution. It is used to detect overflow. An exception or interrupt is essentially anunscheduled procedure call. The address of the instruction that overflowed is saved in aregister, and the computer jumps to a predefined address to invoke the appropriate routine for

that exception.

7. What is EPC?MIPS include a register called the exception program counter (EPC) to contain the address ofthe instruction that caused the exception. The instruction move from system control (mfc0) is

used to copy EPC into a general-purpose register so that MIPS soft ware has the option ofreturning to the off ending instruction via a jump register instruction.

8. What are the steps in multiplication?1. Just place a copy of the multiplicand (1 _ multiplicand) in the proper place if the multiplier

digit is a 1, or2. Place 0 (0 _ multiplicand) in the proper place if the digit is 0.

9. Define Faster Multiplication.

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Faster multiplications are possible by essentially providing one 32-bit adder for each bit ofthe multiplier: one input is the multiplicand ANDed with a multiplier bit, and the other is the

output of a prior adder.10. How Multiply in MIPS is carried out?

MIPS provide a separate pair of 32-bit registers to contain the 64-bit product, called Hi and

Lo. To produce a properly signed or unsigned product, MIPS has two instructions: multiply(mult) and multiply unsigned (multu). To fetch the integer 32-bit product, the programme

uses move from lo (mflo)

11. Define division in binary operationDivides two operands, called the dividend and divisor, and the result, called the quotient, areaccompanied by a second result, called the remainder. Here is another way to express the

relationship between the components:

12. Define the term Dividend, Divisor, Quotient, Remainder.Dividend: A number being divided.

Divisor : A number that the dividend is divided by.Quotient : The primary result of a division;Remainder: The secondary result of a division;

13. Define Scientific Notation, Normalized number.

A notation that renders numbers with a single digit to the left of the decimal point.Normalized a number in floating-point notation that has no lead ing 0s.

14. Define floating point.Computer arithmetic that represents numbers in which the binary point is not fixed is called

as a floating point.

15. Define Fraction, Exponent.

Fraction mean the value, generally between 0 and 1, placed in the fraction field. The fractionis also called the mantissa.

Exponent means the numerical representation system of fl oating-point arithmetic, the valuethat is placed in the exponent field.

16. Define Overflow, UnderflowOverflow (fl oatingpoint) : A situation in which a positive exponent becomes too large to fit

in the exponent field.underfl ow (floatingpoint): A situation in which a negative exponent becomes too large to fitin the exponent field.

17. Define single precision, double precision

Double precision: An fl oating-point value represented in two 32-bit words.Single precision: An fl oating-point value represented in a single 32- bit word.

18. What is guard bit?

Guard bit means the first of two extra bits kept on the right during intermediate calculationsof floating point numbers; used to improve rounding accuracy.

Dividend _ Quotient _ Divisor _ Remainder

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19. What is the use of round method?

Round Method to make the intermediate floating-point result fit the floating-point format;The goal is typically to find the nearest number that can be represented in the format.

20. Define sub word parallelism.

Parallelism occurs within a wide word, the extensions are classified as subword parallelism.It is also classified under the more general name of data level parallelism. They have been

also called vector or SIMD, for single instruction, multiple data.

UNIT III PROCESSOR AND CONTROL UNIT

1. List the instruction set:

The memory-reference instructions load word (lw) and store word (sw) The arithmetic-logical instructions add, sub, AND, OR, and slt The instructions branch equal (beq) and jump (j),

2. What are the two steps for every instruction?

1. Send the program counter (PC) to the memory that contains the code and fetch theinstruction from that memory.2. Read one or two registers, using fi elds of the instruction to select the registers

to read. For the load word instruction, we need to read only one register, butmost other instructions require reading two registers.

3. Define Clocking methodology.The approach used to determine when data is valid and stable relative to the clock. Edge-

triggered clocking is a clocking scheme in which all state changes occur on a clock edge.

4. Define control signalA signal used for multiplexor selection or for directing the operation of a functional unit;contrasts with a data signal, which contains information that is operated on by a functional

unit.

5. Define Asserted, Deasserted. Asserted : The signal is logically high or true.Deasserted : The signal is logically low or false.

6. Define data path element.A unit used to operate on or hold data within a processor. In the MIPS implementation, thedata path elements include the instruction and data memories, the register file, the ALU, andadders.

7.Define Program counter (PC)

The register containing the address of the instruction in the program being executed.

8. Define Register file.

A register file is a collection of registers in which any register can be read or written byspecifying the number of the register in the fi le. The register file contains the register state of

the computer. In addition, we will need an ALU to operate on the values read from theregisters.

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9.Definebranch target addressThe address specified in a branch, which becomes the new program counter (PC) if the

branch is taken. In the MIPS architecture the branch target is given by the sum of the offsetfield of the instruction and the address of the instruction following the branch.

10. Define branch taken and not.

A branch where the branch condition is satisfied and the program counter (PC) becomes thebranch target. All unconditional jumps are taken branches. Branch not taken or (untaken

branch) means a branch where the branch condition is false and the program counter (PC)becomes the address of the instruction that sequentially follows the branch.

11.Define branchA type of branch where the instruction immediately following the branch is always executed

independent of whether the branch condition is true or false.

12.Define truth table From logic, a representation of a logical operation by listing all the values of the inputs and

then in each case showing what the resulting outputs should be.

13. Define dont-care term

An element of a logical function in which the output does not depend on the values of all theinputs. Dont-care terms may be specified in different ways.

14. What are the four steps to execute the instruction?1. The instruction is fetched, and the PC is incremented.

2. Two registers, $t2 and $t3, are read from the register file; also, the main control unitcomputes the setting of the control lines during this step.3. The ALU operates on the data read from the register file, using the function code (bits 5:0,

which is the funct field, of the instruction) to generate the ALU function.4. The result from the ALU is written into the register fi le using bits 15:11 of the instruction

to select the destination register ($t1).

15. Define single clock cycle implementation.

An implementation in which an instruction is executed in one clock cycle. While easy tounderstand, it is too slow to be practical.

16.Define pipeliningAn implementation technique in which multiple instructions are overlapped in execution,

much like an assembly line.

17. How MIPS instructions classically into five steps:1. Fetch instruction from memory.2. Read registers while decoding the instruction. The regular format of MIPS instructions

allows reading and decoding to occur simultaneously.3. Execute the operation or calculate an address.

4. Access an operand in data memory.5. Write the result into a register.

18. What is Hazards?

There are situations in pipelining when the next instruction cannot execute in the followingclock cycle. These events are called hazards, and there are three different types.

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19. Define structural hazard

When a planned instruction cannot execute in the proper clock cycle because the hardwaredoes not support the combination of instructions that are set to execute is called structural

hazard.

20. Define data hazardAlso called a pipeline data hazard. When a planned instruction cannot execute in the proper

clock cycle because data that is needed to execute the instruction is not yet available.

21. Define forwarding or Bypassing.A method of resolving a data hazard by retrieving the missing data element from internal

buffers rather than waiting for it to arrive from programmer visible registers or memory load-

use data hazard.

22. Define Pipeline.Pipeline stall Also called bubble. A stall initiated in order to resolve a hazard.

23. Define control hazardControl hazard also called branch hazard. When the proper instruction cannot execute in the

proper pipeline clock cycle because the instruction that was fetched is not the one that isneeded; that is, the flow of instruction addresses is not what the pipeline expected.

24. Define branch predictionA method of resolving a branch hazard that assumes a given outcome for the branch and

proceeds from that assumption rather than waiting to ascertain the actual outcome.

25. Define latency (pipeline)

The number of stages in a pipeline or the number of stages between two instructions duringexecution

26. Define Dynamic Branch PredictionPrediction of branches at runtime using runtime information.

27. Define Branch prediction buffer or branch history table.

A small memory that is indexed by the lower portion of the address of the branch instructionand that contains one or more its indicating whether the branch was recently taken or not.

28. Define branch delay slotThe slot directly after a delayed branch instruction, which in the MIPS architecture is filled

by an instruction that does not affect the branch

29. Define branch target buffer

A structure that caches the destination PC or destination instruction for a branch. It is usuallyorganized as a cache with tags, making it more costly than a simple prediction buffer.

30. Define correlating predictorA branch predictor that combines local behaviour of a particular branch and global

information about the behaviour of some recent number of executed branches.

31. Define tournament branch predictor

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A branch predictor with multiple predictions for each branch and a selection mechanism thatchooses which predictor to enable for a given branch.

32. Define Interrupt, Vectored Interrupt

An exception that comes from outside of the processor. (Some architectures use the term

interrupt for all exceptions.)33. Define vectored interrupt

An interrupt for which the address to which control is transferred is determined by the causeof the exception.

34. Define imprecise interrupt or imprecise exception.Interrupts or exceptions in pipelined computers that is not associated with the exact

instruction that was the cause of the interrupt or exception.

UNIT IVPARALLELISM

1. What is ILP?

Pipelining exploits the potential parallelism among instructions. This parallelism is calledinstruction-level parallelism (ILP). There are two primary methods for increasing the

potential amount of instruction-level parallelism. The first is increasing the depth of the

pipeline to overlap more instructions

2. What is static multiple issue?Static multiple issue is an approach to implementing a multiple-issue processor where manydecisions are made by the compiler before execution.

3. What is Dynamic multiple issue?Dynamic multiple issue is an approach to implementing a multiple issue processor wheremany decisions are made during execution by the processor.

4. Define issue slotsThe positions from which instructions could issue in a given clock cycle; by analogy, these

correspond to positions at the starting blocks for a sprint.

5. Define speculation

It is an approach that allows the compiler or the processor to guess about the properties ofan instruction, so as to enable execution to begin for other instructions that may depend on

the speculated instruction. For example, we might speculate on the outcome of a branch, sothat instructions aft er the branch could be executed earlier

6. Define issue packetThe set of instructions that issues together in one clock cycle; the packet may be determined

statically by the compiler or dynamically by the processor.

7. What is Very Long Instruction Word (VLIW) ?

A style of instruction set architecture that launches many operations that are defined to beindependent in a single wide instruction, typically with many separate opcode fields.

8. What is use latency Number?

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Use latency Number of clock cycles between a load instruction and an instruction that canuse the result of the load without stalling the pipeline.

9. Define loop unrolling

A technique to get more performance from loops that access arrays, in which multiple copies

of the loop body are made and instructions from different iterations are.

10. What is register renaming?The renaming of registers by the compiler or hardware to remove antidependences.

Antidependence also called name dependence.

11. What is Antidependence?

It is an ordering forced by the reuse of a name, typically a register, rather than by a truedependence that carries a value between two instructions.

12. Define superscalar

It is an advanced pipelining technique that enables the processor to execute more than oneinstruction per clock cycle by selecting them during execution.

13. Define dynamic pipelineIt means scheduling Hardware support for reordering the order of instruction execution so asto avoid stalls.

14. What is the use of commit unit?

The unit in a dynamic or out-of-order execution pipeline that decides when it is safe torelease the result of an operation to programmer visible registers and memory.

15. Define the term Reservation Station , Reorder BufferReservation station : A buffer within a functional unit that holds the operands and the

operation.Reorder buffer : The buffer that holds results in a dynamically scheduled processoruntil it is safe to store the results to memory or a register.

16. Define out-of-order, In-order Execution

out-of-order: A situation in pipelined execution when an instruction blocked from executingdoes not cause the following instructions to wait.In-order commit:A commit in which the results of pipelined execution are written to the

programmer visible state in the same order that instruct ions are fetched.

17. What is an SMP?An SMP consists of multiple similar processors within the same computer, interconnected by

a bus or some sort of switching arrangement. The most critical problem to address in an SMPis that of cache coherence. Each processor has its own cache and so it is possible for a given

line of data to be present in more than one cache.

18. Define multithreaded processor.

When more than one processor are implemented on a single chip, the configuration is

referred to as chip multiprocessing. A related design scheme is to replicate some of the

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components of a single processor so that the processor can execute multiple threadsconcurrently; this is known as a multithreaded processor.

19. What is a cluster?

A cluster is a group of interconnected, whole computers working together as a unified

computing resource that can create the illusion of being one machine. The term wholecomputer means a system that can run on its own, apart from the cluster.

20. Define NUMANon uniform memory access (NUMA) is a type of single address space multiprocessor inwhich some memory accesses are much faster than others depending on which processor asks

for which word.

A NUMA system is a shared-memory multiprocessor in which the access time from a givenprocessor to a word in memory varies with the location of the memory word.

21. What are Flynnscategories of computer systems?Single instruction, single data (SISD) stream

Single instruction, multiple data (SIMD) streamMultiple instruction, single data (MISD) streamMultiple instruction, multiple data (MIMD) stream

22. What are the characteristics of SMP?

Characteristics:1. There are two or more similar processors of comparable capability.2. These processors share the same main memory and I/O facilities and are interconnected

by a b us or other interna l connection scheme, such that memory access time is approximatelythe same for each processor.

23. What are the features of bus organization? Simplicity

Flexibility Reliability

24. Define threadA thread includes the program counter, the register state, and the stack. It is a lightweight

process; whereas threads commonly share a single address space, processes dont.

25. What is process?A process includes one or more threads, the address space, and the operating system state.Hence, a process switch usually invokes the operating system, but not a thread switch.

26. Define fine-grained multithreading, coarse-grained multithreading

Fine-grained multithreading: A version of hardware multithreading that implies switchingbetween threads after every instruction.Coarse-grained multithreading: A version of hardware multithreading that implies switching

between threads only after significant events, such as a last- level cache miss.

27. What is simultaneous multithreading (SMT)?

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It is a version of multithreading that lowers the cost of multithreading by utilizing theresources needed for multiple issue, dynamically scheduled micro architecture.

28. Define synchronization

The process of coordinating the behaviour of two or more processes, which may be running

on different processors. Lock a synchronization device that allows access to data to only oneProcessor at a time.

UNIT V MEMORY AND I/O SYSTEMS

1. What is the principle of locality states?Programs access a relatively small portion of their address space at any insta nt of time, just as

you accessed a very small portion of the librarys collection. There are two different types oflocality.

2. What is temporal locality?Temporal locality (locality in time): if an item is referenced, it will tend to be referenced

again soon. Example if you recently brought a book to your desk to look at, you will probablyneed to look at it again soon.

3. What is spatial locality?Spatial locality (locality in space): if an item is referenced, items whose addresses are close

by will tend to be referenced soon.

4. Define memory hierarchy.

A memory hierarchy consists of multiple levels of memory with different speeds and sizes.

The faster memories are more expensive per bit than the slower memories and thus aresmaller.

5. Define Hit Rate , Miss Rate

Hit rate means the fraction of memory accesses found in a level of the memory hierarchy.Miss rate means the fraction of memory accesses not found in a level of the memory

hierarchy.

6. Define Hit Time, Miss Penalty

Hit time means the time required to access a level of the memory hierarchy, including the

time needed to determine whether the access is a hit or a miss.Miss penalty means the time required to fetch a block into a level of the memory hierarchyfrom the lower level, including the time to access the block, transmit it from one level toanother.

7. List the memory technology and its access time

Memory technology Typical access time $ per GiB in 2012SRAM semiconductor memory 0.52.5 ns $500$1000DRAM semiconductor memory 5070 ns $10$20

Flash semiconductor memory 5,00050,000 ns $0.75$1.00Magnetic disk 5,000,00020,000,000 ns $0.05$0.10

8. Define DIMMs

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Personal Mobile Devices like the iPad use individual DRAMs, memory for servers arecommonly sold on small boards called dual inline memory modules (DIMMs). DIMMs

typically contain 416 DRAMs, and they are normally organized to be 8 bytes wide forserver systems.

9. What is the use of Flash Memory?Flash memory is a type of electrically erasable programmable read-only memory (EEPROM).

Unlike disks and DRAM, but like other EEPROM technologies, writes can wear out flashmemory bits. To cope with such limits, most flash products include a controller to spread the

writes by remapping blocks that have been written many times to less trodden blocks. Thistechnique is called wear levelling10. What are tracks and sectors?

Each disk surface is divided into concentric circles, called tracks. There are typically tens ofthousands of tracks per surface. Each track is in turn divided into sectors that contain the

information; each track may have thousands of sectors. Sectors are typically 512 to 4096bytes in size

11. Define seek and seek timeThe process of positioning a read/write head over the proper track on a disk is called seek.

The time to move the head to the desired track is called the seek time.

12. Define cache.Cache was the name chosen to represent the level of the memory hierarchy between the

processor and main memory in the first commercial computer to have this extra level. Cacheis a safe place for hiding or storing things.

13. Define tag field

Tag field in a table used for a memory hierarchy that contains the address informationrequired to identify whether the associated block in the hierarchy corresponds to a requestedword.

14. Define cache miss

Cache miss is a request for data from the cache that cannot be filled because the data is notpresent in the cache. The index, which is used to select the block

15. Define write-throughA scheme in which writes always update both the cache and the next lower level of the

memory hierarchy, ensuring that data is always consistent between the two.

16. Define write buffer, Write-back

A queue that holds data while the data is waiting to be written to memory is called writebuffer.

Write-back means a scheme that handles writes by updating values only to the block in thecache, then writing the modified block to the lower level of the hierarchy when the block isreplaced.

17. What is fully associative cache , set-associative cache.

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A cache structure in which a block can be placed in any location in the cache is called fullyassociative cache.

Set-associative cache means a cache that has a fixed number of locations (atleast two) whereeach block can be placed.

18. What is the use of least recently used (LRU)?An LRU scheme, the block replaced is the one that has been unused for the longest time. The

set associative example on page 405 uses LRU, which is why we replaced Memory(0) insteadof Memory(6).

19. Define global miss rate, local miss rate.

Global miss rate: The fraction of references that miss in all levels of a multilevel cache.Local miss rate : The fraction of references to one level of a cache that miss; used in

multilevel hierarchies.

20. What is virtual memory

The main memory can act as a cachefor the secondary storage, usually implemented withmagnetic disks. This technique is called virtual memory

21. Define address translationIt is also called address mapping. The process by which a virtual address is mapped to an

address used to access memory.

22. Define segmentation

A variable-size address mapping scheme in which an address consists of two parts: a segmentnumber, which is mapped to a physical address, and a segment off set.

23. Define Page TableThe table containing the virtual to physical address translations in a virtual memory system.

The table, which is stored in memory, is typically indexed by the virtual page number; eachentry in the table contains the physical page number for that virtual page if the page is

currently in memory.

24. Define Swap Space.

The operating system usually creates the space on fl ash memory or disk for all the pages of aprocess when it creates the process. This space is called the swap space.

25. Define Software PollWhen the processor detects an interrupt, it branches to an interrupt-service routine whose job

it is to poll each I/O module to determine which module caused the interrupt. The poll couldbe in the form of a separate command line (e.g., TESTI/O). In this case, the processor raises

TESTI/O and places the address of a particular I/O.

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16 MarksUNIT I OVERVIEW & INSTRUCTIONS

1. Explain about Eight Ideas

Design for Moores Law

Use Abstraction to Simplify Design

Make the Common Case Fast

Performance via Parallelism

Performance via Pipelining

Performance via Prediction

Hierarchy of Memories

Dependability via Redundancy

2. Explain the components of computer system (Explain about von Neumann

architecture)

Three key concepts:

Programming in hardware

Programming in software

I/O components.

Two Internal Registers (MAR , MBR)

I/O address register (I/OAR)

I/O buffer (I/OBR)

Three modules

3. Explain the concept of performance of computer system

Introduction

Defining Performance

Throughput and Response Time

Relative Performance

Measuring Performance

CPU Performance and Its Factors

Improving Performance

Instruction Performance

The Classic CPU Performance Equation

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4. Explain the operation and operands of computer system

Introduction

MIPS operands

MIPS assembly language

Design Principle 1,2

Memory Operands Compiling Using Load and Store

Constant or Immediate Operands

Sample Instruction

5. How we can represent the instruction in computer system

Instruction format The hexadecimal-binary conversion

MIPS Fields

MIPS instruction encoding.

The stored-program concept.

6.Explain the logical operations in computer system

Introduction

AND

OR

NOT

NOR

7.Explain the logical operations in computer system

Micro-Operations

The Fetch CycleThe Indirect Cycle

The Interrupt CycleThe Execute CycleThe Instruction Cycle

Control of the Processor

Functional RequirementsControl SignalsA Control Signals Example

Internal Processor OrganizationThe Intel 8085

Hardwired Implementation

Control Unit InputsControl Unit Logic

8. Explain addressing modesThe most common addressing techniques:

Immediate Direct

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Indirect Register

Register indirect Displacement

Stack

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UNIT II ARITHMETIC OPERATIONS

1. How we can perform binary addition

Introduction to addition

Sample problem in binary addition Overflow

Signed Number and Unsigned Number

Condition for overflow occur

Sample problem for overflow

2. How we can perform binary subtraction

Introduction to subtraction

Sample problem in binary subtraction

Overflow Signed Number and Unsigned Number

Condition for overflow occur

Sample problem for overflow

3. Explain binary multiplication

Introduction to multiplication

Step in multiplication

First version of the multiplication hardware

Sequential Version of the Multiplication Algorithm

Sample problem

Signed Multiplication

Faster Multiplication

Multiply in MIPS

4. Explain binary Division

Introduction to Division

A Division Algorithm and Hardware

First version of the division hardware

Sequential Version of the Division Algorithm Sample problem

Signed Division

Faster Division

Division in MIPS

5. Write short notes on Floating Point Operation

Definition for floating point, Scientific Notation, Normalized Form

Floating-Point Representation

Single Precision Double precision

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Converting Binary to Decimal Floating Point

Floating-Point Addition

Floating-Point Multiplication

Floating-Point Instructions in MIPS

6. Explain Subword Parallelism Introduction to parallelism

basic NEON instructions.

Summary of ARM NEON instructions for subword parallelism

UNIT III PROCESSOR AND CONTROL UNIT

1. Explain basic MIPS implementation

An Overview of the Implementation

abstract view of the implementation of the MIPS The basic implementation of the MIPS subset

2. Explain the concept of building data path

Data path element

Two state elements are needed to store and access instructions

Data path used for fetching instructions and incrementing the program counter.

The two elements needed to implement R-format ALU operations are the register fi leand the ALU

branch target address, Branch taken Branch Not Taken

Creating a Single Data path

3. Explain the concept of control implementation scheme

The ALU Control

Designing the Main Control Unit

Operation of the Datapath

Finalizing Control

Why a Single-Cycle Implementation Is Not Used Today

4. Explain the concept of pipelining

An Overview of Pipelining

Designing Instruction Sets for Pipelining Pipeline Hazards

Data hazards

control hazards

5. Write short notes on pipeline Data path and control

stage of instruction execution

Graphically Representing Pipelines

Pipelined Control

6.

Describe about Data Hazards Forwarding versus Stalling

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Pipelined dependences in a five-instruction sequence

Data Hazards and Stalls7. Describe Control hazards

Assume Branch Not Taken

Reducing the Delay of Branches

Dynamic Branch Prediction Loops and Prediction

8. Write short notes on exception

Exceptions Are Handled in the MIPS Architecture

vectored interrupt

Exceptions in a Pipelined Implementation

Exception in a Pipelined Computer

The data path with controls to handle exceptions.

UNIT IVPARALLELISM

1. Write short notes on ILP

Parallelism via Instructions

Static and Dynamic multiple issues

The Concept of Speculation

An Example: Static Multiple Issue with the MIPS ISA

Simple Multiple-Issue Code Scheduling

Loop Unrolling for Multiple-Issue Pipelines

Energy Efficiency and Advanced Pipelining

2. Explain Parallel processing Challenges

Multiple Processor OrganizationsTypes of Parallel Processor Systems

Parallel Organizations

Symmetric Multiprocessors

OrganizationMultiprocessor Operating System Design Considerations

A Mainframe SMP

Cache Coherence and the Mesi Protocol

Software SolutionsHardware SolutionsThe MESI Protocol

Multithreading and Chip MultiprocessorsImplicit and Explicit Multithreading

Approaches to Explicit Multithreading

Clusters

Cluster ConfigurationsOperating System Design IssuesCluster Computer Architecture

Blade Servers

Clusters Compared to SMP

Nonuniform Memory Access

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MotivationOrganization

3. Explain Flynns classification

Single instruction, single data (SISD) stream

Single instruction, multiple data (SIMD) stream

Multiple instruction, single data (MISD) stream Multiple instruction, multiple data (MIMD) stream

4. Explain Hardware multithreading

Definition for thread and process

fine-grained multithreading

Coarse-grained multithreading

Simultaneous multithreading (SMT)

5. Write short notes on multicore processor

uniform memory access nonuniform memory access (NUMA)

synchronization

A Simple Parallel Processing Program

UNIT V MEMORY AND I/O SYSTEMS

1. Explain the concept of memory technologies

SRAM Technology

DRAM Technology Flash Memory

Disk Memory

2. Explain the concept of cache memory

Accessing a Cache

Handling Cache Misses

Handling Cache Misses

An Example Cache: The Intrinsity FastMATH Processor

3. Write short notes on measuring and improving cache performance Reducing Cache Misses by More Flexible Placement of Blocks

Locating a Block in the Cache

Locating a Block in the Cache

Reducing the Miss Penalty Using Multilevel Caches

Software Optimization via Blocking

4. Explain Virtual Memory

Definition for physical address, Virtual Address, Page fault

Placing a Page and Finding It Again

Page Faults Swap space ,LRU

about Writes

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5. Explain about TLB

translation-lookaside buffer (TLB)

The Intrinsity FastMATH TLB

Integrating Virtual Memory, TLBs, and Caches Implementing Protection with Virtual Memory

Handling TLB Misses and Page Faults

6. Explain about Programmed I/O

.External DevicesKeyboard/Monitor

Disk Drive

I/O Modules

Module Function

I/O Module Structure Programmed I/O

Overview of Programmed I/OI/O Commands

I/O Instructions

Interrupt-Driven I/O

Interrupt ProcessingDesign Issues

7. Explain about direct memory access

Drawbacks of Programmed and Interrupt-Driven I/O

DMA Function Intel 8237A DMA Controller

DMA Operations

8. Write short notes on I/O Processor

The Evolution of the I/O Function

Characteristics of I/O Channels

I/O Channel Architecture

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