Cs6303 unit2

- M.Senthil Kumar, AP/CSE

CS6303 – COMPUTER

ARCHITECTURE

(Regulation 2013)

UNIT II – Arithmetic

Operations

CA-Unit2-Lessonplan.docx

Unit – II Syllabus

CA by M.Senthil Kumar

5.1. ALU

5.2. Addition and subtraction (BB)

5.3. Multiplication

5.4. Division

5.5. Floating Point operations

5.6. Sub word parallelism

5.1. ALU Design

CA by M.Senthil Kumar home

An Arithmetic Logic Unit (ALU) is a digital

electronic circuit that performs arithmetic

and bitwise logical operations on integer

binary numbers.

It is a fundamental building block of the

CPU in all computers.

The inputs to an ALU are the data to be

operated on and a code indicating the

operation to be performed.

ALU – How it works in computer?

5.1. ALU (Contd..)


How Computers Calculate - the ALU.mp4

ALU.mp4

5.3. Multiplication


Normal Multiplication is done as:

home

5.3.Multiplication (H/W)


home

5.3.Multiplication (H/W)


home

5.3. Multiplication (Booth’s)


Booths Multiplication Recoding table:

home

5.3. Multiplication (Booth’s)


5.4. Division


home

5.4. Division


home

5.4. Division (Restoring Algm)


home

5.4. Division (Restoring Algm)


5.4 Division (Non-Restoring Algm)


Non-Restoring_div.mp4

5.5. Floating point Operations


Lecture -16 Floating Point Arithmetic.mp4



Going beyond signed and unsigned integers, programming

languages support numbers with fractions, which are called

real's in mathematics.

Eg:0.000000001ten or 1.0ten x10-9

Notice that in the last case, the number didn’t represent a

small fraction, but it was bigger than we could represent

with a 32-bit signed integer.

The alternative notation for the last two numbers is called

scientific notation, which has a single digit to the left of

the decimal point. A number in scientific notation that has no

leading 0s is called a normalized number, which is the

usual way to write it. For example, 1.0ten × 10-9 is in

normalized scientific notation, but 0.1ten × 10-8 and 10.0ten

× 10 -10 are not.



(Contd..) A designer of a floating-point representation must find

a compromise between the size of the fraction and

the size of the exponent, because a fixed word

size means you must take a bit from one to add a bit

to the other.

This tradeoff is between precision and range:

increasing the size of the fraction enhances the

precision of the fraction, while increasing the size of

the exponent increases the range of numbers that

can be represented.

Floating-point numbers are usually a multiple of the

size of a word.CA by M.Senthil Kumar home


(Contd..)

F involves the value in the fraction field;

E involves the value in the exponent field;





5.6. Sub Word Parallelism

It's another name for SIMD-Within-A-Register (SWAR), or register-

sized vector operations.

The idea is that if you have registers which can hold machine words

of multiple times of your data type size, you can pack several data

elements into them, and make single instructions affect all of those

simultaneously.

A 128-bit register, for instance, can hold two 64-bit floating point

values; as long as your 'multiply' instruction is aware that the register

is split in the middle, you can get 2 multiplications out of 1

operation.

A sub word is a lower precision unit of data contained within a word.

In sub word parallelism, we pack multiple subwords into a word and

then process whole words.


home

5.6. Sub Word Parallelism (Contd..)

It is possible to apply subword parallelism to

noncontiguous subwords of different sizes

within a word.

however, implementations are much simpler if

we allow only a few subword sizes and if a

single instruction operates on contiguous

subwords that are all the same size.

One key advantage of subword parallelism is

that it allows general-purpose processors to

exploit wider word sizes even when not

processing high-precision data.CA by M.Senthil Kumar home

Cs6303 unit2

Education