CS EEE F241 8086 Pinout.pdf

8/18/2019 CS EEE F241 8086 Pinout.pdf

1/75

8086 Pin Out and modes ofOperation

Topic-V

T1. Barry B Brey, The Intel Microprocessors .Pearson, Eight Ed. 2009. Chapter 9

March 3 rd – 12 th 2016


2/75

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION3/12/2016 2


3/75

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Pin

3/12/2016 3


4/75


Pin Diagram & it’s functions


5/75


• Pin Diagram and its functions• Clock generation• Bus buffering• Bus latching

• Timing diagram• Wait states• Minimum mode operation vs Maximum mode operation.

8086 or 8088


6/75

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION3-6

Minimum vs Maximum Operation mode

Minimum Mode Maximum Mode 8086 generates control signals

for memory and I/O operations It needs 8288 bus controller to generate

control signals for memory and I/Ooperations

Some functions are notavailable in minimum mode

It allows the use of 8087 coprocessor;it also provides other functions

Compatible with 8085-basedsystems

• 8086 can operates in single processor (Minimum mode) ormultiprocessor (Maximum mode) configurations to achievehigh performance.


7/75ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION3/12/2016 7


• 8086 & 8088 both are packaged in 40-pin dual in-line packages ( DIPs )

• 808 6 is a 16-bit microprocessor with a 16-bit data bus; 808 8

has an 8-bit data bus. – 8086 has pin connections AD 0 – AD 15 – 8088 has pin connections AD 0 – AD 7

• Data bus width is the only major difference.• 8086 transfers 16-bit data more efficiently


9/75ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION




• Signal having common functions (in minimum as well asin maximum mode)

• Signal having special functions for minimum mode.

• Signal having special functions for maximum mode.




• Signal having common functions (in minimum as well as inmaximum mode)

• Pin Connections AD7 - AD 0

8088 address/data bus lines are multiplexed--contain the rightmost 8 bits of the memory address or I/O -portnumber whenever ALE is active (logic 1)--or data whenever ALE is inactive (logic 0)

These pins are at their high-impedance state during a holdacknowledge .




Pin Connections A15

– A8• 8088 address bus provides the upper-half memory address bits

that are present throughout a bus cycle.• These address connections go to their high-impedance state

during a hold acknowledge.

Pin Connections AD 15 – AD 8• 8086 address/data bus lines compose upper multiplexed

address/data bus on the 8086.• These lines contain address bits A 15 – A8 whenever ALE is a logic

1, and data bus connections D 15 – D8 when ALE is a logic 0.• These pins enter a high-impedance state when a hold

acknowledge occurs.




Pin Connections A19 /S

6- A

16 /S

3

Address/status bus bits are multiplexed to provide address signalsA19 – A16 and status bits S6 – S3.

• high-impedance state during hold acknowledge• status bit S 6 is always logic 0,• bit S 5 indicates the condition of the IF flag bit• S4 and S 3 show which segment is accessed during the current

bus cycle.• S4 S3 = 00 = Alternate Data segment• S4 S3 = 01 = Stack segment• S4 S3 = 10 = Code segment• S4 S3 = 11 = Data segment




Pin Connections BHE / S 7

• The bus high enable pin is used in 8086 to enable the most-significant data bus bits (D 15 – D8) during a read or a write operation.

• The state of S 7 is always a logic 1.



3/12/2016 18


Pin Connections RD When read signal is logic 0, the data bus is receptive to datafrom memory or I/O devices

Pin Connections Ready • Inserts wait states into the timing .

– if placed at a logic 0, the microprocessor enters into waitstates and remains idle – if logic 1, no effect on the operation



Pin Connections

• Interrupt request is used to request a hardware interrupt.

– If INTR is held high when IF = 1, 8086/8088enters an interrupt acknowledge cycle after the currentinstruction has completed execution

NMI • The non-maskable interrupt input is similar to INTR.

– does not check IF flag bit for logic 1 – if activated, uses interrupt vector 2

INTR



Pin Connections

• The TEST pin is an input that is tested by the WAIT instruction.

• If TEST is a logic 0 , the WAIT instruction functions as an NOP,(EXECUTION WILL CONTINUE)

• If TEST is a logic 1, processor remains in idle state.

• The TEST pin is most often connected tothe 8087 numeric coprocessor.

TEST



Pin Connections

• Causes the microprocessor to reset itself if held high a minimum offour clocking periods. – when 8086/8088 is reset, it executes instructions at memory

location FFFFOH – also disables future interrupts by clearing IF flag

CLK • The clock pin provides the basic timing signal .

– must have a duty cycle of 33 % (high for one third of clocking period, low for two thirds) to provide proper internal timing

– -range 5-10 MHz

RESET



Pin Connections

• This power supply input provides a +5.0 V , ± 10 % signal to themicroprocessor.

GND

• The ground connection is the return for the power supply. – 8086/8088 microprocessors have two pins labeled GND – Both must be connected to ground for proper operation

VCC



Pin Connections

• Minimum/maximum mode pin selects either minimum orMaximum mode operation. – if minimum mode selected, the MN/MX pin must be

connected directly to +5.0 V

MN/MX


24/75


(a) The pin-out of the 8086 in maximum mode ;(b) the pin-out of the 8086 in minimum mode .


25/75


Minimum Mode Pins

• Minimum mode operation is obtained by connecting the MN/MX pin directly to +5.0 V

M/IO • M/IO (8086) or IO/M (8088) pin selects memory or I/O.

– indicates the address bus contains either a memory address or anI/O port address.

– high-impedance state during hold acknowledge


26/75


Minimum Mode Pins

• Write line indicates 8086/8088 is outputting data to a memory orI/O device. – during the time WR is a logic 0, the data bus contains valid

data for memory or I/O – high-impedance during a hold acknowledge

INTA • The interrupt acknowledge signal is a response to the INTR input

pin. – normally used to gate the interrupt vector number onto the data

bus in response to an interrupt

WR


27/75


Minimum Mode Pins

• Address latch enable shows the 8086 address/data buscontains an address. –

can be a memory address or an I/O port number – ALE signal doesn’t float during hold acknowledge

DT/R • The data transmit/receive signal shows that the microprocessor

data bus is transmitting ( DT/R = 1 ) or receiving ( DT/R = 0 ) data. – used to enable external data bus buffers

ALE


28/75


Minimum Mode Pins

• Data bus enable activates external data bus buffers.

HOLD, HLDA • Hold input requests a direct memory access (DMA). – if HOLD signal is a logic 1, the microprocessor stops executing

software and places address, data, and control bus at high-impedance

– if a logic 0, software executes normally – Hold acknowledge (HLDA) send by microprocessor, indicates

the 8086/8088 has entered the hold state .

DEN


29/75


SS0 • The SS0 status line is equivalent to the S 0 pin in maximum modeoperation.

• Signal is combined with IO/M and DT/R to decode the function ofthe current bus cycle.

Minimum Mode Pins

IO/M’ DT/R’ SS0’ FUNCTION

0 0 0 INTERRUPT ACKNOWLEDGEMENT

0 0 1 MEMORY READ

0 1 0 MEMORY WRITE

0 1 1 HALT

1 0 0 OPCODE FETCH

1 0 1 I/O READ

1 1 0 I/O WRITE

1 1 1 PASSIVE


30/75


• In order to achieve maximum mode for use with externalcoprocessors, connect the MN/ MX pin to ground .

S2, S1, and S0 • Status bits indicate function of the current bus cycle. – normally decoded by the 8288 bus controller

Maximum Mode Pins


31/75


S2, S1, and S0

Maximum Mode Pins

S2’ S1’ S0’ FUNCTION

0 0 0 INTERRUPT ACKNOWLEDGEMENT

0 0 1 I/O READ0 1 0 I/O WRITE

0 1 1 HALT

1 0 0 OPCODE FETCH

1 0 1 MEMORY READ

1 1 0 MEMORY WRITE

1 1 1 PASSIVE


32/75


• The request/grant pins request direct memory accesses (DMA)during maximum mode operation. – bidirectional; used to request and grant a DMA operation

LOCK • The lock output is used to lock peripherals off the system. This pin

is activated by using the LOCK: prefix on any instruction.

RQ/GT1 & RQ/GT0 (higher priority)

Maximum Mode Pins


33/75


• The queue status bits show the status of the internal instructionqueue. – provided for access by the 8087 coprocessor

QS 1 & QS 0

QS 1 QS 0 FUNCTION

0 0 QUEUE IS IDLE

0 1 FIRST BYTE OF OPCODE

1 0 QUEUE IS EMPTY

1 1 SUBSEQUENT BYTE OF OPCODE

Maximum Mode Pins


34/75


CLOCK GENERATOR (8284A)

• CLK is crystal controlled clock sent to 8086 from an externalclock generator device such as 8284.

• One cycle of this clock is called a T state .

• A state is measured as falling edge of one clock pulse to fallingedge of next clock pulse


35/75




36/75



• With no clock generator, many circuits would be required togenerate the clock (CLK).

• 8284A provides the following basic functions:

– clock generation; – RESET & READY synch;


37/75



Different versions of 8086 have maximum clock frequencies of between 5MHz and 10MHz.

The minimum time of one state will be between 100nS to 200nS

Basic operation such as

• reading a byte from memory /port

• writing a byte to a memory/port

called a machine cycle


38/75



The pin-out of the 8284A clock generator.


39/75





40/75


X1 and X 2 • The crystal oscillator pins connect to an external crystal used as the

timing source for the clock generator and all its functions


41/75


• The frequency/crystal select input chooses the clocking source forthe 8284A. – if held high, an external clock is provided to the EFI input pin

– if held low, the internal crystal oscillator provides the timingsignal


42/75


• The clock output pin provides the CLK input signal to 8086/8088and other components. – output signal is one third of the crystal or EFI input frequency

– 33% duty cycle required by the 8086/8088

PCLK • The peripheral clock signal is one sixth the crystal or EFI input

frequency. – PCLK output provides a clock signal to the peripheral equipment

in the system

CLK


43/75





44/75


RES • Reset input is an active-low input to 8284A.

– often connected to an RC network that provides power-onresetting

Reset output is connected to the 8086/8088 RESET input pin.

RESET


45/75


BUS BUFFERING & LATCHING

• Before 8086/8088 can be used with memory or I/O interfaces, theirmultiplexed buses must be demultiplexed .

CPU pin descriptions:


46/75


GNDAD14

AD13AD12AD11AD10

AD9AD8

AD7 AD6 AD5 AD4 AD3 AD2

AD1 AD0 NMI

INTR CLKGND

VccAD15

A16 /S3 A17 /S4 A18 /S5 A19 /S6 ___SS0 (HIGH) ___MN/MX ___RD ___ ____HOLD (RQ/GT0) ___ ____HLDA (RQ/GT1) ___ ______WR (LOCK) __ __M/IO (S2) __ __DT/R (S1) ____ __DEN (S0) ALE (QS0) _____INTA (QS1) _____TESTREADYRESET

1 40

8086

20 21

Minmode operationsignals (MN/MX=1) Time-

multiplexed Address Bus

/Statussignals (outputs)

0V=“0”,referenc

e for allvoltages

Time-multiplexed Address

(outputs)/ DataBus (bidirectional)

Operation Mode,(input):

1 = minmode(8086 generates

all the neededcontrol signals

for a smallsystem),

0 = maxmode(8288 BusController

expands thestatus signals togenerate morecontrol signals)

Control Bus

(in,out)

Statussignals

(outputs)

Interruptacknowledge

(output)

Hardware

interruptrequests(inputs)

5-10 MHz,(input)

5V±10%

CPU pin descriptions:

Time-multiplexed Address (outputs)/

Data Bus(bidirectional)


47/75


• All computer systems have three buses : – an address bus that provides memory and I/O with the

memory address or the I/O port number – a data bus that transfers data between the microprocessor and

the memory and I/O – a control bus that provides control signals to

the memory and I/O• These buses must be present in order to interface to memory and

I/O.


48/75



49/75


Demultiplexing the Buses

• The address/data bus of the 8086/8088 is multiplexed (shared)to reduce the number of pins required for the integrated circuit

– the hardware designer must extract or demultiplex information from these pins


50/75




51/75




52/75



M/IO’ RD’ WR’ FUNCTION

1 0 1 MEMR’

1 1 0 MEMW’

0 0 1 IOR’

0 1 o IOW’


53/75




54/75




55/75




56/75


3/12/2016 56

Bus Cycle


57/75


3/12/2016 57

Machine Cycle

• MEMR - (opcode/ data)• MEMW -- ( data)• IOR

• IOW


58/75


3/12/2016 58

Bus Cycle

• MOV AX, BX• 8B C3• 1 MEMR (OPCODE FETCH )


59/75


3/12/2016 59

Bus Cycle

• ADD BX, [0110]• 03 1E 10 01• 2 MEMR (OPCODE FETCH + MEMR )

• i.e. 2 Machine cycles• To execute the instruction• 1 Machine cycle---- Read Data from DS:0110

– (1 MEMR)

• 3 Machine Cycles


60/75


3/12/2016 60

Bus Cycle


61/75


3/12/2016 61

Bus Cycle

• ADD [0110], BX• 01 1E 10 01• To instruction fetch:• 2 MEMR (OPCODE FETCH + MEMR )• 2 Machine cycle• To execute the Instruction• 1 Machine cycle---- Read Data from DS:0110

– (1 MEMR)• 1 Machine cycle---- Store Results in DS:0110

– (1 MEMW)• 4 Machine Cycles


62/75


3/12/2016 62

Bus Cycle

• CBW• 98 • 1 MEMR (OPCODE FETCH )



63/75


3/12/2016 63

Bus Cycle

• ADD AX, [BX]• 03 07• To Fetch instruction:

• 1 MEMR (OPCODE FETCH )• 1 Machine cycle• To execute the Instruction• 1 Machine cycle---- Read Data from DS:[BX]

– (1 MEMR)



64/75

TIMING DIAGRAM


65/75


TIMING DIAGRAM

3/12/2016 65

Each cycle equals four system-clocking periods ( T states ).

If the clock is operated at 5 MHz, one 8086/8088 bus cycle iscomplete in 800 ns.

During the first clocking period in a bus cycle, called T1:

• the address of the memory or I/O location is sent out viathe address bus

• During TI, control signals are also output.

• indicating whether the address bus contains a memoryaddress or an I/O device (port) number

TIMING DIAGRAM


66/75


TIMING DIAGRAM

3/12/2016 66

• During T2, the processors issue the RD or WR signal, DEN.

• READY is sampled at the end of T 2.• if low at this time , T3 becomes a wait state (Tw)

• If a read bus cycle, the data bus is sampled at the end of T3.

• In T4, all bus signals are deactivated in preparation for thenext bus cycle

TIMING DIAGRAM


67/75


TIMING DIAGRAM

3/12/2016 67

BUS TIMING


68/75


for READ OPERATION

3/12/2016 68

BUS TIMING


69/75


for WRITE OPERATION

3/12/2016 69

MEMORY ACCESS TIME


70/75


MEMORY ACCESS TIME

3/12/2016 70

MEMORY ACCESS TIME


71/75


MEMORY ACCESS TIME

3/12/2016 71

• Memory access time starts when the address appears on thememory address bus and continues until the microprocessorsamples the memory data at T 3.

• About three T states elapse between these times

• The address does not appear until T CLAV time (time fromclock low to address valid) (110 ns if a 5 MHz clock) afterthe start of T 1.

• TCLAV time must be subtracted from the three clockingstates (600 ns) separating the appearance of the address (T 1)and the sampling of the data (T 3).


72/75

MEMORY ACCESS TIME


73/75


MEMORY ACCESS TIME

3/12/2016 73

• Memory devices chosen for connection to the8086/8088 operating at 5 MHz must be able to accessdata in less than 460 ns .

• Because of the time delay introduced by the address

decoders and buffers in the system a 30- or 40-nsmargin should exist for the operation of these circuits

• The memory speed should be no slower than about 420

ns to operate correctly with the 8086/8088microprocessors.

READY AND WAIT STATE


74/75



3/12/2016 74

• The READY input causes wait states for slower memoryand I/O components.

• A wait state (Tw) is an extra clocking period between T2 and T3 to lengthen bus cycle .

• On one wait state , memory access time of 460 ns , islengthened by one clocking period ( 200 ns ) to 660 ns ,

based on a 5 MHz clock.



75/75


• This section covers READY synchronization circuitryinside the 8284A clock generator.

• If READY is logic 0 at the end of T 2, T 3 is delayed and Tw

inserted between T 2 and T 3.

• READY is next sampled at the middle of T w to determine if the next state is T w or T 3.

CS EEE F241 8086 Pinout.pdf

Documents