cs 152 L1 3 .1 DAP Fa97, U.CB Pipelining Lessons ° Pipelining doesn’t help latency of single task, it helps throughput of entire workload ° Multiple tasks operating simultaneously using different resources ° Potential speedup = Number pipe stages ° Pipeline rate limited by slowest pipeline stage ° Unbalanced lengths of pipe stages reduces speedup ° Time to “fill” pipeline and time to “drain” it reduces speedup 6 PM 7 8 9 Time B C D A 30 30 30 30 30 30 30 T a s k O r d e r
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Cs 152 L1 3.1 DAP Fa97, U.CB Pipelining Lessons °Pipelining doesn’t help latency of single task, it helps throughput of entire workload °Multiple tasks.
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cs 152 L1 3 .1 DAP Fa97, U.CB
Pipelining Lessons
° Pipelining doesn’t help latency of single task, it helps throughput of entire workload
° Multiple tasks operating simultaneously using different resources
° Potential speedup = Number pipe stages
° Pipeline rate limited by slowest pipeline stage
° Unbalanced lengths of pipe stages reduces speedup
° Time to “fill” pipeline and time to “drain” it reduces speedup
° Stall for Dependences
6 PM 7 8 9
Time
B
C
D
A
303030 3030 3030Task
Order
cs 152 L1 3 .2 DAP Fa97, U.CB
The Five Stages of Load
° Ifetch: Instruction Fetch• Fetch the instruction from the Instruction Memory
° Ifetch: Instruction Fetch• Fetch the instruction from the Instruction Memory
° Reg/Dec: Registers Fetch and Instruction Decode
° Exec: Calculate the memory address
° Mem: Write the data into the Data Memory
Cycle 1 Cycle 2 Cycle 3 Cycle 4
Ifetch Reg/Dec Exec MemStore Wr
cs 152 L1 3 .22 DAP Fa97, U.CB
The Three Stages of Beq
° Ifetch: Instruction Fetch• Fetch the instruction from the Instruction Memory
° Reg/Dec: • Registers Fetch and Instruction Decode
° Exec: • compares the two register operand,
• select correct branch target address
• update PC
Cycle 1 Cycle 2 Cycle 3 Cycle 4
Ifetch Reg/Dec Exec MemBeq Wr
cs 152 L1 3 .23 DAP Fa97, U.CB
Pipeline Control
PC
Instructionmemory
Address
Inst
ruct
ion
Instruction[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction[15– 0]
0
0Registers
Writeregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Mux
1Write
data
Read
data Mux
1
ALUcontrol
RegWrite
MemRead
Instruction[15– 11]
6
IF/ID ID/EX EX/MEM MEM/WB
MemWrite
Address
Datamemory
PCSrc
Zero
AddAdd
result
Shiftleft 2
ALUresult
ALU
Zero
Add
0
1
Mux
0
1
Mux
cs 152 L1 3 .24 DAP Fa97, U.CB
° We have 5 stages. What needs to be controlled in each stage?• Instruction Fetch and PC Increment• Instruction Decode / Register Fetch• Execution• Memory Stage• Write Back
° How would control be handled in an automobile plant?• a fancy control center telling everyone what to do?• should we use a finite state machine?