CS 152 Computer Architecture and Engineering CS252 ...cs152/sp20/lectures/L09-VirtualMemory.pdf · Demand Paging Provides the ability to run programs larger than the primary memory

CS152ComputerArchitectureandEngineeringCS252GraduateComputerArchitecture

Lecture9–VirtualMemory

KrsteAsanovicElectricalEngineeringandComputerSciences

UniversityofCaliforniaatBerkeley

http://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs152

Last@meinLecture8

§  Protec=onandtransla=onrequiredformul=programming–  Baseandboundswasearlysimplescheme

§  Page-basedtransla=onandprotec=onavoidsneedformemorycompac=on,easyalloca=onbyOS–  Butneedtoindirectinlargepagetableoneveryaccess

§ Addressspacesaccessedsparsely–  Canusemul=-levelpagetabletoholdtransla=on/protec=oninforma=on,butimpliesmul=plememoryaccessesperreference

§ Addressspaceaccesswithlocality–  Canuse“transla=onlookasidebuffer”(TLB)tocacheaddresstransla=ons(some=mesknownasaddresstransla=oncache)

–  S=llhavetowalkpagetablesonTLBmiss,canbehardwareorsoNwaretalk

§ VirtualmemoryusesDRAMasa“cache”ofdiskmemory,allowsverycheapmainmemory

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ModernVirtualMemorySystemsIllusionofalarge,private,uniformstore

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Protec=on&Privacyseveralusers,eachwiththeirprivateaddressspaceandoneormoresharedaddressspaces

pagetable≡namespaceDemandPaging

ProvidestheabilitytorunprogramslargerthantheprimarymemoryHidesdifferencesinmachineconfigura=ons

Thepriceisaddresstransla/ononeachmemoryreference

OS

useri

PrimaryMemory

SecondaryStorage

VA PAmappingTLB

Recap:HierarchicalPageTable

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Level1PageTable

Level2PageTables

DataPages

pageinprimarymemorypageinsecondarymemory

RootofCurrentPageTable

p1

offset

p2

VirtualAddressfromCPU

(ProcessorRegister,satpin

RISC-V)

PTEofanonexistentpage

p1p2offset01112212231

10-bitL1index

10-bitL2index

PhysicalM

emory

RISC-V Sv32 Virtual Memory Scheme

Recap:Page-BasedVirtual-MemoryMachine(HardwarePage-TableWalk)

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§  Assumespagetablesheldinuntranslatedphysicalmemory

PCInst.TLB

Inst.Cache D Decode E M

DataCache W+

PageFault?

Protec/onviola/on?PageFault?

Protec/onviola/on?

DataTLB

MainMemory(DRAM)

MemoryControllerPhysicalAddress

PhysicalAddress

PhysicalAddress

PhysicalAddress

Page-TableBaseRegister

VirtualAddress Physical

Address

VirtualAddress

HardwarePageTableWalker

Miss? Miss?

AddressTransla@on:pu3ngitalltogether

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VirtualAddress

TLBLookup

PageTableWalk

UpdateTLBPageFault(OSloadspage)

Protec=onCheck

PhysicalAddress(tocache)

miss hit

thepageis∉ memory ∈ memory denied permi_ed

Protec=onFault

hardwarehardwareorsoNwaresoNware

SEGFAULT Where?

Page-FaultHandler

§ WhenthereferencedpageisnotinDRAM:–  Themissingpageislocated(orcreated)–  Itisbroughtinfromdisk,andpagetableisupdated

•  AnotherjobmayberunontheCPUwhilethefirstjobwaitsfortherequestedpagetobereadfromdisk

–  IfnofreepagesareleN,apageisswappedout•  Pseudo-LRUreplacementpolicy,implementedinsoNware

§ Sinceittakesalong=metotransferapage(msecs),pagefaultsarehandledcompletelyinsoNwarebytheOS–  Untranslatedaddressingmodeisessen=altoallowkerneltoaccesspagetables

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HandlingVM-relatedexcep@ons

§ HandlingaTLBmissneedsahardwareorsoNwaremechanismtorefillTLB

§ Handlingpagefault(e.g.,pageisondisk)needsrestartableexcep=onsosoNwarehandlercanresumeaNerretrievingpage–  Preciseexcep=onsareeasytorestart–  Canbeimprecisebutrestartable,butthiscomplicatesOSsoNware

§ Aprotec=onviola=onmayabortprocess–  ButoNenhandledthesameasapagefault

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PCInstTLB

Inst.Cache D Decode E M

DataTLB

DataCache W+

TLBmiss?PageFault?Protec/onviola/on?

TLBmiss?PageFault?Protec/onviola/on?

AddressTransla@oninCPUPipeline

§ Needtocopewithaddi=onallatencyofTLB:–  slowdowntheclock?–  pipelinetheTLBandcacheaccess?–  virtualaddresscaches–  parallelTLB/cacheaccess

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PCInstTLB

Inst.Cache D Decode E M

DataTLB

DataCache W+

TLBmiss?PageFault?Protec/onviola/on?

TLBmiss?PageFault?Protec/onviola/on?

Virtual-AddressCaches

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§  one-stepprocessincaseofahit(+)§  cacheneedstobeflushedonacontextswitchunlessaddressspace

iden=fiers(ASIDs)includedintags(-)§  aliasingproblemsduetothesharingofpages(-)§  maintainingcachecoherence(-)

CPU Physical Cache TLB Primary

Memory VA PA PA

Alternative: place the cache before the TLB

Virtual Cache CPU

VA (StrongARM) PA TLB

Primary Memory VA

VirtuallyAddressedCache(VirtualIndex/VirtualTag)

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PC

Inst. TLB

Inst.Cache D Decode E M Data

Cache W+

DataTLB

MainMemory(DRAM)

MemoryControllerPhysicalAddress

Instruc=ondataPhysicalAddress

PhysicalAddress

Page-Table Base Register

VirtualAddress

VirtualAddress

HardwarePageTableWalker

Miss?Miss?

Translate on miss

AliasinginVirtual-AddressCaches

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VA1

VA2

PageTable

DataPages

PA

VA1

VA2

1stCopyofDataatPA

2ndCopyofDataatPA

Tag Data

Two virtual pages share one physical page

Virtualcachecanhavetwocopiesofsamephysicaldata.Writestoonecopynotvisibletoreadsofother!

GeneralSolu=on:Preventaliasescoexis/ngincache

SoNware(i.e.,OS)solu=onfordirect-mappedcache

VAsofsharedpagesmustagreeincacheindexbits;thisensuresallVAsaccessingsamePAwillconflictindirect-mappedcache(earlySPARCs)

ConcurrentAccesstoTLB&Cache(VirtualIndex/PhysicalTag)

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IndexLisavailablewithoutconsul=ngtheTLB→cacheandTLBaccessescanbeginsimultaneously!

TagcomparisonismadeaNerbothaccessesarecompletedCases:L+b=k,L+b<k,L+b>k

VPNLb

TLB Direct-mapCache2Lblocks

2b-byteblockPPNPageOffset

=hit? DataPhysicalTag

Tag

VA

PA

VirtualIndex

k

Virtual-IndexPhysical-TagCaches:Associa@veOrganiza@on

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Howdoesthisschemescaletolargercaches?

VPNaL=k-bb

TLB Direct-map2Lblocks

PPNPageOffset

=hit?

Data

Phy.Tag

Tag

VA

PA

VirtualIndex

k Direct-map2Lblocks

2a

=2a

ANerthePPNisknown,2aphysicaltagsarecompared

CS152Administrivia

§  PS2dueWednesdayFeb26§ MidterminclassMondayMarch2

–  Coverslectures1–9,plusassignedproblemsets,labs,bookreadings

§  Lab2dueMondayMarch9

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CS252

CS252Administrivia§  Startthinkingofclassprojectsandformingteamsoftwo§  ProposaldueWednesdayFebruary26th§  ProposalshouldbeonepagePDFincluding:

–  Title–  Teammembernames–  Whatareyoutryingtodo?–  Howisitdonetoday?–  Whatisyourideaforimprovementandwhydoyouthinkyou’llbesuccessful

–  Whatinfrastructureareyougoingtouseforyourproject?–  Project=melinewithmilestones

§ MailPDFofproposaltoinstructors§ Givea<5-minutepresenta=oninclassindiscussionsec=on=meonMarch11th

§ NodiscussiononMnodayMarch4th–midterm!

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ConcurrentAccesstoTLB&LargeL1TheproblemwithL1>Pagesize

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CanVA1andVA2bothmaptoPA?

VPN aPageOffsetb

TLB

PPN PageOffsetb

Tag

VA

PA

VirtualIndexL1PAcacheDirect-map

= hit?

PPNaData

PPNaDataVA1VA2

Asolu@onviaSecond-LevelCache

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UsuallyacommonL2cachebacksupbothInstruc=onandDataL1cachesL2is“inclusive”ofbothInstruc=onandDatacaches

• InclusivemeansL2hascopyofanylineineitherL1

CPUL1DataCache

L1Instruc=on

Cache UnifiedL2Cache

RF MemoryMemoryMemoryMemory

An@-AliasingUsingL2[MIPSR10000,1996]

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§  SupposeVA1andVA2bothmaptoPAandVA1isalreadyinL1,L2(VA1≠VA2)

§  ANerVA2isresolvedtoPA,acollisionwillbedetectedinL2.

§  VA1willbepurgedfromL1andL2,andVA2willbeloaded⇒noaliasing!

VPN aPageOffsetb

TLB

PPN PageOffsetb

Tag

VA

PA

VirtualIndexL1PAcacheDirect-map

= hit?

PPNaData

PPNaData

VA1

VA2

Direct-MappedL2

PAa1Data

PPN

intoL2tag

An@-AliasingusingL2foraVirtuallyTaggedL1

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VPN PageOffsetb

TLB

PPN PageOffsetb

Tag

VA

PA

VirtualIndex&Tag

PhysicalIndex&Tag

L1VACache

L2PACacheL2“contains”L1

PAVA1Data

VA1Data

VA2Data

“VirtualTag”

Physically-addressedL2canalsobeusedtoavoidaliasesinvirtually-addressedL1

CS252

AtlasRevisited

§ OnePARforeachphysicalpage

§  PAR’scontaintheVPN’softhepagesresidentinprimarymemory

§ Advantage:Thesizeispropor=onaltothesizeoftheprimarymemory

§ Whatisthedisadvantage?

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VPN

PAR’s

PPN

CS252

HashedPageTable:Approxima@ngAssocia@veAddressing

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§ HashedPageTableistypically2to3=meslargerthanthenumberofPPN’storeducecollisionprobability

§  ItcanalsocontainDPN’sforsomenon-residentpages(notcommon)

§  Ifatransla=oncannotberesolvedinthistablethenthesoNwareconsultsadatastructurethathasanentryforeveryexis=ngpage(e.g.,fullpagetable)

hashOffset

BaseofTable

+ PAofPTE

PrimaryMemory

VPNPIDPPN

PageTableVPN d VirtualAddress

VPNPIDDPN

VPNPID

PID

CS252

PowerPC:HashedPageTable

§  Eachhashtableslothas8PTE's<VPN,PPN>thataresearchedsequen=ally

§  Ifthefirsthashslotfails,analternatehashfunc=onisusedtolookinanotherslot Allthesestepsaredoneinhardware!

§  HashedTableistypically2to3=meslargerthanthenumberofphysicalpages

§  ThefullbackupPageTableismanagedinsoNware

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BaseofTable

hashOffset + PAofSlot

Primary Memory

VPNPPN

PageTableVPN d 80-bitVA

VPN

VMfeaturestrackhistoricaluses:§  Baremachine,onlyphysicaladdresses

–  Oneprogramowneden=remachine§  Batch-stylemul=programming

–  SeveralprogramssharingCPUwhilewai=ngforI/O–  Base&bound:transla=onandprotec=onbetweenprograms(supportsswappingen=reprogramsbutnotdemand-pagedvirtualmemory)

–  Problemwithexternalfragmenta=on(holesinmemory),neededoccasionalmemorydefragmenta=onasnewjobsarrived

§  Timesharing–  Moreinterac=veprograms,wai=ngforuser.Also,morejobs/second.–  Mo=vatedmovetofixed-sizepagetransla=onandprotec=on,noexternalfragmenta=on(butnowinternalfragmenta=on,wastedbytesinpage)

–  Mo=vatedadop=onofvirtualmemorytoallowmorejobstosharelimitedphysicalmemoryresourceswhileholdingworkingsetinmemory

§  VirtualMachineMonitors–  Runmul=pleopera=ngsystemsononemachine–  Ideafrom1970sIBMmainframes,nowcommononlaptops

•  e.g.,runWindowsontopofMacOSX–  Hardwaresupportfortwolevelsoftransla=on/protec=on

•  GuestOSvirtual->GuestOSphysical->Hostmachinephysical 24

VirtualMemoryUseToday-1§  Servers/desktops/laptops/smartphoneshavefulldemand-pagedvirtualmemory–  Portabilitybetweenmachineswithdifferentmemorysizes–  Protec=onbetweenmul=pleusersormul=pletasks–  Sharesmallphysicalmemoryamongac=vetasks–  Simplifiesimplementa=onofsomeOSfeatures

§ Vectorsupercomputershavetransla=onandprotec=onbutrarelycompletedemand-paging

§  (OlderCrays:base&bound,Japanese&CrayX1/X2:pages)–  Don’twasteexpensiveCPU=methrashingtodisk(makejobsfitinmemory)

–  Mostlyruninbatchmode(runsetofjobsthatfitsinmemory)–  Difficulttoimplementrestartablevectorinstruc=ons

§ ModernGPUsoperatesimilarlytovectorsupercomputers,withtransla=onandprotec=onbutnotdemandpaging

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VirtualMemoryUseToday-2

§ MostembeddedprocessorsandDSPsprovidephysicaladdressingonly– Can’taffordarea/speed/powerbudgetforvirtualmemorysupport

– ONenthereisnosecondarystoragetoswapto!– Programscustomwri_enforpar=cularmemoryconfigura=oninproduct

– Difficulttoimplementpreciseorrestartableexcep=onsforexposedarchitectures

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Acknowledgements

§ ThiscourseispartlyinspiredbypreviousMIT6.823andBerkeleyCS252computerarchitecturecoursescreatedbymycollaboratorsandcolleagues:–  Arvind(MIT)–  JoelEmer(Intel/MIT)–  JamesHoe(CMU)–  JohnKubiatowicz(UCB)–  DavidPa_erson(UCB)

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