CRC AND TRANSMIT ERROR REPORT

ENG. ALEX LEVY QA/QC SEISMIC CONSULTANT

[email protected]

1

CRC & TRANSMIT ERROR

Introduction: The land seismic theory and operations are about producing an excitation (by a source) to the land and “listening” (Travel Time) the wave from the “objective” to the surface.

How this wave is acquired and transmitted is a very complex process which involves:

Analog to Digital Conversion,

Multiplexing and Demultiplexing,

Sigma-Delta Filter Application,

Convolution process,

Communications protocols (TCP-IP; Ethernet) and so many others stages that we are going to cover during this presentation.

This document is based on a Sercel System Model 428XL. In the Appendix are explained all the concepts marked as A#XX


[email protected]

2

THE SEISMIC SERCEL NETWORK

The complete system can be described into 4 nodes:

1. Control Node: Server and Human Control Interface (e428 Client Software) 2. Recorder Node: LCI 3. Data Buffer Node: LAUX, LAUL, LRU 4. Acquisition Node: FDU, DSU3, DSU1.

A. The samples of seismic data are always from the Acquisition Node to the Data Buffer Node. B. The samples are analyzed and compressed by the Data Buffer Node and finally sent directly to

the Control Node through the Asynchronous protocol. C. The status and result are sent to the Recorder Node for analysis through the asynchronous

protocol too.

Communication Protocol: Communication between LAU and FDU:

On Line only @ 8 or 16 [Mbps]. Use SYNCHRONOUS COMMUNICATION. LAU Master to FDU: Commands FDU to LAU Slave: Seismic Data and Status.

Communication between LAU or LCI and LAU On Line or Transverse @ 8 or 16 [Mbps]. Use ASYNCHRONOUS COMMUNICATION. Full duplex. (A#1). Automatic routing. Broadcast possibilities. Multi-Transverse possibilities CRC Error Checking.


[email protected]

3

The protocol used on Line and secondary Transverse @ 8 or 16 [Mbps] is a TCP IP protocol. The TCP IP protocol description: The TCP/IP Protocol can be split into 4 layers as an standard TCP IP Protocol, so: Layer 1:

PHYSICALL Layer: Interface between Hardware and Software Communication

between 2 adjacent LAU’s.

Encode cells.

Packet CRC checking. Layer 2:

Data Link Layer: Point to Point communication (P2P).

Communication between 2 adjacent LAU’s.

Frame management.

Frame CRC Checking. Layer 3:

NETWORK Layer: Routing management.

Communication between 2 Lau’s or LCI or Server.

Packets management. Layer 4:

TRANSPORT Layer: Communication between 2 Lau’s or LCI or Server

Message management by MULTIPLEXING / DEMULTIPLEXING (A#2)


[email protected]

4

ENCAPSULATION OF THE DATA:

16 [Mbps] Frame

The 16[Mbps] frame is used in the Line The protocol used on the Transverse @ 100 [Mbps] is a STANDARD EHTERNET PROTOCOL.

Module’s Description and Basic Connections:

Done in the LCI: - Interfacing with the links. - Generating the Firing Order and sensing the Time Break. - Seismic line management and control. - Auxiliary links control. - Collecting system status data to be returned to the HCI (Human Control Interface).

Done in the 428XL Server (PRM and HCI applications) - Collecting the data from the links (Done by the Server). - Noise editing (Zeroing/Clipping/Diversity Stack). - Correlation and Stacking.


[email protected]

5

Pipeline Architecture:

The block handles the data as a pipeline.

They are able to process the data from different acquisitions at the same time. This Allow the 428XL to offer a zero dead time. I.E.: no delay between

consecutive acquisitions. As a result, the vibrator drivers and dynamite shooters do not have to wait for the system to be ready!

LCI Architecture It contains three boards:

a. LPBX: Blaster Board Interface. b. LPWX: Power Management Board. c. LPXL: Line and Transverse Management.

a. LPBX: Blaster Board Interface:

- This board manages the Synchronization of the spread. - This clock is tuned @ 16,384[MHz] +/- 1 ppm (1 part per million).

Main components used on LPBX: - TCXO: 16,384[MHz] Reference Clock for Line Synchronization. - TCXO2: 17,920[MHz] Reference Clock for DPG Synchronization.

b. LPWX: Power Management Board: - Manages all the different power supply need by the other cards. - Uses MosFet Transistor Technology:

The advantages of using this technology are: Allows to manage a very high frequency for the power supply. Reduction in the working temperature. Reduction of components size.

c. LPXL: Line and Transverse Management: - The board is able to manage the communication through the LINE and the TRANSVERSE.

Important: Remind that the LINE speed is 8[Mbps] or 16[Mbps] and TRANSVERSE speed is

100[Mbps]. The Flash Memory that the LCI has contains all the programs for the DSP, FPGA and IBM.


[email protected]

6

DATA Exchange between LINE – LCI – 428XL Server

For the SlipSweep + Navigation the Default Mode is Continuous Asynchronous Mode. Acquisition Modes: - An Acquisition is a set of Elementary Acquisitions - The Elementary Acquisition is always started by a T0 and the length of this Elementary Acquisition

is limited. - In the Asynchronous Mode (SLIPSWEEP MODE) for the FIRST T0 the LAU SYNCHRONIZE the

Acquisition and for the following T there’s no re-synchronization. - In case of Error found by the LAU during the Acquisition, the only solution is to reset the LAU

MEMORY is an Abort from Operator then apply LINE OFF/ON.

Retrieve Mode: The Continuous Asynchronous Mode will be the default mode for the 428XL.

Errors Management: On Samples – Overscalling:

An error message is able to be generated every 16 samples. What’s more, the PRM application will do a summary of the error for the complete Acquisition.

On Acquisition – AcqError due to link unplugged during Acquisition:

An Error message is able to be generated every 16 samples. The LAU will not transmit the blocks (16 samples) of the default traces. The Samples value missed are replaced by the value 0

On LAU Memory – Memory Overflow: All traces concerned by the trouble are non-valid.

Acquisition synchronization trouble – T0 too Early: Non applicable for SlipSweep Mode.

Transmission Error During Retrieve - Transmit Time-out: the Operator has the possibility to Retry, Cancel, or Record the Retrieve.


[email protected]

7

Topology for the Sercel Land Equipment The SPREAD includes:

- FDU - LAUL - LAUX - Recording Truck: LCI, Server, Etc.

FDU – FIELD DIGITIZER UNIT

The main role of the FDU is to DIGITIZES the Seismic Data. The FDU CONVERTS the analog data coming from the geophone to a digital one and send the digital data to the LAUL after that, the data will go to the LAUX and finally to the LCI. The Analog to Digital conversion is based on a SIGMA DELTA CONVERTER which works @ 256 [KHz]. The output from the Sigma Delta Converter is a sample of 24 bits @ 4 [KHz] frequency (The 4[KHz] frequency is due to the sample rate of 0.25[ms], so f= 1/0.25[ms]= 4 [KHz]).


[email protected]

8

FDU MAIN COMPONENTS:

a. Power Supply that generates 6.3[v] for the analog part of the board and 2.7[V] for the digital one.

b. FDU-INT that reshapes the signal, and contains the 2 PLL’s (A#3) used to synchronize the FDU c. FDU-COM that manages the communication with the LAUL, processes the data: performs a first

decimation (rate 64) from 256[KHz] to 4 [Khz] and manages the other functions. d. Sigma-Delta Converter that converts the analog signal from the geophone to a digital bit stream

@ 256 [KHz]. e. EEPROM contains the FDU’s identity and the calibration parameters.

Initialization Sequences The INITIALIZATION is done once the FDU is power-on. The process consists in 4 steps:

- CLOCK SYNCHRONIZATION: The PLL’s in the FDU-INT are synchronized with the data clock @ 8.192[MHz] or 16.384[MHz].

- ALIGNMENT: The FDU-COM detects the beginning of the data frames. The FDU can now interpret

the orders coming from the equipment.

- ORIENTATION PHASE: As the FDU can be connected either way, so, an automatic internal orientation is done at this stage in order to select the active and passive pair.

- INITIALIZATION TESTS: Field test of the string and Instrument Tests.

Seismic Data Path The data is scrambles to transfer white noise (A#4) on the line, to have a better synchronization of the field units.


[email protected]

9

A CRC IS INSERTED TO ENABLE THE LAU TO DETECT ANY TRANSMISSION TROUBLE

Geophone Data Path The analog data is converted into a 24 bits with a 0.25[ms] Sample Rate (SR) and then sent to the LAUL where it is filtered (linear or minimum phase filter), decimated, compressed and sent to the CM.

FDU

A phase comparison between the data and the clock (output of the VCO (1)) is done. Then the voltage generated by the phase comparator (2) is filtered and amplified before being applied to the VCO. According the input of the VCO (Tension or Voltage value), the VCO delivers a new signal with a new frequency. The comparison is done until the phase comparison is not null. In each LAUL an additional PLL performs and extra jitter filtering (A#5) in the forward path. The clock Synchronization circuitry is also implemented in the LAUL, LAUX, and LCI


[email protected]

10

ACQUISITION CHANNEL CIRCUITRY

Definition:

ADC Analog to Digital Converter, a device that will convert an analog signal into a digital one.

DSP (A#6) Digital Signal Processing.

Description: The signal acquisition circuitry is composed by the following four circuits:

Input filter (FDU): Performing initial high-cut filtering and some noise cancellation.

Modulators (FDU): Consisting of a Delta Sigma (∑-Δ) Analog to Digital converter (∑-Δ ADC). Delay Memory (Used in LAU Slave): Consisting of a RAM used to provide temporary storage

for signal processing and remove the sample skew by synchronizing the start acquisition. It is important to take into account that the RAM (Random Access Memory) is cleared (all data is deleted) once the line status is power-off.

Digital Signal Processors (FDU and used in LAU Slave): Removing all that is of no use (including the quantization noise and high frequency components.


[email protected]

11

Analog to Digital Converter (ADC) – How it works:

Conventional ADC: Any ADC will take the value of the analogue signal at the time t and will convert it to a digital value (here 4.5v). Then it will do the same at time t+1 (here 1.25V) and so on:

Aliasing Effect: In the example below we assume Fmax is the maximum frequency in the signal spectrum. So, Fs/2 must be greater that Fmax (Fs>2Fmax), this is in order to AVOID ALIASING EFFECT.

In case of aliasing, the original signal cannot be recovered.


[email protected]

12

Quantization Error: Assuming that a properly sampled signal like the one showed in below.

The conversion from an analog signal to a digital one gives a quantization error.

Let’s analyze an example with 8 bits: 8 bits allow us to read 28. Then we will have 256 different values on a 5[V] Scale.

This means that the quantization error will be: 5

256=20[mV]

For example, with a 9 bits, we can read 512 different values, with a quantization error of 10 [mV].

Oversampling:

In seismic data acquisition the maximum frequency of interest is 500 [Hz].

As a result, the sampling frequency should not be less than 1[KHz] (done by 2xFmax). The 428XL has a sampling frequency of 256[KHz], then, the oversampling ratio is 256.

Advantages of OVERSAMPLING:

Easier ANTIALIASING.

Bit Gain All ADC generate WHITE NOISE. This noise (known as quantization noise) is evenly

spread across the range from 0[Hz] to Fs/2.

By Oversampling @ 256[KHz] the quantization noise is spread from 0[Hz] to 128[KHz] with a lower level.


[email protected]

13

Sercel Delta Sigma Converter (∑-Δ)

Input Protection:

- High Frequency (HF) noise elimination. - Antialiasing filter for oversampling frequency (256[KHz]

How it works:

- The digital signal generated by the ∑-Δ converter is encoded as a 1-bit stream and transmitted on a serial line.

- That is why, a Digital Signal Processor (DSP) is used to convert the serial signal to a parallel 24-bit signal @ 4[KHZ] (T=0.25[ms])

- By INCREASING the order of the ADC (we can achieve this connecting in cascade mode/configuration) and increasing the oversampling ratio, then, the SIGNAL-TO-NOISE RATIO and the CONVERTER’S DYNAMIC RANGE and RESOLUTION ARE INCREASED.


[email protected]

14

Noise Shaping: Many bits can be gained if the noise is shaped:

A DIGITAL CONVERTER CONSIST OF AN ADC, DAC AND AN AMPLIFIER

The aim of noise shaping is to decrease noise at low frequencies. So the transfer function applicable for the noise shaping is:

Qa= A/D quantization noise Qd= D/A errors


[email protected]

15

So; Qa is the quantization error relative to the 1-bit ADC. This is 50% error

Qd is the error relating to the 1 bit DAC. It is virtually zero, only caused by the noise of the DAC

H must be designed such that its value is very high (𝟏𝟎𝟔), and in the band of interest (e.g. 0 to 1000[Hz], and very low (aprox. =0) out of the band of interest. Assuming Qd is negligible:

DELAY MEMORY (LAU)

Description: The RAM DELAY memory or called also ROTATING BUFFER, is located in the LCI board, LAUL, and LAUX. It is the key element, permitting the following functions to be performed:

Data Storage for digital signal processing Removal of sampling skew. Implementation of different anti-aliasing filter characteristics.


[email protected]

16

Data Processing

a. Sample Skew Processing: When a control word is sent to the field units, a delay of a few

milliseconds arises between the moment the first unit receives the word and the moment the last one receives it. Each repeater brings about a delay of 1.5[µs] and cables give rise to a delay of 5[ƞs] per meter. That is why, the start of all FDU must be synchronized and we need to use the following method to do it. After the line is formed, each station unit starts to acquire data. This is fed to the FDU, then the LAU and displayed on the HCI (Human Computer Interface) into the screen (Seismonitor in Jline environment), but it is not recorded. The memory of the LAU Slave gets filled up and retains the latest samples milliseconds of data.

During the line forming, the microcontroller (µcontroller) (of the LAU master for each segment and the LCI) determines the delay corresponding to the time associated with the selected filter, plus the delay associated with the propagation time for the messages between the acquisition module and each link.

As a result, the first data processed is the data that was recorded before the order to start acquisition was received.

b. DATA MEMORY DELAYS: Some delays are required in order to implement the required

convolution process. They depend on the sample rate and the filter type.

Filters Used The decimators are used to perform three functions:

a. Achieving a high-cut filter (anti-aliasing), which is required because the signal is under-sampled. b. Decimating the data from 256[KHz] to the sample rate. c. Applying a linear-phase filter (no phase shift) or minimum-phase filter to the data.


[email protected]

17

LAUX

Function: In our case study we are going to mention the more characteristics features of the LAUX: a. Same functionalities as LAUL b. Multipath capabilities c. Rerouting capabilities d. For more features check the User’s manual.

How it Works: The LAUX wakes up by sensing the voltage on its 4 transmission ghost pairs (hablar del ghost

pairs) (minimum VDC=5[V]), then supplies both sides with the +/-24[V] on each transmission ghost pair and the transverse transmission ghost with a DC voltage to wake up the next LAUX and so on.

The LAUX power on/off is software controlled and therefore any part of the spread can be powered OFF if wanted on the HCI (Human Computer Interface).

The LAUX contains two independent boosters to supply its two sides. The LAUX will work correctly if the voltage is above 10,5[V].

This field equipment interfaces the lines to the CM (Control Module) and also collects, decimates, filters, and compresses the data before sending it to the Server (Seismic Data) or to the LCI (Status, results). It also synchronized all the samples with the time break. The sample rate can be 0.25[ms], 0.5[ms], 1[ms], 2[ms], 4[ms].

LAUX Architecture: It has

A transverse and a line interface (PLL, signal shaping) An IBM403 (µcontroller) Peripherals DSP (to decimates, filters and compressing the data) It is made of 1 sandwich box which contains two boards:

LPWX (Line Power Crossing board) board containing the boosters and Power supply of the unit, the equalizers and the PLL’s.

LPXL (Line Processor Crossing and Line board) board containing the digital hardware.

LPWX Board: Provides

The charger for the Line Tester; 9.5[V] The waking bloc that produces a 3.3[V] to manage the power-up circuits. The power control block that manages everything and check the leakage. The battery control block that protects the boards against and over-voltage. ADC that measures the voltages.

LPXL Board: This board runs the program stored in the flash memory. Also managed the FDU and

process the data. LPXL Board Architecture: Its main architecture contains the following components:

a. Digital Signal Processing (DSP): Decimates, filters and compress the data b. Flash memory: Used to store the program. c. DRAM: One is used by the DSP to process the data, the other one by the IBM. d. IBM 405: Microprocessor @ 33[MHz]. e. DPR: Dual Port Ram, interfaces between the different buses. f. FPGA: Interfaces with the LIPX board. g. UART: Communication device to Xdev plug (TMS, LT).


[email protected]

18

h. EhtPhy: Component for Ethernet management.

LAUL

Function: High Storage Memory capacity for non-Real Time operation.

Receives/Transmit FDU statuses and results.

Power supply the line @ 50[V].

How it works: It wakes up by sensing voltage on the transmission ghost lines, then supplies with voltage the

opposite transmission ghost line

It interprets the orders coming from the LCI or 428XL Server, controls a line of FDU (up to 120 channels depending on interface) and collects the data from them.

On the data it performs: Decimating, Filtering, Compressing After all these it sent back information to the LCI (status) or 428XL Server (Seismic Data),

through the LAUX. Synchronizes all the samples with the Time Break.

LAUL Architecture: It is made of only 1 board:

LPL16 (Line Processor Land board and 16 stands for 16[Mbps] – It means 16 Mega-bits-per-second).

Cables The Transmission is made using two pairs between all the elements: LCI, LAUX, LAUL, and FDU.

Cables Constitution:

The transverse and the line cable are exactly the same. It is important to know about the type and main characteristic of the Sercel Cables:

o Standard: ST+6.5mm(0.25in) o Waterproof: and traction resistant: WPSR 9.5mm (0.37), with a Kevlar braid. o Waterproof: and traction resistant long range: WPSR-LR 9.5mm, with a Kevlar braid Must be

used in the secondary transverse only with LAUX408. o EXT: 0.27mm (0.31in), extension cable that can be used in the transverse only with LAUX 408.


[email protected]

19

GHOST PAIRS: The new transverse has +/-24[V] power control. It’s why we fin again “Booster” power

supply for the transverse management in the LPWX board into the LAUX. The data transmission is done on 2 pairs and the power supply is re-built with the Ghost Pairs. Those signals are conveyed by the ghost pairs that make use of the transmission pairs.


[email protected]

20

The ghost pair transmits the power supply (+/-24[V]) for the line and the transverse.

CRC & TRANSMIT ERROR

The 428XL system uses a synchronous transmission @ 8192[MHz] or 16.384[MHz] on LINES and 100 [Mbps] Ethernet on TRANSVERSES.

The transmission bits are organized in frames occurring every 1[ms].

The frames are generated by the 428XL (LCI) central unit on its Left and Right Transverses, and replicated by each LAUX on its Low and High Port.

A frame is composed of 64 cells: The first cell is the frame header; the next 63 ones are

dedicated to LAU/LAU or FDU/LAU communications.

A cell is 16 bytes long on Lines and 32 bytes long on Transverses.

1 Byte = 16 bits

1 bit = 0 or 1 digital level (0 digital = 0[V] and 1 digital = 5[V])

Each cell is composed of three parts: a. Cell header containing control bits (one byte). b. Cell data (14 bytes on Line, 30 bytes on Transverse). c. Cell CRC (one byte).

The FRAMES are used to implement TWO Communication Schemes as described:

1. FDU/LAU communication (LOW LEVEL PROTOCOL), each FDU writes 4 samples in a cell data field.

- The addressing mode uses a token mechanism: each FDU writes its data in the first free cell following a frame header and sets a busy bit (in the cell header). The addressing mode is then sequential, so the next FDU writes its data in the next DATA CELL.


[email protected]

21

- The communication is SYNCHRONOUS with FDU acquisition and provides an error detection mechanism using the CRC field.

2. LAU/LAU communication (High Level Protocol) - FDU samples received by an LAU are processed and compressed to form packets that are sent back

to the 428XL central unit. - There is no time relation with FDU acquisition: A High Level Protocol with error detection and

recovery is implemented.

Time Synchronization:

The FDU samples the analog input using a 256[Kbits/s] sigma-delta converter. The sampling clock is derived from the 8.192[MHz] line frequency. The FDU perform a first decimation process to produce 24-bit sample @ 0.25[ms] sampling rate. Four 0.25[ms] samples are written into a cell every 1[ms]. The time difference between the generation of the 428XL frame and sampling by each FDU is

measured at line power-on with a precision of 122[ns]. This value (called T1) is measured and stored in each LAU for each FDU it controls.

The frame header sent by the 428XL central unit contains the T0 information. The information is received by all LAU’s and FDU’s

An LAU or FDU decodes T0 if the CRC of the frame header is correct. The T0 information is repeated three times.

The TB from the shooting system is not synchronous with the generation of the 428XL frame. When TB occurs, the 428XL measures the time from TB to the start of the next frame with a precision of 488[ns] and writes the T0 information and the measured time (called T2) in the next frame header. The LAU uses T1+T2 time to have the data received from FDU’s synchronized with T0.

LAU Acquisition: The LAU contains two processor

1. DSP processor: This processor runs two independent processes: 1.1. Process 1: - Receives incoming frames, - Decodes cells, - Check cell consistency and CRC, - Extract samples and stores into a 512[ms] circular buffer.

1.2. Process 2:

- Reads samples from the circular buffer - Performs convolution and decimation to generate acquisition samples at the user

sample rate.


[email protected]

22

- Compresses them into packets of 16 scans and sends the compressed packets to the IBM processor

2. IBM403 processor: - This processor stores compressed packets into an acquisition buffer. - The acquisition buffer is sent to 428XL central unit upon request using the LAU/LAU protocol. - This phase (called retrieval) can be done at later date compared to acquisition.

Transmit Error Effects The TRANSMIT ERROR AFFECTS THE LINE TRANSMISSION DIFFERENTLY DEPEENDING ON THE PROTOCOL USED:

FDU to LAU Communications:

When receiving a frame from the line, the LAU checks for cell consistency. When a cell CRC error is detected, the corresponding path is displayed in orange. If frame headers are unaltered, the acquisition continues. If frame headers are altered, then the acquisition stops with an error such as frame

error or token error.

LAU to LAU Communications:

The transfer of compressed sample packets from LAU to the 428XL central unit uses the

high level protocol. If a transmit error occurs, a packet CRC error is detected, the wrong packet is discarded

and repeated. Transmit error have no effect on this type of communication.


[email protected]

23

CRC error handling algorithm

An algorithm is implemented that minimizes the effect of random transmit error upon acquisition and allows the acquisition to continue, in event of CRC errors, rather than stopping with and error message.

In any frame where a CRC error occurs, the four 0.25[ms] samples of each FDU are replaced by the four corresponding samples of the previous frame.

As the 0.25[ms] FDU samples are then filtered, the result is an “interpolation” (A#7) (@ 2[ms] sampling rate, the duplicated samples are convoluted with 508 samples around).

The corresponding path is displayed in orange. The trace affected by CRC error during the acquisition are marked as “edited” in the SEGD

record. The Trace Edit Field in demultiplexed trace header is set to 03.

Case Study: In order to better explanation of how the CRC error handling algorithm works, a practical case is showed below, in which a CRC error is generated during the acquisition of an FDU test sin wave @ 31.25[Hz] for all sampling rates. The trace altered by the CRC (seis5441) is captured by the SGA along with a reference trace (seis5436).


[email protected]

24


[email protected]

25


[email protected]

26

Effect of consecutive CRC ERRORS: We are going to see a CRC error on all acquisition frames during 20[ms] every 100[ms] and 2[ms] sampling rate. The acquisition signal is a 31.25[Hz] sine wave. The trace altered by CRC Errors is displayed in red and can be compared with a normal trace displayed in brown.

APPENDIX: (A#1) Full Duplex:

Send/Receives larger amount of data.

Send/Receives data at the same time.

There is no danger of collision and therefore the transfer data is completed!

A full duplex link can only connect two devices, so, in case of multiple devices connection a lot of links must be done.


[email protected]

27

A full duplex link can only connect two devices, so many links are required if multiple devices are to be connected together

In a Full Duplex 10Base-T Ethernet environment, the two host would have two channels, separating out transmit and receive.

(A#2) Multiplexing/Demultiplexing:

Multiplexing is a method by which multiple analog message signals or digital data streams are

combined into one signal over a shared medium.

The multiplexed signal is transmitted over a communication channel.

The multiplexing divides the capacity of the communication channel into several logical channels,

one for each message signal or data stream to be transferred.

A reverse process, known as demultiplexing, extracts the original channels on the receiver end.

A device that performs the multiplexing is called a MUX, and a device that performs the reverse

process is called DEMUX or DMX.

(A#3) PLL: The digital PLL is really just an analog PLL with a digital phase detector.

The DPLL is a hybrid system

The DPLL is very popular in synthesizer applications

In the figure the optional digital divider, and variations on it, are used in frequency synthesis applications.

Popular types of digital phase detectors include: – Exclusive or gate (EXOR) – Edge-triggered JK-flipflop – Phase frequency detector (PFD)

In digital communications various levels of synchronization are required

The synchronization problem can be viewed as one of parameter estimation from waveforms

The PLL is used to SYNCHORNIZE THE FDU.

https://en.wikipedia.org/wiki/Shared_medium

https://en.wikipedia.org/wiki/Communication_channel


[email protected]

28

(A#4) White Noise: White noise is defined as an uncorrelated noise process with equal power at all frequencies

(Figure 2.1).

A noise that has the same power at all frequencies in the range of ±∞ would necessarily need to

have infinite power, and is therefore only a theoretical concept.

However, a band-limited noise process, with a flat spectrum covering the frequency range of a

bandlimited Communication system, is to all intents and purposes from the point of view of the

system a white noise process.

(A#5) Jittering Effect: Jitter effect may be caused by electromagnetic interference (EMI) and crosstalk with carriers of other signals. Jitter can cause a display monitor to flicker, affect the performance of processor, introducing clicks or other undesired effect in audio signals, and loss of transmitted data between network devices. The amount of tolerable jitter depends on the affected application. In analog to digital and digital to analog conversion of signals, the sampling is normally assumed to be periodic with a fixed period (the time between every two samples is the same) If there is jitter present on the clock signal to the analog-to-digital converter or a digital-to-analog converter, the time between samples varies and instantaneous signal error arises. The error is proportional to the slew rate of the desired signal and the absolute value of the clock error. Various effect such as noise (random jitter), or spectral component (periodic jitter) can come about depending on the patter of the jitter in relation to the signal. In some conditions, less than a nanosecond of jitter can reduce the effective bit resolution of a converter with a Nyquist Frequency of 22[KHz] to 14 bits.

This is a consideration in high-frequency signal conversion, or where the clock signal is especially prone to interference. Anti-Jitter circuits: Anti-Jitter circuits (AJC’s) area a class of electronic circuits designed to reduce the level of jitter in a regular pulse signal. AJC’s operate by re-timing the output pulses so they align more closely to an idealized pulse signal. They are widely used in clock and data recovery circuits in digital communications, as well as for data sampling systems such as the analog-to-digital converter and digital-to-analog converter. Examples of anti-jitter circuits include phase-locked loop and delay-locked loop. Inside digital to analog converters jitter causes unwanted high-frequency distortions. In this case it can be suppressed with high fidelity clock signal usage.


[email protected]

29

ABFT Frequency Translator is designed to attenuate jitter / phase noise; accompanied with a 10MHz Reference Signal - while up-converting the input frequency by times two or times 4. This solution maintains phase & frequency cohesion to the 10MHz input reference. The approached employed in the ABFT design is a non-traditional Phase Locked Loop; ensuring significant jitter clean-up, very close-to-the-input carrier.

If ABFT is driven from a Noisy 10.00MHz reference, the intrinsic phase noise of the ABFT device will take over; starting at about 1kHz offset and will be typically better than -150dBc/Hz @ 10kHz away from the carrier. This will yield better than 0.50 ps. rms jitter over 12kHz to 20MHz BW, regardless of the input reference noise.


[email protected]

30

(A#6) Digital Signal Processing (DSP):

(A#7) Interpolation: Interpolation is a method of constructing new data points within the range of a discrete set of know data point. In engineering and science, one often has a number of data points, obtained by sampling or experimentation, which represent the values of a function for a limited number of values of the independent variable. It is often required to interpolate (estimate) the value of that function for an intermediate value of the independent viable.

References: - Sercel User’s Manual 1; 2; 3; Technical Manual - Data Communication Fundamentals; By Kharagpur - Phase-Locked Loops with applications ECE 5675/4675 Lectures Note Spring 2011; By Mark A.

Wickert. - Advanced Digital Signal Processing and Noise Reduction; By Saeed V. Vaseghi. - Crystals Oscillators Real-Time-Clocks Filters Precision Timing Magnetics Engineered Solutions;

Abracon Corporation.

CRC AND TRANSMIT ERROR REPORT

Engineering