1 - CPRE 583 (Reconfigurable Computing): VHDL overview 4: Common VHDL Mistakes Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 7: 9/14/2011 (Common VHDL Mistakes: “It works perfect in simulation, but not in the hardware!” ) Instructor: Dr. Phillip Jones ([email protected]) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.e du/cpre583/
CPRE 583 Reconfigurable Computing Lecture 7: 9/14/2011 (Common VHDL Mistakes: “It works perfect in simulation, but not in the hardware!” ). Instructor: Dr. Phillip Jones ([email protected]) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA. - PowerPoint PPT Presentation
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1 - CPRE 583 (Reconfigurable Computing): VHDL overview 4: Common VHDL Mistakes Iowa State University (Ames)
CPRE 583Reconfigurable Computing
Lecture 7: 9/14/2011(Common VHDL Mistakes: “It works perfect
2 - CPRE 583 (Reconfigurable Computing): VHDL overview 4: Common VHDL Mistakes Iowa State University (Ames)
• MP1: Due Next Friday. We will push MP2 back a week and cut it from 3 weeks to 2 weeks
• Mini literary survey assigned– PowerPoint tree due: Fri 9/23 by class, so try to have to
me by 9/22 night. My current plan is to summarize some of the classes findings during class.
– Final 5-10 page write up on your tree due: Fri 9/30 midnight.
Announcements/Reminders
3 - CPRE 583 (Reconfigurable Computing): VHDL overview 4: Common VHDL Mistakes Iowa State University (Ames)
• Start with searching for papers from 2007-2010 on IEEE Xplorer: http://ieeexplore.ieee.org/– Advanced Search (Full Text & Meta data)
• Find popular cross references for each area
• For each area try to identify 1 good survey papers
• For each area– Identify 2-3 core Problems/issues– For each problem identify 2-3 Approaches for addressing – For each approach identify 1-2 papers that Implement the
if (sel = ‘1’) then a_out <= a; data_out <= my_data; end if;
end process;
process (clk)begin -- check for rising edge of the clk if(clk’event and clk = ‘1’) then
-- initialize all driven signals during reset if(reset = ‘1’) then a_out <= x”00”; data_out <= x”00”; else if (sel = ‘1’) then a_out <= a; data_out <= my_data; end if; end if;
end if;end process;
11 - CPRE 583 (Reconfigurable Computing): VHDL overview 4: Common VHDL Mistakes Iowa State University (Ames)
State Machine Structure -- Assign STATE to next stateprocess (clk)begin -- check for rising edge of the clk if(clk’event and clk = ‘1’) then
-- initialize all driven signals during reset if(reset = ‘1’) then STATE <= S1; else STATE <= Next_STATE; end if;