1 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 8: 9/17/2010 (VHDL to FPGA: A Tool Flow Overview ) Instructor: Dr. Phillip Jones ([email protected]) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http:// class.ece.iastate.edu/ cpre583/
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CPRE 583 Reconfigurable Computing Lecture 8: 9/17/2010 (VHDL to FPGA: A Tool Flow Overview )
CPRE 583 Reconfigurable Computing Lecture 8: 9/17/2010 (VHDL to FPGA: A Tool Flow Overview ). Instructor: Dr. Phillip Jones ([email protected]) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA. http://class.ece.iastate.edu/cpre583/. Announcements/Reminders. - PowerPoint PPT Presentation
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1 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
CPRE 583Reconfigurable Computing
Lecture 8: 9/17/2010(VHDL to FPGA: A Tool Flow Overview )
Reconfigurable Computing LaboratoryIowa State University
Ames, Iowa, USA
http://class.ece.iastate.edu/cpre583/
2 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
• HW2: will be released by 5pm Friday
• MP2: Make sure to get starting ASAP!– Make sure to read the README file in the MP2 distribution
• Contains info on how to fix a Gigabit core licensing issue ISE has
• Mini literary survey– PowerPoint tree due Today.– Final 5-10 page write up on your tree due: Fri 9/24
midnight.• Should tell the story of your literary tree
– Week extension for those that decide today they may what to do a survey on today’s topic
Announcements/Reminders
3 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
• Start with searching for papers from 2007-2010 on IEEE Xplorer: http://ieeexplore.ieee.org/– Advanced Search (Full Text & Meta data)
• Find popular cross references for each area
• For each area try to identify 1 good survey papers
• For each area– Identify 2-3 core Problems/issues– For each problem identify 2-3 Approaches for addressing – For each approach identify 1-2 papers that Implement the
approach.
Literary Survey
4 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
Literary Survey: Example Structure
Network Intrusion Detection
P1 P2 P3
A1 A2 A3 A1 A2 A1 A2
I1 I1 I2 I1 I1 I1 I1 I2 I1
• 5-10 page write up on your survey tree
5 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
Fall 2010 Student Example
6 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
Common Questions
7 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
Common Questions
8 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
Common Questions
9 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
Common Questions
10 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
• Introduction to mapping VHDL to FPGA hardware
• What you should learn– What are the major steps?– What is the basic purpose of each step?
Overview
11 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
• Input Hardware Description Langue (HDL) • Synthesis• Map• Place & Route• Hardware configuration file generation
Major Steps
12 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
Graphical flow
Implement
Simulate
Synthesize
Map
Place
Route
Download
13 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
Major Steps (Text: Chapters 13-20)Z <= (A and B) or C;Input VHDL description
LUTABC
ZTransform primitive to technologydependent primitives (MAP)
ZABTransform VHDL into primitive
gates (synthesis) C
Associate primitive with specificInstances, and connect usingRouting resources (PAR)
LUT
ABCLUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Z
Encode placement and routing description into a configuration file for programming a specific FPGA type
000
ABC000
000
000
000
000
000
101
000
Z
14 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames)
High Level Design Description• VHDL• Verilog• C type languages (e.g. handle C)
– Typically auto transformed into VHDL or Verilog• Schematic capture (I believe ISE has this option)