CPLDs Dr. D. V. Kamath Professor, Department of E&C Engg., Manipal Institute of Technology, Manipal 1
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CPLDs
Dr. D. V. Kamath
Professor, Department of E&C Engg.,
Manipal Institute of Technology, Manipal
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CPLDs
Complex Programmable Logic Device (CPLD)
Multiple PALs integrated together
More Complex PALHigher capacity devicesSingle PAL architecture is not feasible
CPLDs are an extension of the PAL concept
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CPLDs
Typical CPLD die
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CPLD
Typical CPLD architecture
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Altera CPLD
Two Altera versions are available
Altera Flex structure(Flex 8000 series) Altera Max structure (MAX 5000, MAX 7000, MAX 9000 series)
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Altera MAX architecture
(a) Chip floor plan (b) MAX family Logic Array Block(LAB) (c) MAX family macro cell
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Altera MAX architecture
The basic features of Altera MAX architecture are as follows:
Altera MAX CPLD consists of LAB(Logic Array Block)s and chipwideinterconnect
Max family LAB consists of LA(local array) and macro cells
LA consists of wide programmable AND array
The basic logic cell for the Altera MAX architecture, a macrocell, is a descendant of the PAL.
Macro cells comprise of narrow fixed OR array, logic expanders, and programmable inversion
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Altera MAX architecture- Logic expander
Logic expanders
Logic expander is used to generate extra logic terms
Using the logic expander, it is possible to implement functions thatrequire more product terms than are available in a simple PALmacrocell.
The SOP(Sum of Product) expression can be rewritten as “sum ofproducts of products”. We can use logic expanders to implementthe extra product terms (called expander terms or helper terms).
These extra product terms can be shared among other macrocellsif needed. Hence, these extra logic gates that form these shareableproduct terms are called as shared logic expander , or just sharedexpander .
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Altera MAX architecture-Logic expander
Consider the function
𝐹 = 𝐴 CD + 𝐵 CD + AB + B 𝐶
F has 4 product terms and thus F cannot be implemented using a macrocell that has only a 3-wide OR array
F can be rewritten as
𝐹 = 𝐴 + 𝐵 CD + 𝐴 + 𝐶 𝐵
𝐹 = 𝐴. 𝐵 𝐶. 𝐷 + 𝐴. 𝐶 .𝐵
The 𝐴.𝐵 and 𝐴. 𝐶 are the expander terms
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Altera MAX architecture-Logic expander
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Altera MAX architecture- Logic expander
Logic expanders
The disadvantage of the shared expanders is the extra logic delayincurred because of the second pass that may need to take throughthe product-term array. Before the logic assignment stage (assigninglogic to macrocells by logic tools), it is not possible to predictwhether the design need to use the logic expanders.
The timing of the Altera MAX architecture is not strictlydeterministic (i.e., it is not possible to predict the exact timing).
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Altera MAX architecture - Programmable inversion
Programmable inversion allows the logic assignment stage to reduce the number of product terms needed
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Altera MAX architecture - Programmable inversion
Use of programmable inversion to simplify the logic
The function F = A · B' + A · C' + A · D' + A' · C · D requires 4 product terms
But, F ' = A · B · C · D + A' · D' + A' · C' requires only 3 product terms
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MAX 7000 Altera CPLD
Altera MAX 7000
The MAX 7000 family of high-density, high-performance CMOSCPLDs is based on Altera’s second-generation MAX architecture.MAX 7000 series is widely used and offers state-of-the-art logiccapacity and speed performance.
MAX 5000 is an older technology and MAX 9000 is similar to MAX7000, except that MAX 9000 offers higher logic capacity
MAX 7000 devices are available both based in EPROM and EEPROMtechnology
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MAX 7000 Altera CPLD
Altera 7000 series architecture
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MAX 7000 Altera CPLD
Altera 7000 series architecture comprises of LAB(Logic ArrayBlock)s, PIA(Programmable Interconnect Array) and I/O controlblocks
PIA is capable of connecting any LAB input or output to any otherLAB
Also, the inputs and outputs of the chip connect directly to the PIAand to LABs
Each LAB consists of 16 (two sets of 8) macro cells
Each MAX 7000 LAB has 36 inputs from the chip-wide interconnectand 16 outputs to PIA . From 8 to 16 outputs from each LAB can berouted to the I/O pins through the I/O control block. From 8 to 16inputs from the I/O pins can be routed through the I/O controlblock to the PIA
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MAX 7000 Altera CPLD
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MAX 7000 Altera CPLD
The global clock input (GCLK) and global clear input (GCLRn) connectto all macro cells
Two output enable signals (OE1n and OE2n) connect to all I/Ocontrol blocks
The vertical lines in the logic array are common to all of the macrocells in a LAB
The vertical lines are driven with programmable interconnect linesfrom the PIA and from shared expanders
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MAX 7000 Altera CPLD - LAB
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MAX 7000 Macro cell
ACTEL ACT1 Logic module (LM)
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MAX 7000 Altera CPLD
LAB and macro cell
Each macro cell comprises a set of programmable AND plane thatfeeds an OR-gate and a programmable flip-flop.
The flip-flops can be configured as D type, JK, T, SR, or can betransparent
The number of inputs to the OR gate in a macro cell is variable; theOR gate can be fed from any or all of the 5 product terms within themacro cell, and in addition can have up to 15 extra product termsfrom macro cells in the same LAB.
The product term flexibility makes the MAX 7000 series LAB moreefficient in terms of the chip area(The typical logic functions thatdon't need more than 5 product terms, and the architecturesupports wider functions when they are needed)
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Altera Flex architecture
(a) Chip floor plan (b) Flex family Logic Array Block(LAB) (c) Details of the Logic Element(LE)
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