CPLD FPGA

VLSI DesignUNIT-7

Semiconductor IC design

PLAPAL

CPLDFPGA

Standard Cells

Why Programmable Logic devices

• Often, the cost, speed, or power dissipation of a microprocessor may not meet system goals and an alternative solution is required.

• A variety of programmable chips are available that can be more efficient than general purpose microprocessors yet faster to develop than dedicated chips:

• Chips with programmable logic arrays• Chips with programmable interconnect• Chips with reprogrammable logic and interconnect

Programmable Logic Array(PLA)

representation of PLA

• A programmable logic array (PLA) provides a regular structure for implementing combinational logic specified in sum-of-products canonical form.

• They are dense and fast ways to implement simple functions.• Any logic function can be expressed in sum-of-products form;

i.e., where each output is the OR (sum) of the ANDs (products) of true and complementary inputs.

• The inputs and their complements are called literals. The AND of a set of literals is called a product or minterm. The outputs are ORs of minterms.

• The PLA consists of an AND plane to compute the minterms and an OR plane to compute the outputs.

• The most straightforward design for a small PLA uses a pseudo-nMOS NOR gate.

Programmable Logic Array(PLA)

Dot diagram representation of PLA

Programmable Logic Array(PLA)

Programmable Logic Array(PLA)

Pseudo-nMOS PLA reprasentation for Full Adder

Programmable Logic Array(PLA)

Pseudo-nMOS PLA schematic for Full Adder

Programmable Array Logic (PAL)

• The Programmable Array Logic (PAL) is a variation of the PLA. Like the PLA, it has a wide, programmable AND plane for ANDing inputs together.

• However, the OR plane is fixed, limiting the number of terms that can be ORed together. Other basic logic devices, such as multiplexers, exclusive ORs, and latches are added to the inputs and outputs.

Programmable Array Logic (PAL)

PAL Architecture

CPLD vs FPGA

Complex Programmable Logic Devices CPLDs

• Essentially they are designed to appear just like a large number of PALs in a single chip, connected to each other through a crosspoint switchExample CPLD FamiliesSome CPLD families from different vendors are listed below:· Altera MAX 7000 and MAX 9000 families· Atmel ATF and ATV families· Lattice ispLSI family· Lattice (Vantis) MACH family· Xilinx XC9500 family

Complex Programmable Logic Devices CPLDs

Altera MAX 7000 CPLD

Complex Programmable Logic Devices CPLDs

Altera MAX 7000 Logic Array Block (LAB)

Complex Programmable Logic Devices CPLDs

MAX 7000 Macrocell.

Field Programmable Gate Array(FPGA)

Cypress FLASH370 CPLDs

Field Programmable Gate Array(FPGA)

• Field-Programmable Gate Arrays (FPGAs) use the high circuit densities in modern processes to construct ICs that, as their name suggests, are completely programmable even after a product is shipped or “in the field.”

• Two basic versions exist. The first uses a special process option such as a fuse or antifuse to permanently program interconnect and personalize logic. These are one-time programmable.

• The second type uses static RAM or flash memory to configure routing and logic functions.

• In general, an FPGA chip consists of an array of logic cells surrounded by programmable routing resources.

• As an example of the first type of FPGA, devices manufactured by Actel embed an array of logic modules within an interconnect matrix. Routing channels run vertically or horizontally.

• A special one-time programmable contact, called an antifuse, is placed at the intersection of routing traces. These normally have high resistance (effectively an open circuit). Upon application of a special programming voltage across the contact, the resistance permanently drops to a few ohms.

Field Programmable Gate Array(FPGA)

• The chip is composed of an array of configurable logic blocks (CLBs). Metal routing tracks run vertically and horizontally between the array of CLBs.

• These terminate at the gray blocks, which are routing switches that can be implemented using antifuses, CMOS transmission gates, or tristate buffers.

• The routing resources can also be connected to the inputs and outputs of the adjacent CLBs.

• CLBs use programmable lookup tables to compute any function of several variables.

• Configurable I/O cells that can be used as input, output, or bidirectional pads surround the core array of CLBs.

Field Programmable Gate Array(FPGA)

Field Programmable Gate Array(FPGA)

Actel Antifuse Structure

FPGA families: Xilinx Spartan3, Virtex-7

Standard Cells