CPE 626 Advanced VLSI Design Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04F/ [email protected]Assistant Professor Electrical and Computer Engineering Dept. University of Alabama in Huntsville A. Milenkovic 2 Advanced VLSI Design Computer Engineering Methodology Evaluate Existing Evaluate Existing Systems for Systems for Bottlenecks Bottlenecks Simulate New Simulate New Designs and Designs and Organizations Organizations Implement Next Implement Next Generation System Generation System Technology Trends Benchmarks Workloads Implementation Complexity Applications Market A. Milenkovic 3 Advanced VLSI Design Technology Directions: SIA Roadmap Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm 2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735 .580 .255 .110 .049 .022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm 2 ) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183
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Scientific desktops: high-performance FPs and graphicsCommercial servers: support for databases and transaction processing, enhancement for reliability, support forscalabilityEmbedded computing: special support for graphics or video, power limitations
A. Milenkovic 6
Advanced VLSI Design
Gajski and Kuhn’s Y Chart
Physical/Geometry
StructuralBehavioral
Processor
Hardware Modules
ALUs, RegistersGates, FFs
Transistors
SystemsAlgorithms
Register TransferLogic
Transfer Functions
Architectural
Algorithmic
Functional Block
Logic
Circuit
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Domains
Functional –operations performed by the system
Structural – how the system is composed
Geometry – how the system is laid out in physical space
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A. Milenkovic 7
Advanced VLSI Design
The Need for IP CoresBenefits of HDL-based design
PortabilityTechnology independence
Design cycle reduction
Automatic synthesis and Logic optimization
… But, the gap between available chip complexity and design productivity continues to increase
Design productivity21% / year
Chip Complexity 58% / year
⇒ Use IP cores
LaCASA IP Library
A. Milenkovic 8
Advanced VLSI Design
New Generation of Designers …Emphasis on hierarchical IP core designDesign systems, not components!Understand hardware/software co-designUnderstand and explore design tradeoffs between complexity, performance, and power consumption
⇒ Design a soft processor/micro-controller core
LaCASA IP Library
A. Milenkovic 9
Advanced VLSI Design
UAH Library of Soft CoresMicrochip’s PIC18 micro-controller
Microchip’s PIC16 micro-controllerIntel’s 8051
ARM Integer CPU coreFP10 Floating-point Unit (ARM)
Advanced Encryption Standard (AES)Video Processing System on a Chip
LaCASA IP Library
4
A. Milenkovic 10
Advanced VLSI Design
Design Flow for CPU CoresReference Reference ManualManual
InstructionInstructionSet AnalysisSet Analysis
DpthDpth&&CntrCntrDesignDesign
VHDL ModelVHDL Model
VerificationVerification
ASM Test ASM Test ProgramsPrograms
MPLAB IDEMPLAB IDE
iHex2RomiHex2Rom
Synthesis&Synthesis&ImplementationImplementation
C C ProgramsPrograms
C CompilerC Compiler
LaCASA IP Library
A. Milenkovic 11
Advanced VLSI Design
Soft IP Engineering CycleEncompasses all relevant steps
Put together knowledge in digital design, HDLs, computer architecture, programming languagesState-of-the-art devicesWork in teams
Specification
Design
Modeling
Simulation &Verification
FPGA Implementation
Measurements(Compl.&Perf.&Power)
Design Improvements
LaCASA IP Library
A. Milenkovic 12
Advanced VLSI Design
PIC18 Greetings
http://www.ece.uah.edu/~milenka/pic18/pic.html
LaCASA IP Library
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A. Milenkovic 13
Advanced VLSI Design
Designing a simple CPU in 60 minutesLaCASA step-by-step tutorial
Follow the principle that the memory will be limiting factor in design: each instruction takes exactly the number of clock cycles defined by the number of memory accesses it must take.
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Advanced VLSI Design
MU0 Datapath DesignAssume that each instruction starts when it has arrived in the IRStep 1: EX (execute)
LDA S: ACC < - Mem[S]
STO S: Mem[S] <- ACC
ADD S: ACC < - ACC +Mem[S]
SUB S: ACC <- ACC -Mem[S]
JMP S: PC < - SJGE S: if (ACC >= 0) PC <- S
JNE S: if (ACC != 0) PC <- S
Step 2: IF (fetch the next instruction)
Either PC or the address in the IR is issued to fetch the next instruction
address is incremented in the ALU and value saved into the PC
InitializationReset input to start executing instructions from a known address; here it is 000hex
• provide zero at the ALU output and then load it into the PC register
A. Milenkovic 17
Advanced VLSI Design
MU0 RTL OrganizationControl Logic
AselBsel
ACCce (ACC change enable)
PCce (PC change enable)IRce (IR change enable)
ACCoe (ACC output enable)
ALUfs (ALU function select)MEMrq (memory request)
RnW (read/write)
Ex/ft (execute/fetch)
memory
ACC
IRce
PCce
ALUfs
Bsel
ACCce
ACCoe
MEMrq RnW
mux0 1
Asel
ALUAB
PC
ACC[15]ACCz
IR
opcode
MU0
A. Milenkovic 18
Advanced VLSI Design
MU0 control logicInput s Out p ut s
Opc ode Ex / f t ACC15 Bs el PCc e ACCoe M EMrq Ex / f tIn st ruc t i on Res et ACCz As el ACCce IRc e ALUf s RnWReset xxxx 1 x x x 0 0 1 1 1 0 = 0 1 1 0LDA S 0000
000000
01
xx
xx
10
10
10
01
01
00
= BB+1
11
11
10
STO S 00010001
00
01
xx
xx
10
x0
00
01
01
10
xB+1
11
01
10
ADD S 00100010
00
01
xx
xx
10
10
10
01
01
00
A+BB+1
11
11
10
SUB S 00110011
00
01
xx
xx
10
10
10
01
01
00
A-BB+1
11
11
10
JMP S 0100 0 x x x 1 0 0 1 1 0 B+1 1 1 0JGE S 0101