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1

Flip-Flop Applications

Applications of Flip-Flops:Counters

Asynchronous Counter

Synchronous Counter

Register

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Counters

A counter is a sequential machine that produces aspecified count sequence.

The count changes whenever the input clock is

asserted. There is a great variety of counter based on itsconstruction:

Clock: Synchronous or Asynchronous

Clock Trigger: Positive edged or Negative edged Counts: Binary, Decade, Gray

Count Direction: Up, Down, or Up/Down

Flip-flops: JK or T or D

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3

Counters A counteris a register that goes through a predetermined

sequence of states upon the application of clock pulses.

Asynchronous counters

Synchronous counters

Async. counters (or ripple counters)

the clock signal (CLK) is only used to clock the first FF.

Each FF (except the first FF) is clocked by the preceding FF.

Sync. counters, the clock signal (CLK) is applied to all FF, which means that

all FF shares the same clock signal,

thus the output will change at the same time.

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Uses of Counters

The most typical uses of counters are:

To count the number of times that a certain event takesplace

The occurrence of event to be counted is represented bythe input signal to the counter

To control a fixed sequence of actions in a digitalsystem

To generate timing signals

To generate clocks of different frequencies

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Two Classes of Counters

Counters are classified into two categories: Asynchronous Counters (Ripple counters)

Synchronous Counters

Asynchronous: The events do not have a fixed time relationship

with each other and do not occur at the same time. Synchronous: The events have a fixed time relationship with

each other and do occur at the same time.

Counters are classified according to the way they are clocked: In asynchronous counters, the first flip-flop is clocked by the

external clock pulse and then each successive flip-flop is byclocked the output of the preceding flip-flop.

In synchronous counters, the clock input is connected to all of theflip-flop so that they are clocked simultaneously.

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Asynchronous Counters

In asynchronous counter each flip-flop derives its own clockfrom other flip-flops and is therefore independent of the inputclock.

Consequently, the output of each flip-flop may change at

different time, hence the term asynchronous. For the asynchronous counter, the output of the first flip-flopbecomes the clock input for the second flip-flop, and theoutput of the second flip-flop becomes the clock input for thethird flip-flop etc.

For the first flip-flop, the output changes whenever there is anegative transition in the clock input.

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Asynchronous Counters This means that the output of the first flip-flop produces a

series of square waves that is half the frequency of theclock input.

Since the output of the first flip-flop becomes the clock of

the second flip-flop, the output of the second flip-flop ishalf the frequency of its clock,

i.e. the output of the first flip-flop that in turn is half thefrequency of the clock input.

This behavior, in essence is captured by the binary bit

pattern in the counting sequence.

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Asynchronous counters

Modulus (MOD)the number of states it countsin a complete cycle before it goes back to the

initial state.

Thus, the number of flip-flops used depends onthe MOD of the counter (ie; MOD-4 use 2 FF (2-

bit), MOD-8 use 3 FF (3-bit), etc..)

Example: MOD-4 ripple/asynchronous up-counter.

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Asynchronous Counters (continue) The asynchronous counter that counts 4

number starts from 00011011 and

back to 00 is called MOD-4 ripple

(asynchronous) up-counter. Next state table

and state diagram

Present State Next State

Q1Q0 Q1Q0

00 01

01 10

10 11

11 00

00

01

10

11

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MOD-4 Asynchronous up-counter

J Q

K Q

CLK

1 J Q

K Q

CLK

1

Q0 (LSB) Q1 (MSB)

CLK

Q1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1

Binary 0 1 2 3 0 1 2 3

0

Asynchronous Counters (continue)

CLK

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The external clock is connected to the clock input of the firstflip-flop (FF0) only.

So, FF0 changes state at the falling edge of each clock pulse,but FF1 changes only when triggered by the falling edge of the

Q output of FF0. Because of the inherent propagation delay through a flip-flop,

the transition of the input clock pulse and a transition of the Qoutput of FF0 can never occur at exactly the same time.

Therefore, the flip-flops cannot be triggered simultaneously,producing an asynchronous operation.

The 2-bit ripple counter circuit above has four different states,each one corresponding to a count value.

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Asynchronous Counters (continue) A counter with n flip-flops can have 2 to the power n states.

The number of states in a counter is known as its mod(modulo) number.

Thus a 2-bit counter is a mod-4 counter.

A mod-n counter may also be described as a divide-by-ncounter.

This is because the most significant flip-flop (the furthestflip-flop from the original clock pulse) produces one pulse

for every n pulses at the clock input of the least significantflip-flop (the one triggers by the clock pulse).

Thus, the above counter is an example of a divide-by-4counter.

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MOD-8 Asynchronous up-counter

J Q

K Q

CLK

1 J Q

K Q

CLK

1 J Q

K Q

CLK

1

C B A

A 0

B 0

C 0

CLK


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Next state table and state diagram

Present

State

Next State

ABC ABC

000 001001 010

010 011

011 100100 101

101 110

110 111

111 000

0

1

2

3

7

6

5

4


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Four bit up counter

15

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Asynchronous 3 Bit Down Counter

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Asynchronous Decade counter

18

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Asynchronous Decade counter

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Mod-12 Asynchronous counter

20

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Circuit diagram for MOD-6 ripple up-counter (MOD

2N)

J Q

K

CLR

Q

CLK

1 1 1

C B A

J Q

K

CLR

Q

CLK

J Q

K

CLR

Q

CLK

Detect the output at

ABC=110 to activate

CLR. NAND gate is used

to detect outputs that generates 0!

CLK

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Disadvantages of Asynchronous Counters: Propagation delay is severe for larger MOD of counters,

especially at the MSB.

Existence of glitch is inevitable for MOD 2N counters.

Difficult to design random counters (i.e.: to design circuit

that counts numbers in these sequence

56723156723156.)

Solution, use SYNCHRONOUS COUNTERS.

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For synchronous counters, all the flip-flops are usingthe same clock signal.

Thus, the output would change synchronously.

Procedure to design synchronous counter as follows:STEP 1: Obtain the State Diagram.

STEP 2: Obtain the Excitation Table using state transitiontable for any particular FF (JK or D).

Determine # of FF used.

STEP 3: Obtain and simplify the function of each FF inputusing K-Map.

STEP 4: Draw the circuit.

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Design a MOD-4 synchronous up-counter, using

JK FF.

STEP 1: Obtain the State transition Diagram

0

1

2

3

00

01

10

11Binary

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STEP 2: Obtain the Excitation table, two JK FF are used.

Present State Next State Flip-Flop inputs

A B A B JA KA JB KB0 0 0 1 0 X 1 X

0 1 1 0 1 X X 1

1 0 1 1 X 0 1 X

1 1 0 0 X 1 X 1

OUTPUT TRANSITION

QN QN+1

FF INPUT

J K

0 0 0 X0 1 1 X1 0 X 11 1 X 0

Excitation table

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STEP 3: Obtain the simplified function using K-Map

BA 0 1

0 0 1

1 X X

JA = B

BA 0 1

0 X X

1 0 1

KA = B

B

A 0 10 1 X

1 1 XJB = 1

BA 0 1

0 X 1

1 X 1KB = 1

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STEP 4: Draw the circuit diagram

JB

Q

KBQ

CLK

1J

AQ

KAQ

CLK

B (LSB) A (MSB)

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28


Design a MOD-4 synchronous down-counter, using JKFF?

STEP 1: Obtain the State transition Diagram

0

3

2

1

00

11

10

01Binary

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Synchronous countersObtain the Excitation table. Two JK FF are used.

Present

St.

Next St.

A B A B JA KA JB KB0 0 1 1 1 x 1x

0 1 00 0x x1

1 0 01 x1 1x

OUTPUT TRANSITION

QN QN+1

FF INPUT

J K

0 0 0 X0 1 1 X

1 0 X 11 1 X 0

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Obtain the simplified function using K-Map

BA 0 1

0 1 0

1 x x

JA =A

BA 0 1

0 X X

1 1 0

KA =B

BA 0 1

0 1 X

1 1 XJB =1

BA 0 1

0 X 1

1 X 1KB =1

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Draw the circuit diagram

JB Q

KBQ

CLK

JA Q

KA Q

CLK

B

A

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3-Bit Synchronous Binary Counter

The J and K inputs of FF0 are connected to HIGH.

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3-Bit Synchronous Binary Counter FF1 has its J and K inputs connected to the output of FF0,

and the J and K inputs of FF2 are connected to the outputof an AND gate that is fed by the outputs of FF0 and FF1.

After 3rd clock pulse, both outputs of FF0 and FF1 are

HIGH. Positive edge of the 4th clock pulse will cause FF2 to

change its state due to the AND gate.

Advantage of sync. counters is that there is no cumulativetime delay because all flip-flops are triggered in parallel.

Maximum operating frequency for this counter will besignificantly higher than for the corresponding ripplecounter.

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SYNCHRONOUS COUNTERS

All flip-flops are clocked simultaneously Mod-16 Synchronous Up-Counter

ff

1fmax

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SYNCHRONOUS COUNTER DESIGN

Mod-6 Up-Counter Using D-flip-flopsDesign table

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MOD-6 UP-COUNTER K-maps

Final design

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Synchronous Up/Down Counters

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Counter Design Procedure

1. Describe a general sequential circuit in terms ofits basic parts and its input and outputs.

2. Develop a state diagram for a given sequence.

3. Develop a next-state table for a specific countersequence.

4. Create a FF transition table.

5. Use K-map to derive the logic equations.

6. Implement a counter to produce a specifiedsequence of states.

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clock

data in

may changestable

data out (Q) stable stablestable

Registers

Sample data using clock

Hold data between clock cycles

Computation (and delay) occurs between registers

clock

data in

D Q D Qdata out

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there is a timing "window"around the clocking eventduring which the input mustremain stable and unchangedin order to be recognized

clock

data

changingstable

input

clock

Tsu Th

Timing Methodologies (contd)

Definition of terms setup time: minimum time before the clocking event

by which the input must be stable (Tsu)

hold time: minimum time after the clocking event

until which the input must remain stable (Th)

clock

dataD Q D Q

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Example - Circuit with Feedback

Output is a function of arbitrarily many past inputs

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Example - Circuit without Feedback

Output is a function of the input sampled at three

different points in time.

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Shift Register

Shift registers are constructed using several flip-flop,connected in such a way to STORE and TRANSFER digital

data.

Basically, D flip-flop is used. The input data (either 0 or 1)

is applied to the D terminal and the data will be stored at Q

during positive/negative-edge transition of the clock pulse.

D Q

Q

1 1

Negative edge transition of CLK

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One D FF is used to store 1-bit of data.

Thus, the number of flip-flops used is the same with the

number of bit stored.

Shift register mean that the data in each FF can be transferred/move to other FF upon edge triggering of the clock signal.

Four types of data movement in shift register are:

Parallel in / parallel out (PIPO)

Serial in / parallel out (SIPO)

Serial in / serial out (SISO)

Parallel in / serial out (PISO)

Shift Register

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Shift Register

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Serial Data Vs.Parallel Data movement

Serial Parallel

Movement of N-bit data require

N number of CLK pulses. Thus,

the operation is slow.

Only one FF is required to beconnected at the output terminal,

thus only one wire is required.

Require only one CLK pulse to

transfer all N-bit of data. Thus,

operation is faster than serial.

Required N number ofconnection to the output

terminal, which is proportional to

the number of bit. Thus, too

many connection is required.

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Parallel in / parallel out (PIPO)

Flip-flop configuration for PIPO register.

D Q2

CP

D Q1

CP

D Q3

CP

D Q0

CP

CLK

D3 D2 D1 D0

Q3 Q2 Q1 Q0

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PIPO data movement.

Q3

Q2

CLK

Q1

Q0

1 0 1 1 1

00

0

0

1 0 10 0

0

0

1 1 1 1

0 0 1 0

D3

D2

D1

D0

1

0

1

0

0

1

1

0

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Parallel in / parallel out

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Serial in / parallel out (SIPO)

51

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Flip-flop connection for SISO.

D Q1

FF1

CP

D Q2

FF2

CP

D Q0

FF0

CP

D Q3

FF3

CPCLK

DIN

1st CLK 2nd CLK 3rd CLK 4th CLK

Serial in / Serial out (SISO)

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Flip-flop connection for PISO.

Parallel in / serial out (PISO)

D Q1

FF1

CP

D Q2

FF2

CP

D Q0

FF0

CP

D Q3

FF3

CPCLK

D0 D1 D2 D3SHIFT/LOAD

Serial

data

out

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PISO data movement.

SHIFT/LOAD

CLK

Q3

0

0 1 1 1

1 0 1

0

0

0

1

1 1 1 1

0 0 1 1

D0

D1

D2

D3

1 00 1 0 1

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Ashift register counter is a shift register whose

output being fed back (connected back) to the serial

input.

This shift register would count the state in a uniquesequence!

Two types of shift register counter:

The ring counter

The Johnson counter

Shift Register Counters

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Ring Counter

Q3 Q2 Q1 Q0

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Ring Counter (continue)

0 0 0 1

1 0 0 0

0 1 0 0

0 0 1 0

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Ring Counter (continue)

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Ring counters are used to

construct One-Hot counters

It can be constructed for any

desired MOD number

A MOD-N ring counter usesN flip-flops connected in the

arrangement as shown in fig. a)

In general ring-counter will

require more flip-flops than abinary counter for the same

MOD number

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J h C t

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Johnson Counter

Or Twisted-ring counter

Johnson counter constructed exactly like a normal ring counter

except that the inverted output of the last flip-flop is fed back to

first flip-flop

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Johnson Counter (Continue)

A

B

C

0 1 1 1

0 0 1 1

0 0 0 1


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Applications of shift registers

66

S i l Ci i

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Sequential Circuits

Design steps

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Topics Discussed

Characteristic equation for RS, D, JK & T FF. Design/excitation table for RS, D, JK & T FF.

3-bit synchronous counter design using T FF.

Design of synchronous counter with the count sequence

0,3,2,4,1,5,7, and repeat using RS FF/T FF. Design of synchronous counter that goes through the

sequence 2,6,1,7,5, and repeat using D FF.

A FF has 3 inputs S, R, & T. no more than one of theseinputs may be 1 at any time. S & R inputs behave as SR FF.

T input behave as T FF. Show a state graph for this FF

Write an equation for output Q+ in terms of S, R, T & Q

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THANK YOU

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