Cost-Based Tradeoff Analysis of Cost-Based Tradeoff Analysis of Standard Cell Designs Standard Cell Designs Peng Li Pranab K. Nag Wojciech Maly Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA 15213 {pli, pkn, maly}@ece.cmu.edu
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Cost-Based Tradeoff Analysis of Standard Cell Designs
Cost-Based Tradeoff Analysis of Standard Cell Designs. Peng Li Pranab K. Nag Wojciech Maly Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA 15213 {pli, pkn, maly}@ece.cmu.edu. Motivations. Necessity for Evaluation of Designs’ Cost Effectiveness - PowerPoint PPT Presentation
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Cost-Based Tradeoff Analysis of Cost-Based Tradeoff Analysis of Standard Cell DesignsStandard Cell Designs
Peng LiPranab K. NagWojciech Maly
Electrical and Computer EngineeringCarnegie Mellon University
Pittsburgh, PA 15213{pli, pkn, maly}@ece.cmu.edu
2 P. Li, SLIP’2000
MotivationsMotivations Necessity for Evaluation of Designs’ Cost Effectiveness
– Tendency of Manufacturing Cost Increase
– Selection of Technology Which Yields the Least Cost
Emergence of Fabless Design Houses
– Choice of Manufacturing Technologies
– Consideration of Manufacturing from Design Perspective
Importance of Early-Stage Predictions
– Reduction of Number of Design Iterations
– Facilitation of Early-Stage Decision
3 P. Li, SLIP’2000
ObjectiveObjective
Cost Prediction for Standard Cell Designs
– Quickly Predict Die Size & Interconnect Yield
As a Function of Number of Metal Layers
Based On a Given Placement
– Predict Die Cost Based on a Wafer Cost Model
– Forecast Optimal Selection of Number of Metal
Layers In Terms Of Die Cost
4 P. Li, SLIP’2000
Why Number of Metal Layers MattersWhy Number of Metal Layers Matters Affect Die Size and Yield An Important Cost Factor
– Six Standard Cell Designs Portions of Industrial DSP circuits
Design Name # of Cells # of Nets1 Sync2 3440 34672 Cdgc2 2751 34033 Fifo2 2390 24294 Ifagc2 382 5345 Prescale 2021 28266 Hnyq 2608 3806
– Comparison With Data Based On Layouts 2-4 metal layers Our method : die size, routing utilization and yield Cadence tools: layout generation, critical area
extraction(Dracula) and yield calculation
19 P. Li, SLIP’2000
Experimental ResultsExperimental Results Die Size Estimation