CORE 2 DUO

CONTENTS

1.INTRODUCTION2.FEATURES

3.MICHROARCHITECTURE 4.DUAL CORE

IMPORTANCE 5.REGISTER SET

6.INTRUCTION SET 7.ADDRESSING MODES

8.DIFFERENCES 9.ADVANTAGES.

INTRODUCTION(core 2 duo )

Today we bring you the information on Intel’s new mainstream processor – the CORE 2 DUO formerly known by the code name “CONROE”The core 2 brands was introduced on july 27 2006comprising the solo(single core ),duo (dual core),quad(quad core) process

The Intel core 2 duo iprocessor on 65nm technology is the next generation ,high performance , low power processor based on the Intel core microarchitecture.

The Pentium D is simply two Pentium 4 Prescott cpus inefficiently paired together and ran as dual core.The Pentium D, Core Duo, Core 2 Duo and Athlon X2 are all current CPUs that have dual cores in one package.

KEY FEATURES:-

Dual core processor for mobile with enhanced performance.

Advanced power management features including enhanced Intel SpeedStep technology.

Digital Thermal Sensors. Intel Dynamic acceleration

technologyEnhanced Multi Threaded thermal

management (EMTTM).

Additional FEATURES:-

Helps in reducing the operating costs and increasing productivity.

Based on the enhanced INTEL core Microarchitecture and the 65nm process technology.

Energy efficient performance.Build in security features help

combat the expense of security threats

Intel HD BOOT

Deep power down technology

Mobile optimised architecture

Smart memory access

Virtualisation technology

Dynamic acceleration

SMART CACHE-DECREASED TRAFFIC WHEN L1 AND

L2 CORE ARE SHARED. INCREASED TRAFFIC WHEN L1 AND L2 USED

INDEPENDENTLY.SMART MEMORY ACCESS-

LOST OPPURTUNITIES FOR OUT OF ORDER EXECUTION.

DIGITAL MEDIA BOOST-LOWER BITS IN 1 CYCLE AND UPPER

IN THE NEXT.

CONROE-*DESKTOP CPU

*NUMBER OF TRANSISTORS ON 2MB AND 4 MB MODELS

WOODCREST- *SERVER OPTIMIZED

*SAME FEATURES AS CONROE. MEROM-

*MOBILE CPU. *SAME FEATURES AS CONROE.

WHY IS IT CALLED DUAL CORE?

REGISTER SET The main tools to write programs in core 2

duo, under x86 assembly are the processor registers.

Using registers instead of memory to store values makes the process faster and cleaner. Here is a list of the available 32 bit registers on the core 2 duo and higher processors. Most of the can be broken down to 16 or even 8 bits register.

1. General registers EAX EBX ECX EDX 2. Segment registers CS DS ES FS GS SS 3. Index and pointers ESI EDI EBP EIP ESP4. Indicator EFLAGS

GENERAL REGISTERS are the one we use most of the time. Most of the instructions perform on these registers. They all can be broken down into 16 and 8 bit registers.

32 bits : EAX EBX ECX EDX 16 bits : AX BX CX DX 8 bits : AH AL BH BL CH CL DH DL The "H" and "L" suffix on the 8 bit registers stand for high byte and low byte.  EAX, AX, AH, AL : Called the Accumulator register. It is used for I/O port access, arithmetic, interrupt calls, etc... EBX, BX, BH, BL : Called the Base register It is used as a base pointer for memory access.ECX,CX,CH,CL : Called the Counter register It is used as a loop counter and for shiftsEDX, DX, DH, DL : Called the Data register It is used for I/O port access, arithmetic, some interrupt calls.

SEGMENT REGISTERS.Segment registers hold the segment address of various items. They are only available in 16 values. They can only be set by a general register or special instructions. Some of them are critical for the good execution of the program and you might want to consider playing with them when you'll be ready for multi-segment programming CS : Holds the Code segment in which your program runs. Changing its value might make the computer hang. DS : Holds the Data segment that your program accesses. Changing its value might give erronous data.

ES,FS,GS : These are extra segment registers available for far pointer addressing like video memory and such. SS : Holds the Stack segment your program uses. Sometimes has the same value as DS. Changing its value can give unpredictable results, mostly data related .

INDEX AND POINTERS and the offset part of and address. They have various uses but each register has a specific function. They some time used with a segment register to point to far address (in a 1Mb range). The register with an "E" prefix can only be used in protected mode.

ES:EDI EDI DI : Destination index register Used for string, memory array copying and setting and for far pointer addressing with ES DS:ESI EDI

SI : Source index register Used for string and memory array copying SS:EBP EBP

BP : Stack Base pointer register Holds the base address of the stack SS:ESP ESP SP :

STACK POINTER REGISTER - Holds the top address of the stack CS:EIP EIP IP : Index Pointer Holds the offset of the next instruction It can only be read .

The EFLAGS register The EFLAGS register hold the state of the processor. It is modified by many instructions and is used for comparing some parameters, conditional loops and conditionnal jumps. Each bit holds the state of specific parameter of the last instruction. Here is a listing : Bit Label Desciption0 CFCarry flag 2 PF Parity flag4 AF Auxiliary carry flag 6 ZF Zero flag 7 SF Sign flag 8 TF Trap flag 9 IF Interrupt enable flag 10 DF Direction flag 11 OF Overflow flag 12-13 IOPL I/O Priviledge level 14 NT Nested task flag 16 RF Resume flag 17 VM Virtual 8086 mode flag 18 ACAlignment check flag (486+) 19 VIF Virutal interrupt flag 20 VIP Virtual interrupt pending flag 21 ID ID flag

ISA is the part of an overall computer’s architecture relatedto programming, including the native data types, instructions,registers, addressing modes, memory architecture, interruptand exception handling, and external I/O. An ISA includesa specification of opcodes (machine commands) implementedby a particular microprocessor design. Within afamily of processors, ISA is often enhanced over timewith new instructions to deliver superior performanceand energy-efficiency while maintaining compatibility

INSTRUCTION SET

to already existing applications.

Instruction Meaning Notes

AAAASCII adjust AL afteraddition

used with unpacked binary coded decimal

AADASCII adjust AX beforedivision

buggy in the original instruction set, but "fixed" in the NEC V20, causing a number of incompatibilities

AAMASCII adjust AX aftermultiplication

AASASCII adjust AL aftersubtraction

ADC Add with carry

ADD Add

AND Logical AND

CALL Call procedure

NOTNegate the operand, logicalNOT

OR Logical OR

OUT Output to port

POP Pop data from stack(Only works with register CS on 8086/8088.)

POPFPop data into flags register

PUSHPush data onto stack

INC Increment by 1

INT Call to interrupt

INTOCall to interrupt if overflow

IRET Return from interrupt

Jxx Jump if condition

(JA, JAE, JB, JBE, JC, JCXZ, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ)

SPEED OF CORE 2 DUO PROCESSOR

Intel core 2 duo is a 3.0GHz dual core processor based on the wolfdale core that is being manufactured on the 45nm processor•This socket 775 processor packs in 6MB of L2 latch & operates with a 1333MHz Front side bus speed•Intel core 2 duo E8400 is physically similar 2 the core 2 duo E6750 & socket 775 pentium D processor that came before it. All of these processor use the land grid array 775-pad package. Intels move 2 a 45 nm manufacturing process means the silicon die here is approx 104mm2 in area & contains around 410 million transistors.•Duo to its 45nm die-shrink, the intel core @ duo E8400 processor can be clocked at higher speed yet maintains the same thermal design power(TDP) as the older E6000 series of processors• the typical TDP of core 2 duo E8400 is 65W.All E8000 series processor have 410 million transistor, 6MB of L2 cache,run at 1333MHz front side bus & have a TDP of 65W

ADDRESSING MODESTHE WAY THE OPERANDS ARE CHOSEN DURING PROGRAMME EXECUATION IS DEPENDENT ON THE ADDRESSING MODE OF INSTRUCTION.COMPUTERS USE ADDRESSING MODE1.TO GIVE PROGRAMMING VERSATILITY 2.TO REDUCE THE NUMBER OF BITS IN THE ADDRESSING FIELD OF THE INSTRUCTION TYPES-

Register/Register*� Immediate*� Direct� Indirect

Register Indirect� Based

Indexed Based Indexed

� String� I/O Port

Direct Addressing

MOV [700H],AX

ADDRESSING PART OF THE INSTRUCTION=ADDRESS OF ADDRESS OF THE OPERAND

Register Indirect Addressing

mov ah, [bx]  ;

ADDRESS PART OF THE INSTRUCTION=EFFECTIVE ADDRESS OF THE OPERAND

Indexed Indirect Addressing

INDEX REGISTER+ADDRESSING PART OF THE INSTRUCTION

MOV AX,[SI]

Based Indexed Indirect Addressing

EFFECTIVE ADDRESS=BASE REGISTER+INDEX REGISTER

MOV AX,[BX][SI]

DIFFERENCESDUAL CORE

1. The Core Duo is Intel's first generation

2. dual core processor is based upon the Pentium M

3. It is made mostly for laptops (though a few motherboard manufacturers have released desktop boards supporting the Core Duo CPU), and is much more efficiently than Pentium

CORE 2 DUO

1. The Core 2 Duo is Intel's second generation

2. This processor is made for desktops and laptops designed from the ground up to be fast while not consuming nearly as much power as previous CPUs.

1. WIDE EXECUTION2. COMPREHENSIVE ADVANCEMENTS3. ENABLE IN EACH CORE4. EACH CORE FETCHES, DISPATCHES, EXECUTES5. LESS ENERGY CONSUMPTION

ADVANTAGES

SUBMITTED BY:

MonaalMonikaMoupiyaNavdeepNeha