Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.

Copyright © 2005 Altera Corporation

Accelerating Design Cycles Using Quartus II


SignalTap II Embedded Logic AnalyzerSignalTap II Embedded Logic Analyzer

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SignalTap II AgendaSignalTap II Agenda SignalTap II Overview & Features Using SignalTap II Interface Advanced Triggering

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SignalTap II ELASignalTap II ELASignalTap II ELASignalTap II ELA Captures the Logic State of FPGA Internal

Signals Using a Defined Clock Signal Gives Designers Ability to Monitor Buried Signals Connects to Quartus II through FPGA JTAG Pins Captures Real-Time Data

Up to 200 Mhz Is Available for Free

Installed with Full Subscription or Web Edition Installed with Stand-Alone Programmer

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SignalTap II Device SupportSignalTap II Device Support

Stratix & Stratix II Stratix GX Cyclone & Cyclone II Excalibur Mercury APEX II APEX 20K/E/C

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How Does It Work?How Does It Work?How Does It Work?How Does It Work?

1. Configure ELA2. Download ELA into

FPGA along with Design

3. ELA Samples Internal Signals

4. Quartus II Communicates with ELA through JTAG

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ELA Resource UtilizationELA Resource Utilization ELA Uses Device Resources for Implementation

ALMs/LEs for ELA Megafunction & Routing Memory for Sample Storage

LE Count Is a Function of the Number of Channels & Trigger Levels

Memory Block Count Is a Function of Number of Channels & Sample Depth Selectable Trade-off Between Depth & Number of

Channels 128K Sample Depth with 1024 Channels Is Not

Practical – 32,768 M4K Blocks

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Stratix/Cyclone Sample Resource UsageStratix/Cyclone Sample Resource Usage

Number of Channels

Logic Elements

Trigger Level 1 Trigger Level 2 Trigger Level 3

8 316 371 426

32 566 773 981

256 2900 4528 6156

Number of Channels

M4Ks Based on Sample Depth

256 512 2K 8K 32K

8 < 1 1 4 16 64

32 2 4 16 64 256

256 16 32 128 512

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Modes of OperationModes of OperationModes of OperationModes of Operation

Three Different Configurations Internal RAM ELA Configuration Debug Port ELA Configuration Hybrid Approach

Provides Flexibility Based on Available Device Resources Memory Resources Are Limited

Use Debug Port Configuration Pin Resources Are Limited

Use Internal RAM Configuration

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Internal RAM ConfigurationInternal RAM ConfigurationInternal RAM ConfigurationInternal RAM Configuration Acquired Data Saved in Device Internal RAM Streamed Off-device through JTAG Port LEs Required to Implement ELA Core Logic

ELACore Logic

ELAMemory

Signals FromInternal Nodes

JTAG Port To JTAGConnector

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Debug Port ConfigurationDebug Port ConfigurationDebug Port ConfigurationDebug Port Configuration

Acquired Data Routed to Unused Device I/O Pins Captured by External Logic Analyzer or Oscilloscope

LEs Required to Implement ELA Core Logic I/O Pins Required for External Analysis

Signals FromInternal Nodes

To UnusedI/O Pins

Signals toDebug Ports

ELACore Logic

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Supported Download CablesSupported Download Cables

USB Blaster USB Port Cable

ByteBlaster™ II Parallel Port Cable

ByteBlasterMV™

Parallel Port MasterBlaster™

USB / Serial Port Cable

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SignalTap II Key FeaturesSignalTap II Key Features

Setup Data Triggering Data Capture Data Analysis

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Setup FeaturesSetup Features Up to 1024 Data Channels Multiple Analyzers in One Device

Supports Analysis of Multiple Clock Domains

Each Analyzer Can Run Simultaneously

Resource Usage Estimation Incrementally Routes New Signals

Setup

Data Triggering

Data Capture

Data Analysis

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Data Triggering FeaturesData Triggering Features Up to 10 Trigger Levels Per Channel

Allows Application of Simple (Basic) & Complex (Advanced) Triggering Schemes

Defines a Sequential Pattern of Logic Conditions

Each Trigger Level is Logically ANDED If (L1 & L2 ... & L10) == TRUE Data Capture

Setup

Data Triggering

Data Capture

Data Analysis

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Data Triggering Features (Cont.)Data Triggering Features (Cont.) Three Main Trigger Positions

Trigger Input Setup External Trigger to Trigger the Analyzer

Trigger Output Signifies Trigger Event Occurred with SignalTap II

Use One ELA’s Trigger Output as Trigger Input for Another

Data Triggering

Setup

Data Triggering

Data Capture

Data Analysis

TIME

Old Samples New Samples

trigger

Samples CapturedSamples Captured

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Data Capture FeaturesData Capture Features Up to 128K Samples Per Channel

Increases Chance of Catching Target Event

Two Methods of Data Acquisition

1. Circular 2. Segmented

Mnemonic Tables Create User-Defined Labels for Bit Sequences

(Ex. State Machine)

Setup

Data Triggering

Data Capture

Data Analysis

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Data Analysis FeaturesData Analysis Features Data Export

Save Real Time Data & Apply Data as Stimulus to Simulation

Data Log Keep a a Log of Captured Data Compare Old Data Vs. New Data

Setup

Data Triggering

Data Capture

Data Analysis

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SignalTap II Design FlowSignalTap II Design Flow

1) Use SignalTap II File (.STP) Use Quartus II GUI STP Separate from Design Files

2) Use Quartus II MegaWizard Instantiate Directly into HDL

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Using STP FileUsing STP File

1. Create .STP File• Assign Sample Clock• Specify Sample Depth• Assign Signals to STP File• Specify Triggering• Setup JTAG

2. Save .STP File & Compile with Design

3. Program Device

4. Acquire Data

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1) Creating a New .STP File1) Creating a New .STP File1) Creating a New .STP File1) Creating a New .STP File To Create a .STP File

Method 1 Select the in Quartus II

Method 2 Select New (File Menu) Other Files SignalTap II File

Default File Name Will Be STP1.stp

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Main .STP File ComponentsMain .STP File Components

Signal Configuration

JTAG Chain Configuration

Waveform Viewer

.STP FileInstance Manager

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Instance ManagerInstance Manager

Instance Manager Selects Current ELA to Setup/View Displays the Current Status of each Instance Displays Size (Resource Usage) of ELA

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Signal ConfigurationSignal Configuration

Manages Data Capture & Signal Configuration Sample Clock Sample Depth Trigger Position Trigger-In & Trigger-Out

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Assign Sample ClockAssign Sample Clock Use Global Clock for Best

Results Data Written to Memory on

Every Sample Clock Rising Edge

Clock Signal Cannot Be Monitored as Data

External Clock Pin Created Automatically if Clock Unassigned auto_stp_external_clock ELA Expects External Signal to

be Connected to Clock Pin

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Specify Sample DepthSpecify Sample Depth Sample Depth

Set Number of Samples Stored for each Data Signal

0 to 128K Sample Depth 0 Selected When External

Analyzer Is Used

Select RAM Type for Stratix & Stratix II Devices Useful when Preserving a

Specific Memory Type is Necessary

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Data CaptureData Capture Circular

Specify Trigger Position Pre Center Post Continuous

Segmented Specify Segment Depth

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Circular BufferCircular Buffer

1. Data is Circled through the Acquisition Buffer until the Trigger Event Occurs

2. After the Trigger Event Occurs, Post-Trigger Data is Collected until the Buffer Fills up

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Example: Circular BufferExample: Circular Buffer

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Segmented BufferSegmented Buffer

Acquisition Buffer is Segmented into a Smaller, User Defined Blocks Example: 4K is segmented into 4-1K segments

1. Data is Circled through the Acquisition Buffer until the Trigger Event Occurs

2. When the Trigger Event Occurs, Post-Trigger Data is Collected until the Segment Fills up

3. Process Repeats until all Segments are Filled

Segment 1 Segment 2 Segment 3Trigger Event

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Example: Segmented BufferExample: Segmented Buffer

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TriggeringTriggering Trigger Levels

Indicate up to 10 Trigger Conditions

Trigger-In Any I/O Pin Can Trigger the

SignalTap II Analyzer Generates auto_stp_trigger_in_n Pin

Trigger-Out Indicates When a Trigger Pattern

Occurs Generates auto_stp_trigger_out_n

Pin Delayed 4 Clock Cycles after Actual

Trigger Event

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Waveform ViewerWaveform Viewer

Setup Tab Describes the Signal Settings Data Signals vs. Trigger Signals Sets up Each Triggering Level (L1 – L10)

Data Tab Displays Captured Data

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STP File Waveform ViewerSTP File Waveform Viewer

Setup Tab

Data Tab

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Set up Waveform ViewerSet up Waveform Viewer Add Signals to Viewer Window

Use Node Finder Main Menu, Toolbar, or Right-Click Click Only Signals that Are Found Using the SignalTap II Filter in the Node

Finder Can Be Captured

Important: Not All Signals Are Available

Data Enable Column Check Box Controls Whether Signal Is Captured As Data Ex. Removing Reduces Sample Memory Size

Trigger Enable Column Check Box Controls Whether Signal Is Disregarded as a Trigger Pattern Ex. Signal Used Only for Data Collection

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Basic TriggeringBasic Triggering

Right-Click to Set Value

All Signals Must Be True for Level to Cause Data Capture

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Debug PortDebug Port Routes Data Signals to Spare I/O Pins for

Capture by External Logic Analyzer Quartus II Automatically Generates

auto_stp_debug_out_m_n Pin m Represents the Instance Number of the Analyzer n Represents the Order the Debug Port Pin Occurs

in the Signal List

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Mnemonic TableMnemonic Table Allows a Set of Bit Patterns

to Be Assigned User-Defined Names Right-Click in the Setup View

of an STP File & Select Mnemonic Setup

Select Add Table Select Add Entry

Ex. State Machines or Decoders/Encoders

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JTAG Chain ConfigurationJTAG Chain Configuration

Select Programming Hardware Scan Chan Button Automatically

Determines Devices Physically Connected to the Chain

Detects Non-Altera Devices & Displays Them as Unknown

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2) Save .STP File & Compile2) Save .STP File & Compile

SignalTap II Logic Analyzer Control in Compiler Settings Assignments Settings Specify the STP File to Compile with Project

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3) Program Device(s)3) Program Device(s) Use Quartus II Programmer or STP File

Program Button in the SignalTap II Interface Only Configures the Selected Device in Chain

Use Quartus II Programmer to Program Multiple Devices

Can Create a STP File for each Device in the JTAG Chain

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4) Acquire Data4) Acquire Data

SignalTap II Toolbar & STP File Controls

Run Autorun Stop Read Data (Reads in Data from Last Analysis)

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Displaying Acquired DataDisplaying Acquired Data

Display Signal as Bar or Line Chart Export to Other Tools for Viewing or Analysis

(File Menu) Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File

Format in Time or Sample Number

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Using STP File ReviewUsing STP File Review

1. Create .STP File• Assign Sample Clock• Specify Sample Depth• Assign Signals to STP File• Specify Triggering• Setup JTAG

2. Save .STP File & Compile with Design

3. Program Device

4. Acquire Data

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Using MegaWizardUsing MegaWizard

1. Create Instantiation Using MegaWizard• Number of Data Channels• Sample Depth• Number of Triggers Inputs• Number of Trigger Levels (Advanced/Basic)

2. Instantiate into Design

3. Synthesize Design

4. Create STP File Based on Instances & Edit

5. Acquire Data

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1) Create Instantiation1) Create InstantiationSize SignalTap II Instance

Basic or Advanced Triggering?

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2 & 3) Instantiate & Synthesize2 & 3) Instantiate & Synthesize

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4) Create STP File (File Menu) & Edit4) Create STP File (File Menu) & Edit

Generates New STP File Based on Number Design Instances

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RecompilationRecompilation Recompilation Required

Addition/Removal of Instance, Data or Trigger Modifying the Sample Clock or Buffer Depth Enabling/Modifying Trigger-In/Trigger-Out Enabling the Debug Port

Lock Mode Prevents Changes Requiring Recompilation

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Incremental RoutingIncremental Routing

Switches between Nodes without Full Recompilation

Maximizes Effectiveness

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SignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental Routing Switches between Nodes without Full Recompilation

1) Enable Smart Recompilation

2) Manually Set the Number of Allocated Nodes Nodes Acts as Place Holders for Real Signals that Can Be Added Later Auto Creates Enough Nodes for Current Number of Data/Triggers

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SignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental Routing

Step 3: Add Post-Fitting nodes to STP file SignalTap II: Post-Fitting Nodes Always Incrementally Routed SignalTap II: Pre-Synthesis Nodes Always Cause a Full

Recompilation if Added Later Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes is

that They Can Be Removed & Replaced with Post-fitting Nodes without a Total Recompilation

Pre-Synthesis Nodes

Post-fitting Nodes

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Quartus II Netlist OptimizationQuartus II Netlist Optimization New Synthesis Optimization Features Do Not

Work Well with SignalTap II SignalTap II Nodes may Disappear Register Re-timing & WYSIWYG Re-Synthesis Should

be Disabled if SignalTap II is Used

Set the Netlist Optimizations Logic Option to Never Allow on Entities Which Have SignalTap II Nodes

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SignalTap II & LogicLockSignalTap II & LogicLock

SignalTap II can Potentially Effect the Performance of a Design Routing and/or Placement Can Change

Possible Solution: LogicLock Use LogicLock to Place Design Blocks within

Specific Regions Place the SignalTap II Block in its Own

LogicLock Region

See Appendix for Example of Using LogicLock with SignalTap II

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Exercise

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Advanced TriggeringAdvanced Triggering

Create Advanced Boolean Functions Using Pre-Synthesis Nodes

Trigger Result

SignalTap II Nodes

Boolean Function Composed of Multiple Objects

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Enabling Advanced TriggeringEnabling Advanced Triggering

1. Change the Trigger Level Type from Basic to Advanced Triggering

2. A New Advanced Trigger Tab & Window Will Appear

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Advanced Trigger WindowAdvanced Trigger Window

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Advanced Trigger WindowAdvanced Trigger Window

Node List Lists Available Nodes for Advanced Triggering

Pre-Synthesis Nodes Only

Object Library Lists Functions Necessary to Build Equations

Advanced Trigger Condition Editor Graphic Tool to Build Equation

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Object LibraryObject Library

Object Type SettingsEdge & Level Detector Pos/Neg Edge, Levels

Input Objects Bit & Bus Values

Comparison Operators <, <=, =, !=, >, >=

Bitwise Operators Bitwise AND, OR, XOR, Complement

Logical Operators Logical NOT, AND , OR, XOR

Reduction Operators Reduction AND, OR, XOR

Shift Operators Left/Right Shift

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Advance Trigger Condition EditorAdvance Trigger Condition Editor

1. Click & Drag from Node List/Object Library into Editor

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Advance Trigger Condition EditorAdvance Trigger Condition Editor2. Connect Nodes & Objects

Use Automatic Connection by Positioning Click & Drag Output Ports to Draw Wires

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Advance Trigger Condition EditorAdvance Trigger Condition Editor

3. Connect to Result Block

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Object PropertiesObject Properties General Tab

Change the Object Type Add Your Own Object

Name

Parameter Tab Set Bus or Bit Value Switch Between

Operators of the Same Object Type

Insert Pipelining

Double-Click on an Object to Open Object Properties

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Post-Fitting NodesPost-Fitting Nodes Results of Basic Triggering Conditions Can Be

Used For Advanced Triggering

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Example (1)Example (1) Trigger on the Following Condition

If (Control =1) OR (d = F0h) AND (result = 10Fh)

Pre-synthesis Nodes: Control d[7:0]

Post-synthesis Node: result[11:0]

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Example (2)Example (2)

Edit Basic Trigger Conditions - result

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Change to Advance Trigger Condition

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Add Rest of Pre-Synthesis Nodes

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Compiling with SignalTap IICompiling with SignalTap II Any Object Parameter with a White Background

is Runtime Configurable Change Does Not Require a Full Compilation

Any Other Changes Require a Full Compilation

The User Entered Bus Value Constant is

Runtime Configurable

The Comparator Setting is also Run Time

Configurable

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Data DelayData Delay Delays a SignalTap II

Node by a User Specified Number of Sampling Clock Cycles

Object Properties Dialog Box

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Data Delay ExampleData Delay Example

Trigger Out Latency: 6 Clock Cycles

Clock

Instruction Register 0x02 0x030x01

Trigger Condition 1

If (Opcode = 0x01) followed by (Opcode = 0x02) followed by (Opcode = 0x03)

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Allows User to Debug Logic Design Problems during Circuit Operation at System Speed

Provides Easy Setup & Visibility of Internal Nodes without External Analyzer

SignalTap II ELA SummarySignalTap II ELA Summary




SignalProbe Incremental RoutingSignalProbe Incremental Routing

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SignalProbe Incremental RoutingSignalProbe Incremental Routing

Fast Incremental Routing of Debugging Signals (Test Points) to Spare/Reserved I/O Pins Uses Any Available Routing without Full Recompilation

JTAG

Logic

Available Routing

Unused I/O

Debugging Cell

Used Routing

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SignalProbe AdvantagesSignalProbe Advantages

Simple to Use Quartus II Handles Signal Routing

User Only Specifies Source Node & Destination Pin Quartus II Reports Delay Times from Node to Pin

User Can Test Output of Any Hard Node Placement of Compiled Design Remains

Unaffected fMAX of Signal Being Debugged Unchanged

SignalProbe Uses Incremental Routing Compilation Time Typically <10% of Full Compilation

Time

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SignalProbe Supported DevicesSignalProbe Supported Devices

Stratix II Stratix Stratix GX Cyclone MAX II Excalibur APEX II APEX 20K/E/C

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1. Enable Smart Compilation Assignments Settings Compiler Process

2. Reserve SignalProbe Output Pins

3. Compile Design (Optional)

4. Assign SignalProbe Source (Debugging Nodes)

5. Add Pipeline Registers & Clock, if Needed

Using SignalProbeUsing SignalProbe

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6. Perform SignalProbe Compilation Processing Start Start SignalProbe Compilation

7. Program Device

8. Repeat Steps 4-7 to Change SignalProbe Sources

Using SignalProbe (cont.)Using SignalProbe (cont.)

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Assign SignalProbe Dialog BoxAssign SignalProbe Dialog Box

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Reserve SignalProbe PinsReserve SignalProbe Pins

Type Reserved Pin Name

Enable SignalProbe

Select Pin Number

Click Add

Assign I/O Standard

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Assign SignalProbe SourcesAssign SignalProbe Sources

Use SignalProbe Filter in Node Finder to Locate Sources

Assign Clock & Number of Registers for Pipelining

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SignalProbe SourcesSignalProbe Sources

All Sources Must Be Nodes that Exist after Fitting Use SignalProbe Filter in Node Finder

Valid Examples LE Outputs Memory Block Outputs DSP Block Outputs

Invalid Examples Groups or Busses Carry or Cascade Chains

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Change Source of Pins Add/Delete Source of Pins Enable/Disable SignalProbe Pins

All Require SignalProbe Compilation Only Do Not Need to Perform Full Compilation

Editing SignalProbe AssignmentsEditing SignalProbe Assignments

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SignalProbe OptionsSignalProbe OptionsSignalProbe OptionsSignalProbe Options

Route SignalProbe Signals during Full Compilation Warning : Test Nodes May Be Synthesized

Away Allow Place & Route to Be Modified (If

Necessary)

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Allows Internal Signals to Be Routed to Unused I/O Quickly & Easily

Ensures Design Placement & Routing Are Unchanged When Adding Test Points

SignalProbe SummarySignalProbe Summary

Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.

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