Copyright © 2004 by Miguel A. Marin Revised 2005-1-171 CMOS CIRCUIT TECHNOLOGY NMOS & PMOS TRANSISTOR SWITCH NMOS & PMOS AS LOGIC CIRCUITS NMOS & PMOS.

Copyright © 2004 by Miguel A. Marin Revised 2005-1-17

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CMOS CIRCUIT TECHNOLOGY NMOS & PMOS TRANSISTOR SWITCH NMOS & PMOS AS LOGIC CIRCUITS NMOS & PMOS LOGIC GATES CMOS LOGIC GATES POSITIVE & NEGATIVE LOGIC PHYSICAL CHARACTERISTICS PASS-TRANSISTORS PASSING 1’S AND 0’S TRANSMISSION GATES


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NMOS & PMOS TRANSISTOR SWITCH

NMOS TRANSISTOR SWITCH

PMOS TRANSISTOR SWITCH

V G

V SV D

SOURCE DRAIN

GATE

LOW X = 0

HIGH X=1

V G

V SV D

SOURCE DRAIN

GATE

HIGH X = 1

LOW X=0


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NMOS & PMOS AS LOGIC CIRCUITS

NMOS AS LOGIC CIRCUITS:VDD IS THE HIGH VOLTAGE FROM THE POWER SUPPLY0 VOLTS IS THE LOW VOLTAGE,GROUND POLARITY

IN NMOS, WHEN TURNED ON, VD IS PULLED DOWN TO GROUND

V D

V G

V D = 0CLOSEDSWITCHWHEN

VG = VDD

V D V D

V D = 0OPEN

SWITCHWHENVG = 0

V D = 0


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NMOS & PMOS AS LOGIC CIRCUITS

PMOS AS LOGIC CIRCUITS:VDD IS THE HIGH VOLTAGE FROM THE POWER SUPPLY0 VOLTS IS THE LOW VOLTAGE,GROUND POLARITY

IN PMOS, WHEN TURNED ON, VD IS PULLED UP TO VDD

V S

V G

V D = 0OPEN

SWITCHWHEN

VG = VDD

V DD V DD

V D = V DDCLOSEDSWITCHWHENVG = 0

V D


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NMOS & PMOS LOGIC GATES

NMOS LOGIC GATES: THE NOT GATETHERE IS POWER DISSIPATION IN STEADY STATE

V X

V f

V DDH

GROUNDL

V X V f

LOGIC SYMBOL

V DD

V X

V fV X V f

HL

LH


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NMOS LOGIC GATES: THE NAND GATETHERE IS POWER DISSIPATION IN STEADY STATE

IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NAND GATE

V X

V Y

V f

V DD

LOGIC SYMBOL

V X V Y V f

L LL HH LH H

HHHL


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NMOS & PMOS LOGIC GATES NMOS LOGIC GATES: THE NOR GATE

THERE IS POWER DISSIPATION IN STEADY STATE

IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NOR GATE

V X V Y V f

L LL HH LH H

HLLL


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NMOS LOGIC GATES: THE AND GATETHERE IS POWER DISSIPATION IN STEADY STATE

IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE AND GATE

V X V

Y

V f

L LL HH LH H

LLLH

LOGIC SYMBOL


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NMOS LOGIC GATES: SUMMARYTHERE IS POWER DISSIPATION IN STEADY STATE


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PMOS LOGIC GATES: THE NOT GATETHERE IS POWER DISSIPATION IN STEADY STATE

V X V f

HL

LH


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PMOS LOGIC GATES: THE NAND GATETHERE IS POWER DISSIPATION IN STEADY STATE

IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NAND GATE

V X V Y V f

L LL HH LH H

HHHL


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NMOS & PMOS LOGIC GATES PMOS LOGIC GATES: THE NOR GATE

THERE IS POWER DISSIPATION IN STEADY STATE

IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NOR GATE

V X V Y V f

L LL HH LH H

HLLL


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PMOS LOGIC GATES: THE AND GATETHERE IS POWER DISSIPATION IN STEADY STATE

IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE AND GATE

V X V

Y

V f

L LL HH LH H

LLLHLOGIC SYMBOL


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PMOS LOGIC GATES: SUMMARYTHERE IS POWER DISSIPATION IN STEADY STATE


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CMOS LOGIC GATES

TO EVOID STEADY STATE POWER DISSIPATION THE PULL-UP DEVICE, USED IN NMOS LOGIC GATES, IS REPLACED BY A PULL-UP

NETWORK BUILT WITH PMOS TRANSISTORS. THE PULL-DOWN DEVICE, USED IN PMOS LOGIC GATES, IS REPLACED BY A PULL-

DOWN NETWORK BUILT WITH NMOS TRANSISTORS.

PULL-UP NETWORK(PUN)

PULL-DOWN NETWORK(PDN)

V DD

V f

V X

V Z


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CMOS LOGIC GATES

CMOS CIRCUIT : NOT GATE

VX T1 T2 V f

L ON OFF

H

H OFF ON

L

V X V f

V DD

T 1

T 2


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CMOS LOGIC GATES

CMOS CUIRCUITVX VY T1 T2 T3 T4 V f

L LL HH LH H

ON ON OFF OFFON OFF OFF ONOFF ON ON OFFOFF OFF ON ON

HHHL


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CMOS LOGIC GATES PROCEDURE TO CONSTRUCT CMOS COMPLEX LOGIC

GATES F. THE PULL-UP NETWORK IS CONSTRUCTED WITH F USING

ONLY PMOS TRANSISTORS. THE POLARITIES OF THE VARIABLES ARE COMPLEMENTED

THE PULL-DOWN NETWORK IS CONSTRUCTED WITH !F USING ONLY NMOS TRANSISTORS.

PUN AND PDN ARE MUTUALLY EXCLUSIVE. THEY CANNOT BE CONDUCTING AT THE SAME TIME. THE OUTPUT Vf CANNOT BE HIGH AND LOW SIMULTANEOUSLY. IF BOTH NETWORKS ARE NOT CONDUCTING, THEN THE OUTPUT IS SAID TO BE FLOWTING OR PESENTING HIGH IMPIDANCE.

THE POLARITY OF THE INPUT VARIABLES IS THE SAME FOR BOTH NETWORKS.


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CMOS LOGIC GATES

GENERAL STRUCTURE OF A CMOS COMPLEX LOGIC GATE CIRCUIT F.

PULL-UP NETWORK :SYNTHESIZE F

COMPLEMENTING THEPOLARITY OF THE

VARIABLES. THESE AREINPUTS TO PMOS

TRANSISTORS

PULL-DOWN NETWORK :SYNTHESIZE !F WITH THE

POLARITY OF THEVARIABLES UNCHANGED.

THESE ARE INPUTS TONMOS TRANSISTORS

OUTPUT F

INPUT VARIABLES

V DD


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CMOS LOGIC GATES

EXAMPLE OF A CMOS COMPLEX LOGIC GATE CIRCUIT F.

DESIGN A CMOS CIRCUIT PRODUCING THE FUNCTION F(A,B,C,D) = !A + (!B +!C) !D.

!F(A,B,C,D) = A(BC + D)

PULL-UP NETWORK

PULL-DOWN NETWORK


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POSITIVE & NEGATIVE LOGIC

THE BEHAVIOR OF A SWITCHING DEVICE, LIKE A CMOS GATE, IS GIVEN IN TERMS OF HIGH AND LOW VOLTAGES. FOR A GIVEN DEVICE, THIS BEHAVIOR IS UNIQUE.

HOWEVER, ITS LOGIC BEHAVIOR CAN BE DEFINED EITHER WITH

POSITIVE LOGIC CONVENCTION: HIGH FOR 1 ; LOW FOR 0

OR WITH NEGATIVE LOGIC CONVENCTION: HIGH FOR 0; LOW FOR 1.

IN GENERAL THE LOGIC BEHAVIOR OF A SWITCHING DEVICE MAY BE DIFFERENT IN POSITIVE AND NEGATIVE LOGICS. FOR EXAMPLE, THE CMOS DEVICE ON NEXT SLIDE REPRESENTS THE NAND GATE IN POSITIVE LOGIC AND THE NOR GATE IN NEGATIVE LOGIC


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POSITIVE & NEGATIVE LOGIC

EXAMPLE OF POSITIVE AND NEGATIVE LOGICS

a11

a22

b15


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PHYSICAL CHARACTERISTICS

TRANSISTOR AS A SWITCH STATIC CURRENT NOISE MARGIN DYNAMIC OPERATION PROPAGATION DELAY POWER DISSIPATION FAN-IN/FAN-OUT


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TRANSISTOR AS A SWITCH: STATIC CURRENT; THE NOT GATE

WHEN THE TRASISTOR IS CUT-OFF, IT CAN CONDUCT A VERY LOW CURRENT, CALLED LEAKAGE CURRENT

RRR

DDf DS

DSVV

mAK

V

R

VI

DS

fSAT 2.0

1

2.0

V DD

V X

V f

PULL-UP DEVICE V f = V OL

R

R DS

I SAT

V X = HIGH VOLTAGE


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VOLTAGE TRANSFER CHARACTERISTIC VT is the threshold voltage ~ 0.2 VDD

VOH is the output high voltage = VDD

VOL is the output low voltage = 0.2 volts The plot of Vf versus Vx shows the voltage transfer characteristic


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NOISE MARGIN TWO MARGINS: NML , NMH

BY DEFINITION: NML = VIL - VOL ; NMH = VOH – VIL

EXAMPLE: FOR CMOS SWITCHING CIRCUITS LET VOH = VDD AND VOL= 0 v. Finding the two points where SLOPE = -1 VIL~ 1/8 (3 VDD + 2 VT), VIH~ 1/8 (5 VDD - 2 VT) IF VT = 0.2 VDD THEN NML = NMH = 0.425 VDD

For VDD = 5 v. NML = NMH = 2.1 v. For VDD = 3.3 v. NML = NMH = 1.4 v.


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PHYSICAL CHARACTERISTICS DYNAMIC OPERATION

LET US CONSIDER TWO INVERTERS CONNECTED IN CASCADE

CAPACITIVE LOAD AT NODE A IS DUE TO SILICON CONSTRUCTION OF TRANSISTOR. IT IS CALLED PARASITIC OR STRAY CAPACITANCE

V F

V DD

T 1

T 2

V X

V DD

T 1

T 2

A


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DYNAMIC OPERATION (Continues) Each transistor contributes a GATE CAPACITANCE

Cg = W . L . Cox

where Cox is called OXIDE CAPACITANCE and depends on technology and is given in f F/µm2 units

Other capacitance is due to wiring. ALL THESE CAPACITANCE ARE REPRESENTED BY C.

C AFFECTS THE SPEED OF OPERATION OF THE CIRCUIT


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PHYSICAL CHARACTERISTICS PROPAGATION DELAY is defined as the time required to

discharge C through the NMOS transistor voltage VDD/2 and it is given by the formula

or

where kn’ is the process transconductance parameter, W the width and L the length of the substrate.For PMOS, the propagation delay is computed by choosing the corresponding kn’ .

D

DD

Dp I

VC

I

VCt

2 DDVL

Wnk

Cpt

7.1


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POWER DISSIPATION Is the amount of power used by a transistor. It must

be small Consider the inverter:

For Vx = 0, no current flows, and therefore, no power is consumed.

For Vx = 5 v., the current flowing is ISAT, the power dissipated is

PS = ISAT VDD. If ISAT = 0.2 mA, then PS = 0.2 x 5 = 1.0 mW

10 000 inverters will dissipate 10 watts


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POWER DISSIPATION (Continues) Steady state power dissipation: is the power

dissipated in steady state current flow. Dynamic power dissipation: is the power dissipated

due to the switching action. NMOS circuits present STATIC and DYNAMIC power

dissipation PMOS circuits present STATIC and DYNAMIC power

dissipation CMOS circuits present ONLY DYNAMIC power

dissipation


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PHYSICAL CHARACTERISTICS POWER DISSIPATION (Continues)

CMOS CIRCUITS POWER DISSIPATION: THE ENERGY STORED IN THE CAPACITOR IS

E =(C VDD2)/2

FOR CHARGING AND DISCHARGING THE CAPACITOR, THE TOTAL ENERGY IS 2 E = C VDD

2.

POWER = ENERGY PER UNIT TIME IF THE CYCLE TIME (CHARGE – DISCHARGE PER SECOND)

IS EQUAL TO f, THEN THE DYNAMIC POWER CONSUMED IS PD = f C VDD

2


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PHYSICAL CHARACTERISTICS FAN-IN/FAN-OUT

FAN-IN of a circuit is the number of its inputs.

It is given by the formula:

where k is the number of inputs and C is the equivalent capacitance at the output of the gate

FAN-OUT of a circuit is the maximum number of circuits, n, that can be connected to its output. Then, the capacitor in the above equation is Cn = n x C. The propagation delay is computed by the same formula.

NAND’S with small FAN-IN are constructed with NMOS transistors

NOR’S with large FAN-IN are constructed with NMOS transistors: k transistors in parallel ~ k x W; C, however, increases the load.

kDDVL

Wnk

Cpt

7.1


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PASS-TRANSISTORS PASSING 1’S AND 0’

Let us consider the following two configurations

VA = VDD – VT VB is not quite equal to 0 v

NOT FULLY PASSING VDD NOT FULLY PASSING 0 v.

THIS IS DUE TO WHAT IS CALLED BODY EFFECT. BOTH SUBSTRATESARE BIASED TO VDD WHICH INCREASES THE THRESHOLD VOLTAGE,

VT,

BY A FACTOR OF 1.5 V..

B

V DD

V DD

A


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TRANSMISSION GATES A TRANSMISSION GATE (T-GATE) IS A CMOS CIRCUIT THAT PASSES,

EQUALLY WELL, THE HIGH AND THE LOW VOLTAGES. BOTH PATHS ARE EITHER SIMULTANEOUSLY CONNECTING OR

SIMULTANEOUSLY DISCONECTING X TO F. A T-GATE DRIVES ITS OUTPUT EITHER TO LOW OR TO HIGH EQUALLY WELL. EXAMPLE:

!S

S

X F

S F

01

HIGH IMPEDANCE: ZX


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TRANSMISSION GATES ANOTHER EXAMPLE: EX-OR GATE F = A B

THE SHANNON EXPANSION GIVES F = A [!B] + !A [B]

Copyright © 2004 by Miguel A. Marin Revised 2005-1-171 CMOS CIRCUIT TECHNOLOGY NMOS & PMOS TRANSISTOR SWITCH NMOS & PMOS AS LOGIC CIRCUITS NMOS & PMOS.

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