Copyright © 2003 Texas Instruments. All rights reserved. DSP C5000 Architecture Overview.

Copyright © 2003 Texas Instruments. All rights reserved.

DSP C5000DSP C5000

Architecture OverviewArchitecture Overview


ESIEE, Slide 2

C5000C5000

What Makes a DSP a Special Processor?What Makes a DSP a Special Processor?


ESIEE, Slide 3

Common Architectural Features of DSPsCommon Architectural Features of DSPs

MAC- multiply/ accumulate Unit MAC- multiply/ accumulate Unit

Executes one or more MAC in one clock Executes one or more MAC in one clock cyclecycleInternal registers for storing operands and Internal registers for storing operands and resultsresultsMultiple internal data memoriesMultiple internal data memoriesAuxilary adressing registers (8 or more) Auxilary adressing registers (8 or more) with with a dedicated ALUa dedicated ALUMultiple buses and dual access to data Multiple buses and dual access to data memorymemorySeparate access to program and data Separate access to program and data memoriesmemories(Harvard architecture)(Harvard architecture)DMA (Direct Memory Access)DMA (Direct Memory Access)

Data crunching:Data crunching:


ESIEE, Slide 4

Common Architectural Features of DSPsCommon Architectural Features of DSPs

Real-time and Multi-tasking:Real-time and Multi-tasking:Hardware and software interrupt handlingHardware and software interrupt handling

Zero overhead loopsZero overhead loops

Pipelined instructionsPipelined instructions

Parallel unitsParallel units

Specialised peripherals Specialised peripherals

Complex Algorithms:Complex Algorithms:Specialised instructions (Viterbi, LMS…)Specialised instructions (Viterbi, LMS…)

Bit reverse adressing (FFT)Bit reverse adressing (FFT)

Circular buffers (FIR filters)Circular buffers (FIR filters)


ESIEE, Slide 5

General DSP System Block DiagramGeneral DSP System Block Diagram


ESIEE, Slide 6

DSP Requires Multiply and AccumulateDSP Requires Multiply and Accumulate


ESIEE, Slide 7

Multiply and Accumulate UnitMultiply and Accumulate Unit


ESIEE, Slide 8

Multiple BusesMultiple Buses


ESIEE, Slide 9

Internal Memory for Fast AccessInternal Memory for Fast Access


ESIEE, Slide 10

Instruction Pipeline for Fast ExecutionInstruction Pipeline for Fast Execution

Instruction is broken into smaller Instruction is broken into smaller taskstasks that can be executed in parallelthat can be executed in parallel


ESIEE, Slide 11

Sequential Processing of InstructionsSequential Processing of Instructions


ESIEE, Slide 12

Less Cycles per InstructionLess Cycles per InstructionLess Power ConsumptionLess Power Consumption


ESIEE, Slide 13

Texas InstrumentsTexas InstrumentsC5000 SolutionsC5000 Solutions


ESIEE, Slide 14

TMS320C55X DSP Block DiagramTMS320C55X DSP Block Diagram

3 Data Read3 Data Read BusesBuses

1 Program 1 Program BusBus

2 Data Write2 Data WriteBusBus


ESIEE, Slide 15

TMS320C55x Key FeaturesTMS320C55x Key Features

32 x 16-bit Instruction buffer queue (IBQ)32 x 16-bit Instruction buffer queue (IBQ) Two 17-bit x17-bit MAC unitsTwo 17-bit x17-bit MAC units One 40-bit ALUOne 40-bit ALU One 40-bit Barrel ShifterOne 40-bit Barrel Shifter One 16-bit ALUOne 16-bit ALU Four 40-bit accumulatorsFour 40-bit accumulators Twelve independent buses:Twelve independent buses:

– – Three data read busesThree data read buses– – Two data write busesTwo data write buses– – Five data address busesFive data address buses– – One program read busOne program read bus– – One program address busOne program address bus


ESIEE, Slide 16

More C55x FeaturesMore C55x Features User-configurable IDLE DomainsUser-configurable IDLE Domains Variable length instructions and Variable length instructions and

efficient block repeat operationsefficient block repeat operations Dual MAC operations in a single Dual MAC operations in a single

cyclecycle Performs high precision arithmetic Performs high precision arithmetic

and logical operationsand logical operations Shift a 40-bit result up to 31 bits to Shift a 40-bit result up to 31 bits to

the left,or 32 bits to the rightthe left,or 32 bits to the right Performs arithmetic in a simpler ALU Performs arithmetic in a simpler ALU

of 16 bits.of 16 bits. Hold results of computations and Hold results of computations and

reduce the required memory traffic reduce the required memory traffic (4 Accumulators)(4 Accumulators)


ESIEE, Slide 17

Comparison Between C54x and C55xComparison Between C54x and C55x C54xC54x C55xC55x

MACsMACs 11 22

AccumulatorsAccumulators 22 44

Read busesRead buses 22 33

Write busesWrite buses 11 22

Program fetchProgram fetch 11 11

Address busesAddress buses 44 66

Program word size Program word size 16 bits16 bits 8/16/24/32/40/48 bits8/16/24/32/40/48 bits

Data word size Data word size 16 bits16 bits 16 bits16 bits

Auxiliary Register ALUsAuxiliary Register ALUs 2 (16-bit each) 2 (16-bit each) 3 (24-bit each)3 (24-bit each)

ALU ALU 1 (40-bit)1 (40-bit) 1 (40-bit)/1 (16-bit)1 (40-bit)/1 (16-bit)

Auxiliary RegistersAuxiliary Registers 88 88

Data RegistersData Registers 00 44

MemoryMemory separate data/progseparate data/prog Unified spaceUnified space


ESIEE, Slide 18

Performances Features Comparison Between Performances Features Comparison Between C54x and C55xC54x and C55x

30 to 160 Million Instructions per Second (MIPS) and MACs30 to 160 Million Instructions per Second (MIPS) and MACs for the C54x compared to 140 to 800 MIPS for the C55xfor the C54x compared to 140 to 800 MIPS for the C55x (5 times better)(5 times better)

Core Power consumption improves by 6 from 0.32 mW/ MIPS Core Power consumption improves by 6 from 0.32 mW/ MIPS for the C54x to 0.05 for the C55x.for the C54x to 0.05 for the C55x.

Variable instruction length (8 to 48 bits) for the C55x and 16 Variable instruction length (8 to 48 bits) for the C55x and 16 bits for the C54x gives a better code density.bits for the C54x gives a better code density.

C55x has twice as many Macs (2 and 1), Accumulators (4 and C55x has twice as many Macs (2 and 1), Accumulators (4 and 2), program fetch words (32 and 16 bits)2), program fetch words (32 and 16 bits)


ESIEE, Slide 19

C55x ArchitectureC55x Architecture

Data Read Buses (D, B, C) Data Read Buses (D, B, C)

Program A/D BusProgram A/D Bus

Data Write Buses (E, F)Data Write Buses (E, F)

PCPC MACMAC MACMAC

AC0AC0

AC1AC1

InstrInstr

BufferBuffer

QueueQueue

DecodeDecode

I U AU DU

ARnARn CDPCDPAA d d d d r r

GenGen

MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1

PU


ESIEE, Slide 20

C55x Program and Instruction UnitsC55x Program and Instruction UnitsPCPC

RETARETA

PUPU

Status RegistersStatus RegistersProgram FlowProgram Flow

PPUPPUInterruptsInterrupts

4-byte packet fetched4-byte packet fetched every cycle every cycle

Variable-length instruction setVariable-length instruction set (8, 16, 24, 32, 40, 48-bit) (8, 16, 24, 32, 40, 48-bit)

InstructionInstructionBufferBuffer64 x 864 x 8

DecoderDecoder

PUPU AUAU DUDU

4848

IUIUProg Addr GenProg Addr Gen

FF_FFFFFF_FFFF

00_000000_0000

ExternalExternal

InternalInternal PDB[32]PDB[32]

PAB[24]PAB[24]

Now, the A-unit...Now, the A-unit...


ESIEE, Slide 21

C55x Addressing Unit (AU)C55x Addressing Unit (AU)ARAUARAU

CDPCDP

DPDP

AR0-7AR0-7

AUAU

ALU/ShftALU/Shft

T0T0T1T1T2T2T3T3

16-bit16-bit

StackStackPointersPointers

23/16-bit23/16-bit

CircularCircularBuffersBuffers

23/16-bit23/16-bit

Where else could the data go?...Where else could the data go?...

AAddddrr

GGeenn

BAB[24]BAB[24]

CAB[24]CAB[24]

DAB[24]DAB[24]

CB[16]CB[16]

DB[16]DB[16]

A-Unit handles all A-Unit handles all datadata addressing addressing

FF_FFFFFF_FFFF

00_000000_0000

XX

XX

XX

First 64KW Pg 0First 64KW Pg 0

Last 64KW Pg 127Last 64KW Pg 127

Xreg: 23 bits, reg: 16 bitsXreg: 23 bits, reg: 16 bits


ESIEE, Slide 22

C55x Data Computation Unit (DU)C55x Data Computation Unit (DU)

DUDU

D-Unit executes mostD-Unit executes mostmathematical operationsmathematical operations

40-bit40-bit

MAC MAC

AC0AC1AC2AC3

40-bitALU

Shift

Viterbi HardwareViterbi HardwareTransition RegsTransition Regs

Bit OperationsBit Operations

BB[16]BB[16]

CB[16]CB[16]

DB[16]DB[16]

Now, what happens to the result?...Now, what happens to the result?...

FF_FFFFFF_FFFF

00_000000_0000

ExternalExternal

InternalInternal


ESIEE, Slide 23

C55x Writes (E and F buses)C55x Writes (E and F buses)

AUAU

32-bit write in one cycle32-bit write in one cycle

EAB[24]EAB[24]

FAB[24]FAB[24]

FB[16]FB[16]

EB[16]EB[16]

FF_FFFFFF_FFFF

00_000000_0000

ExternalExternal

InternalInternal

AC0AC1AC0AC1

DUDU

AC2AC3


ESIEE, Slide 24

Focus on C55x ArchitectureFocus on C55x Architecture


ESIEE, Slide 25

Functional Diagram of C5510 1 of 2 Functional Diagram of C5510 1 of 2


ESIEE, Slide 26

Functional Diagram of C5510 2 of 2Functional Diagram of C5510 2 of 2


ESIEE, Slide 27

Pipelines of the C55xPipelines of the C55x

Pipeline execution breaks an operation into smaller Pipeline execution breaks an operation into smaller pieces that can be executed independently.pieces that can be executed independently.

The fetch pipeline is done inside the Instruction The fetch pipeline is done inside the Instruction Buffer Unit and fills IBQ Buffer Unit and fills IBQ

The execute pipeline fetches instructions from IBQ The execute pipeline fetches instructions from IBQ and executes themand executes them

There are 2 independent pipelines:There are 2 independent pipelines:

Program fetch pipeline (3 clock cycles)Program fetch pipeline (3 clock cycles)

Program execution pipeline (7 clock cycles)Program execution pipeline (7 clock cycles)


ESIEE, Slide 28

C55x C55x Fetch PacketFetch Packet Pipeline Pipeline

PUPU

Fetch-packet pipeline fetches Fetch-packet pipeline fetches 4-byte packets4-byte packets from program from programmemory INTO the IBQ every cycle (unless IBQ is full)memory INTO the IBQ every cycle (unless IBQ is full)

Fetch packet pipeline operates Fetch packet pipeline operates independentlyindependently from execute pipeline from execute pipeline

IUIU AUAU DUDU

Data Read Buses (B,C,D)Data Read Buses (B,C,D)AA

DDData Write Buses (E,F)Data Write Buses (E,F)

Program BusProgram Bus

EEMMIIFF

IBQIBQ

64x864x8

PF1PF1 PF2PF2 FF

PF1PF1

PF1PF1

PF2PF2

PF2PF2

FF

FFF - fetch 4-byte packetF - fetch 4-byte packetPF2 PF2 PF1 PF1 - gen prog address- gen prog address

4 bytes4 bytes- memory wait- memory wait


ESIEE, Slide 29

DD ADAD AC1AC1AC2AC2 RR XX WW

DD ADAD AC1AC1AC2AC2 RR XX WW

DD

DD

DD

DD

DD

ADAD

ADAD

ADAD

ADAD

ADAD

AC1AC1AC2AC2 RR XX WW




AC1AC1AC2AC2 RR XX WWW - write to memoryW - write to memoryX - executeX - execute

D - decode D - decode opcodeopcode

IBQIBQ

64x864x8 1-61-6bytesbytes

IU performs fetch/decode from IBQIU performs fetch/decode from IBQ

AU generates operand addressesAU generates operand addresses AU/DU execute instructionsAU/DU execute instructions X: result to registerX: result to register

W: result to memoryW: result to memory

Execute pipelineExecute pipeline fetches fetches instructionsinstructionsFROM the IBQ, then executes themFROM the IBQ, then executes them

IUIU AUAU DUDU

Data Read Buses (B,C,D)Data Read Buses (B,C,D)

Data Write Buses (E,F)Data Write Buses (E,F)

AA

DD

EEMMIIFF

AD - compute addressAD - compute addressAC1 - gen read addressAC1 - gen read addressAC2 - memory waitAC2 - memory waitR - read operandsR - read operands

C55x C55x ExecuteExecute Pipeline Pipeline


ESIEE, Slide 30

DDRead six bytes from the instruction buffer queue.Read six bytes from the instruction buffer queue.Decode an instruction pair or a single instruction.Decode an instruction pair or a single instruction.Dispatch instructions to the appropriate CPU functional units.Dispatch instructions to the appropriate CPU functional units.Read STx_55 bits associated with data address generation:Read STx_55 bits associated with data address generation:ST1_55(CPL), ST2_55(ARnLC), ST2_55(ARMS), ST2_55(CDPLC)ST1_55(CPL), ST2_55(ARnLC), ST2_55(ARMS), ST2_55(CDPLC)

ADADRead/modify registers involved in data address generation. Read/modify registers involved in data address generation. Perform operations that use the A-unit ALU. Perform operations that use the A-unit ALU. Decrement ARx for the conditional branch instruction Decrement ARx for the conditional branch instruction Evaluate the condition of the XCC instructionEvaluate the condition of the XCC instruction

AC1AC1Memory read operations, send addresses on the appropriate CPU Memory read operations, send addresses on the appropriate CPU address buses.address buses.

Execute Pipeline Phases 1 of 2Execute Pipeline Phases 1 of 2


ESIEE, Slide 31

AC2AC2Allows one cycle for memories to respond to read requests.Allows one cycle for memories to respond to read requests.

RRRead data from memory, I/O space, and MMR-addressed registers.Read data from memory, I/O space, and MMR-addressed registers.Read A-unit registers Read A-unit registers Evaluate the conditions of conditional instructions.Evaluate the conditions of conditional instructions.

XXRead/modify registers that are not MMR-addressed.Read/modify registers that are not MMR-addressed.Read/modify individual register bits.Read/modify individual register bits.Set conditions.Set conditions.Evaluate the condition of the RPTCC instruction.Evaluate the condition of the RPTCC instruction.

WWWrite data to MMR-addressed registers or to I/O space (peripheral Write data to MMR-addressed registers or to I/O space (peripheral registers).registers).Write data to memory. Write data to memory.

Execute Pipeline Phases 2 of 2Execute Pipeline Phases 2 of 2


ESIEE, Slide 32

A(24)

A(24)

D(32)

D(32)

C55xx C55xx corecore

InternalInternal00_00C000_00C0

01_000001_0000

05_000005_0000

MMRsMMRs

DARAM (32KW)DARAM (32KW)

SARAM (128KW)SARAM (128KW)

ExternalExternal

ProgramProgram DataData Program and data shareProgram and data sharethe same mapthe same map

1. Program - (Bytes)1. Program - (Bytes)

- 16M x 8-bit, linear 24-bit- 16M x 8-bit, linear 24-bit addresses addresses

- Used by fetch/decode logic - Used by fetch/decode logic

2. Data (Words)2. Data (Words)

- 8M x 16-bit, segmented into- 8M x 16-bit, segmented into 64K pages, 23-bit address 64K pages, 23-bit address

- Most code written by a user- Most code written by a user will access data will access data

2 ways to view the map:2 ways to view the map:

FF_FFFFFF_FFFF

00_006000_0060

00_800000_8000

02_800002_8000

7F_FFFF7F_FFFF

00_000000_0000 00_000000_0000

2323 00ProgProg

002323 0011

DataData

C5510 Unified Memory MapC5510 Unified Memory Map


ESIEE, Slide 33

Memory AccessMemory Access 16M bytes of memory are addressable as 16M bytes of memory are addressable as

program space or data space program space or data space When the CPU uses program space to read When the CPU uses program space to read

program code from memory, it usesprogram code from memory, it uses 24-bit 24-bit addresses to reference bytes.addresses to reference bytes.

When program accesses data space, it uses 23-bit When program accesses data space, it uses 23-bit addresses to reference 16-bit words.addresses to reference 16-bit words.

In both cases, the address buses carry 24-bit In both cases, the address buses carry 24-bit values, but during a data-space access, the least values, but during a data-space access, the least significant bit on the address bus is forced to 0.significant bit on the address bus is forced to 0.


ESIEE, Slide 34

Data MemoryData Memory

Data space is divided into 128 main data pages (0 Data space is divided into 128 main data pages (0 through 127) of 64K addresses each.through 127) of 64K addresses each.

An instruction that references a main data page An instruction that references a main data page concatenates a 7-bit main data page value with a 16-bit concatenates a 7-bit main data page value with a 16-bit offset.offset.

On data page 0, the first 96 addresses (00 0000h-On data page 0, the first 96 addresses (00 0000h-00 005Fh) are reserved for the memory-mapped 00 005Fh) are reserved for the memory-mapped registers (MMRs).registers (MMRs).


ESIEE, Slide 35

I/O MemoryI/O Memory I/O space is separate from data/program space and is I/O space is separate from data/program space and is

available only for accessing registers of the available only for accessing registers of the peripherals on the DSP. The word addresses in I/O peripherals on the DSP. The word addresses in I/O space are 16 bits wide, enabling access to 64K space are 16 bits wide, enabling access to 64K locationslocations

The CPU uses the data-read address bus DAB for The CPU uses the data-read address bus DAB for reads and data-write address bus EAB for writes. reads and data-write address bus EAB for writes. When the CPU reads from or writes to I/O space, the When the CPU reads from or writes to I/O space, the 16-bit address is concatenated with leading 0s. 16-bit address is concatenated with leading 0s.

Example, suppose an instruction reads a word at the 16-bit address Example, suppose an instruction reads a word at the 16-bit address 0102h. DAB carries the 24-bit value 00 0102h.0102h. DAB carries the 24-bit value 00 0102h.


ESIEE, Slide 36

EHPIEHPI- 16-bit host access to memory- 16-bit host access to memory

DMADMA- 6 Channels (rotating priority)- 6 Channels (rotating priority)

EMIFEMIF- Access to EPROM, SRAM, SBSRAM,- Access to EPROM, SRAM, SBSRAM, SDRAM SDRAM

BOOT LoaderBOOT Loader- From external memory, Host, McBSP- From external memory, Host, McBSP

3 Multi-Channel Buffered SPs3 Multi-Channel Buffered SPs - High speed sync serial comm- High speed sync serial comm

General Purpose I/OGeneral Purpose I/O- 8-bit i/o port- 8-bit i/o port

Timer/CountersTimer/Counters- Two 20-bit timer/counters- Two 20-bit timer/counters

Power-Down ModesPower-Down Modes

Instruction Cache (24K bytes)Instruction Cache (24K bytes)

55xx55xxCPUCPU

C5510C5510

ExternalExternalMemoryMemory

EMIFEMIF

DMADMA

BootBoot

EHPIEHPIHostHost MCBSPMCBSP

TimersTimers

PowerPower

GPIOGPIO

CacheCache

C5510 Peripheral OverviewC5510 Peripheral Overview


CPU Registers DescriptionCPU Registers Description

C54x and C55xC54x and C55x


ESIEE, Slide 38

CPU Registers C54x vs C55xCPU Registers C54x vs C55x

The study of CPU registers gives a very The study of CPU registers gives a very good understanding on the processor good understanding on the processor architecture.architecture.

The C54x DSP is code compatible with The C54x DSP is code compatible with the C55x, therefore registers have the the C55x, therefore registers have the same functionally in both DSPs.same functionally in both DSPs.

Registers in the C55x are more complex Registers in the C55x are more complex so we will see their role and give so we will see their role and give equivalents for the C54x.equivalents for the C54x.

The following table summarizes the The following table summarizes the differences.differences.


ESIEE, Slide 39

C55x CPU Registers andC55x CPU Registers and C54x Equivalents 1 of 3 C54x Equivalents 1 of 3

Abbreviation Name Size C54x

AC0–AC3 Accumulators 0 through 3 40 bits A , B

AR0–AR7 Auxiliary registers 0 to 7 16 bits same

BK03, BK47, BKC Circular buffer size registers 16 bits BK

BRC0, BRC1 Block-repeat counters 0 & 1 16 bits BRC

BRS1 BRC1 Save register 16 bits none

BSA01,BSA23,BSA45,BSA67, BSA

Circular buffer start addressregisters

16 bits none

CDP Coefficient data pointer (lowpart of XCDP)

16 bits none

CDPH High part of XCDP 7 bits none


ESIEE, Slide 40

C55x CPU Registers andC55x CPU Registers and C54x Equivalents 2 of 3 C54x Equivalents 2 of 3

CFCT Control-flow context register 8 bits none

CSR Computed single-repeat register

16 bits none

DBIER0,DBIER1

Debug interrupt enable registers 0 and 1

16 bits none

DP Data page register (lowpart of XDP)

16 bits DP(9 )

DPH High part of XDP 7 bits none

IER0, IER1 Interrupt enable registers 0& 1 16 bits IMR

IFR0, IFR1 Interrupt flag registers 0 and 1 16 bits IFR

IVPD, IVPH Interrupt vector pointers 16 bits IPTR(9 )

PC Program counter 24 bits PC(16)

PDP8 Peripheral data page register 9 bits none

REA0, REA1Block-repeat end address

registers 0 and 124 bits REA


ESIEE, Slide 41

C55x CPU Registers andC55x CPU Registers and C54 Equivalents 3 of 3 C54 Equivalents 3 of 3

RETA Return address register 24 bits na.

RPTC Single-repeat counter 16 bits na.

RSA0, RSA1Block-repeat start address registers 0

and 124 bits RSA

SP Data stack pointer 16 bits SP

SPH High part of XSP and XSSP 7 bits na.

SSP System stack pointer 16 bits na.

ST0_55–ST3_55 Status registers 0 through 3 16 bitsST0,ST1,PMST

T0–T3 Temporary registers 0 to 3 16 bits T

TRN0, TRN1 Transition registers 0 and 1 16 bits TRN

XAR0–XAR7Extended auxiliary registers 0 through

7 23 bits na.

XCDP Extended coefficient data pointer 23 bits na.

XDP Extended data page register 23 bits na.

XSP Extended data stack pointer 23 bits na.

XSSP Extended system stack pointer 23 bits na.

XPC(not C55) Extended program counter 7 bits C548, C549, C5402, C5410,C5420


ESIEE, Slide 42

Accumulators (AC0–AC3) The C55 contains four 40-bit accumulators:The C55 contains four 40-bit accumulators:

AC0, AC1, AC2, and AC3 (The primary function of AC0, AC1, AC2, and AC3 (The primary function of these these registers is to assist in data computation in the D unit: registers is to assist in data computation in the D unit: ALU, ALU, MACs and the shifter. MACs and the shifter.

The four accumulators are equivalent:The four accumulators are equivalent:any instruction that uses an accumulator can be any instruction that uses an accumulator can be

programmed programmed to use any one of the four.to use any one of the four.

Each accumulator is partitioned into:Each accumulator is partitioned into:a low word (ACxL), a high word (ACxH), and eight a low word (ACxL), a high word (ACxH), and eight

guard guard bits (ACxG).bits (ACxG).

Each of portion can be accessed individually:Each of portion can be accessed individually:by using addressing modes that access the memory-by using addressing modes that access the memory-

mapped mapped registers.registers.

In the TMS320C54x-compatible mode (C54CM = 1), In the TMS320C54x-compatible mode (C54CM = 1), accumulators AC0 and AC1 correspond to accumulators AC0 and AC1 correspond to TMS320C54x accumulators A and B, respectively.TMS320C54x accumulators A and B, respectively.


ESIEE, Slide 43

Transition Registers (TRN0, TRN1) The two transition registers are used in the compare-The two transition registers are used in the compare-

and-select-extremum instructions:and-select-extremum instructions: When performing two 16-bit extremum selections update When performing two 16-bit extremum selections update

TRN0 and TRN1 based on the comparison of two TRN0 and TRN1 based on the comparison of two accumulators’ high words and low words.accumulators’ high words and low words.

TRN0 is updated based on the comparison of the TRN0 is updated based on the comparison of the accumulatorsaccumulators high words; high words;

TRN1 is updated based on the comparison of the low words.TRN1 is updated based on the comparison of the low words. When performing a single 40-bit extremum selection the When performing a single 40-bit extremum selection the

selected transition register (TRN0 or TRN1) is updated selected transition register (TRN0 or TRN1) is updated based on the comparison of two accumulators throughout based on the comparison of two accumulators throughout their 40 bits.their 40 bits.

TRN0 and TRN1 can hold transition decisions for the TRN0 and TRN1 can hold transition decisions for the path to new metrics in Viterbi algorithm path to new metrics in Viterbi algorithm implementations.implementations.


ESIEE, Slide 44

Temporary Registers (T0–T3)Temporary Registers (T0–T3)

Four 16-bit general-purpose temporary Four 16-bit general-purpose temporary registers: T0–T3 can be used for:registers: T0–T3 can be used for: Hold one of the memory multiplicands for Hold one of the memory multiplicands for

multiply, multiply-and-accumulate, and multiply-multiply, multiply-and-accumulate, and multiply-and-subtract instructionsand-subtract instructions

Hold the shift count used in addition, subtraction, Hold the shift count used in addition, subtraction, and load instructions performed in the D unitand load instructions performed in the D unit

Keep track of more pointer values by swapping Keep track of more pointer values by swapping the contents of the auxiliary registers (AR0–AR7) the contents of the auxiliary registers (AR0–AR7) and the temporary registers (using a swap and the temporary registers (using a swap instruction)instruction)

Hold the transition metric of a Viterbi butterfly Hold the transition metric of a Viterbi butterfly for dual 16-bit operations performed in the D-unit for dual 16-bit operations performed in the D-unit ALUALU


ESIEE, Slide 45

Registers Used to Address Data Space and Registers Used to Address Data Space and I/O SpaceI/O Space

Auxiliary Registers (XAR0–XAR7 / AR0–AR7)

The CPU includes eight extended auxiliary The CPU includes eight extended auxiliary registers XAR0–XAR7registers XAR0–XAR7

Each high part ( ARnH) is used to specify the 7-Each high part ( ARnH) is used to specify the 7-bit main data page for accesses to data space.bit main data page for accesses to data space.

Each low part ( ARn) can be used as:Each low part ( ARn) can be used as: A 16-bit offset to the 7-bit main data page (to form a 23-bit A 16-bit offset to the 7-bit main data page (to form a 23-bit

address)address) A bit address (in instructions that access individual bits or bit A bit address (in instructions that access individual bits or bit

pairs)pairs) A general-purpose register or counterA general-purpose register or counter


ESIEE, Slide 46

ARn and XARn AccessARn and XARn Access ARn Auxiliary register n and XARn Extended ARn Auxiliary register n and XARn Extended

auxiliary register n are accessible via auxiliary register n are accessible via dedicated instructions . dedicated instructions .

ARn is mapped to memoryARn is mapped to memory

XARn is not mapped to memory.XARn is not mapped to memory.

ARnH high part of extended auxiliary register ARnH high part of extended auxiliary register n is Not individually accessible. n is Not individually accessible.

To access ARnH, you must access XARn.To access ARnH, you must access XARn.

XAR0–XAR7 or AR0–AR7 are used in the XAR0–XAR7 or AR0–AR7 are used in the AR indirect addressing mode and the dual AR AR indirect addressing mode and the dual AR indirect addressing mode. indirect addressing mode.

Basic arithmetical, logical and shift operations Basic arithmetical, logical and shift operations can be performed on AR0–AR7 in the A-unit can be performed on AR0–AR7 in the A-unit arithmetic logic unit (ALU).arithmetic logic unit (ALU).


ESIEE, Slide 47

Coefficient Data Pointer (XCDP / CDP)

CDP is a coefficient data pointer, and CDPH CDP is a coefficient data pointer, and CDPH an associated extension register, concatenate an associated extension register, concatenate the two form the extended CDP that is called the two form the extended CDP that is called XCDP XCDP

CDPH is used to specify the 7-bit main data CDPH is used to specify the 7-bit main data page for accesses to data spacepage for accesses to data space. .

The low 16 bits part (CDP) can be used as:The low 16 bits part (CDP) can be used as:

A 16-bit offset to the 7-bit main data page A 16-bit offset to the 7-bit main data page (to form a 23-bit address)(to form a 23-bit address)

A bit address (in instructions that access A bit address (in instructions that access individual bits or bit pairs)individual bits or bit pairs)

A general-purpose register or counterA general-purpose register or counter


ESIEE, Slide 48

XCDP and CDP AccessesXCDP and CDP Accesses

XCDP Extended coefficient data pointer is XCDP Extended coefficient data pointer is accessible via dedicated instructions only.accessible via dedicated instructions only.

XCDP is not a register mapped to memoryXCDP is not a register mapped to memory.. CDP Coefficient data pointer is accessible via CDP Coefficient data pointer is accessible via

dedicated instructions and as a memory-dedicated instructions and as a memory-mapped registermapped register

CDPH High part of extended coefficient data CDPH High part of extended coefficient data pointer is accessible via dedicated instructions pointer is accessible via dedicated instructions and as a memory-mapped registerand as a memory-mapped register


ESIEE, Slide 49

Circular Buffer Start Address RegistersCircular Buffer Start Address Registers(BSA01, BSA23, BSA45, BSA67, BSAC)(BSA01, BSA23, BSA45, BSA67, BSAC)

The CPU includes five 16-bit circular buffer The CPU includes five 16-bit circular buffer start address registersstart address registers

Each buffer start address register is Each buffer start address register is associated with a particular pointer associated with a particular pointer

A buffer start address is added to the pointer A buffer start address is added to the pointer only when the pointer is configured for only when the pointer is configured for circular addressing in status register ST2_55.circular addressing in status register ST2_55.


ESIEE, Slide 50

Circular Buffer Size RegistersCircular Buffer Size Registers(BK03, BK47, BKC)(BK03, BK47, BKC)

Three 16-bit circular buffer size registers Three 16-bit circular buffer size registers specify the number of words (up to 65535) in specify the number of words (up to 65535) in a circular buffer. a circular buffer.

Each buffer size register is associated with Each buffer size register is associated with particular pointersparticular pointers

In the TMS320C54x-compatible mode In the TMS320C54x-compatible mode (C54CM = 1), BK03 is used for all the (C54CM = 1), BK03 is used for all the auxiliary registers, and BK47 is not used.auxiliary registers, and BK47 is not used.


ESIEE, Slide 51

Data Page Register (XDP / DP)Data Page Register (XDP / DP) Data page register, DP, and associated Data page register, DP, and associated

extension register DPH can be concatenated extension register DPH can be concatenated to form an extended DP that is called XDPto form an extended DP that is called XDP

The high part (DPH) is used to specify the 7-The high part (DPH) is used to specify the 7-bit main data page for accesses to data space.bit main data page for accesses to data space.

The low part specifies a 16-bit offset (local The low part specifies a 16-bit offset (local data page) that is concatenated with the main data page) that is concatenated with the main data page to form a 23-bit address.data page to form a 23-bit address.

In the DP direct addressing mode, XDP In the DP direct addressing mode, XDP specifies a 23-bit address, and in the k16 specifies a 23-bit address, and in the k16 absolute addressing mode, DPH is absolute addressing mode, DPH is concatenated with a 16-bit immediate value to concatenated with a 16-bit immediate value to form a 23-bit address.form a 23-bit address.


ESIEE, Slide 52

DP/ XDP AccessesDP/ XDP Accesses XDP Extended data page register Accessible XDP Extended data page register Accessible

via dedicated instruction only. XDP is not a via dedicated instruction only. XDP is not a register mapped to memory.register mapped to memory.

DP Data page register accessible via dedicated DP Data page register accessible via dedicated instructions and as a memory-mapped instructions and as a memory-mapped registerregister

DPH High part of extended data page DPH High part of extended data page Register is accessible via dedicated Register is accessible via dedicated instructions and as a memory-mapped instructions and as a memory-mapped registerregister


ESIEE, Slide 53

Peripheral Data Page Register (PDP)Peripheral Data Page Register (PDP)

The 9-bit peripheral data page register The 9-bit peripheral data page register (PDP) selects a 128-word page within the (PDP) selects a 128-word page within the 64K-word I/O space.64K-word I/O space.


ESIEE, Slide 54

Stack Pointers (XSP / SP, XSSP / SSP)Stack Pointers (XSP / SP, XSSP / SSP) The data stack pointer (The data stack pointer (SPSP), a system stack ), a system stack

pointer (pointer (SSPSSP), and an associated extension ), and an associated extension register (register (SPHSPH) are the CPU stack registers) are the CPU stack registers

When accessing the data stack, the CPU When accessing the data stack, the CPU concatenates SPH with SP to form an concatenates SPH with SP to form an extended SP that is called XSP.extended SP that is called XSP.

XSP contains the address of the value last XSP contains the address of the value last pushed onto the data stack.pushed onto the data stack.

SPH holds the 7-bit main data page of SPH holds the 7-bit main data page of memory, and SP points to the specific word memory, and SP points to the specific word on that page.on that page.


ESIEE, Slide 55

Stack Register AccessesStack Register Accesses XSP Extended data stack pointer is accessible XSP Extended data stack pointer is accessible

via dedicated instructions only. XSP is not a via dedicated instructions only. XSP is not a register mapped to memory.register mapped to memory.

SP Data stack pointer is accessible via SP Data stack pointer is accessible via dedicated instructions and as a memory-dedicated instructions and as a memory-mapped registermapped register

XSSP Extended system stack pointer is XSSP Extended system stack pointer is accessible via dedicated instructions only. accessible via dedicated instructions only. XSSP is not a register mapped to memory.XSSP is not a register mapped to memory.

SSP System stack pointer is accessible via SSP System stack pointer is accessible via dedicated instructions and as a memory-dedicated instructions and as a memory-mapped registermapped register

SPH High part of XSP and XSSP is accessible SPH High part of XSP and XSSP is accessible via dedicated instructions and as a memory-via dedicated instructions and as a memory-mapped register. mapped register.


ESIEE, Slide 56

Program Flow Registers (PC, RETA, CFCT)

PC Program counter is a 24-bit register holds PC Program counter is a 24-bit register holds the address of the 1 to 6 bytes of code being the address of the 1 to 6 bytes of code being decoded in the I unit.decoded in the I unit.

When the CPU performs an interrupt or call, When the CPU performs an interrupt or call, the current PC value (the return address) is the current PC value (the return address) is stored on the stack, and then PC is loaded stored on the stack, and then PC is loaded with a new address.with a new address.

When the CPU returns from an interrupt When the CPU returns from an interrupt service routine or a called subroutine, the service routine or a called subroutine, the return address is restored to PC. return address is restored to PC.


ESIEE, Slide 57

RETA Return Address RegisterRETA Return Address Register CFCT Control-flow Context Register CFCT Control-flow Context Register

If the selected stack configuration uses the If the selected stack configuration uses the fast-return processfast-return process

RETA is a temporary holding place for the return RETA is a temporary holding place for the return address and CFCT is a temporary holding place for address and CFCT is a temporary holding place for the 8-bit loop context while a subroutine is being the 8-bit loop context while a subroutine is being executedexecuted

CFCT, along with RETA, enables the efficient CFCT, along with RETA, enables the efficient execution of multiple layers of subroutinesexecution of multiple layers of subroutines

You can read from or write to RETA and CFCT as You can read from or write to RETA and CFCT as a pair with dedicated, 32-bit load and store a pair with dedicated, 32-bit load and store instructions.instructions.

The Loop context is stored into CFCT, when an The Loop context is stored into CFCT, when an interrupt or a subroutine call occur the loop interrupt or a subroutine call occur the loop context is stored in CFCT and restored on return. context is stored in CFCT and restored on return.


ESIEE, Slide 58

Registers For Managing InterruptsRegisters For Managing Interrupts

IVPD Point to the DSP interrupt vectorsIVPD Point to the DSP interrupt vectors

(IV0–IV15 and IV24–IV31)(IV0–IV15 and IV24–IV31) IVPH Point to the host interrupt vectors IVPH Point to the host interrupt vectors

(IV16–IV23)(IV16–IV23) IFR0, IFR1 Indicate which maskable IFR0, IFR1 Indicate which maskable

interrupts have been requestedinterrupts have been requested IER0, IER1 Enable or disable maskable IER0, IER1 Enable or disable maskable

interrupts interrupts DBIER0, DBIER1 Configure select maskable DBIER0, DBIER1 Configure select maskable

interrupts as time-critical interruptsinterrupts as time-critical interrupts


ESIEE, Slide 59

Interrupt Vector Pointers (IVPD, IVPH)Interrupt Vector Pointers (IVPD, IVPH)

The DSP interrupt vector pointer (IVPD) points to the The DSP interrupt vector pointer (IVPD) points to the 256-byte program page that contains the DSP 256-byte program page that contains the DSP interrupt vectors (IV0–IV15 and IV24–IV31). These interrupt vectors (IV0–IV15 and IV24–IV31). These vectors can be mapped to memory that is allocated to vectors can be mapped to memory that is allocated to the DSP only.the DSP only.

The host interrupt vector pointer (IVPH) points to the The host interrupt vector pointer (IVPH) points to the 256-byte program page that contains the host 256-byte program page that contains the host interrupt vectors (IV16–IV23). These vectors can be interrupt vectors (IV16–IV23). These vectors can be mapped to memory shared by the DSP and the host mapped to memory shared by the DSP and the host processor, so that the host processor can define the processor, so that the host processor can define the associated interrupt service routines.associated interrupt service routines.

If IVPD and IVPH have the same value, all of the If IVPD and IVPH have the same value, all of the interrupt vectors will be in the same 256-byte program interrupt vectors will be in the same 256-byte program page. page.

Two 16-bit interrupt vector pointers (IVPD and IVPH) Two 16-bit interrupt vector pointers (IVPD and IVPH) point to interrupt vectors in program space.point to interrupt vectors in program space.


ESIEE, Slide 60

Interrupt Flag Registers (IFR0, IFR1)Interrupt Flag Registers (IFR0, IFR1)

The 16-bit interrupt flag registers, IFR1 and The 16-bit interrupt flag registers, IFR1 and IFR0, contain flag bits for all the maskable IFR0, contain flag bits for all the maskable interrupts:interrupts: When a maskable interrupt request reaches the When a maskable interrupt request reaches the

CPU, the corresponding flag is set to 1 in one of CPU, the corresponding flag is set to 1 in one of the IFRs. the IFRs.

This indicates that the interrupt is pending, or This indicates that the interrupt is pending, or waiting for acknowledgement from the CPU.waiting for acknowledgement from the CPU.

One can read IFRs to identify pending interrupts, One can read IFRs to identify pending interrupts, and write to the IFRs to clear pending interrupts.and write to the IFRs to clear pending interrupts.

To clear an interrupt request write a 1 to the To clear an interrupt request write a 1 to the corresponding IFR bit. corresponding IFR bit.

All pending interrupts can be cleared by writing All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR.the current contents of the IFR back into the IFR.

Acknowledgement of a hardware interrupt Acknowledgement of a hardware interrupt request also clears the corresponding IFR bit.request also clears the corresponding IFR bit.

A device reset clears all IFR bits.A device reset clears all IFR bits.


ESIEE, Slide 61

RTOSINTF Bit in IFR1RTOSINTF Bit in IFR1 RTOSINTF bit 10 in IFR1 is an interrupt flag RTOSINTF bit 10 in IFR1 is an interrupt flag

bit for the real-time operating system bit for the real-time operating system interrupt, RTOSINTinterrupt, RTOSINT

When you read the RTOSINTF bit, When you read the RTOSINTF bit, If If RTOSINTFRTOSINTF=0, RTOSINT is not pending.=0, RTOSINT is not pending. If If RTOSINTFRTOSINTF=1, RTOSINT is pending.=1, RTOSINT is pending.

To clear this flag bit to 0 (and clear its To clear this flag bit to 0 (and clear its corresponding interrupt request), write corresponding interrupt request), write a 1 to the bit.a 1 to the bit.


ESIEE, Slide 62

DLOGINTF and BERRINTF Bits in IFR1DLOGINTF and BERRINTF Bits in IFR1

DLOGINTF is the bit 9 of IFR1 for the datalog interrupt, DLOGINTF is the bit 9 of IFR1 for the datalog interrupt, If DLOGINTF bit is:If DLOGINTF bit is:

0 then DLOGINT is not pending.0 then DLOGINT is not pending. 1 then DLOGINT is pending.1 then DLOGINT is pending.

BERRINTF is the 8th Bit in IFR1 is an Interrupt flag the BERRINTF is the 8th Bit in IFR1 is an Interrupt flag the bus error interrupt, BERRINTbus error interrupt, BERRINT

If BERRINTF bit is:If BERRINTF bit is: 0 then BERRINT is not pending.0 then BERRINT is not pending. 1 then BERRINT is pending.1 then BERRINT is pending.

To clear these flags to 0 (and clear the corresponding To clear these flags to 0 (and clear the corresponding interrupt request), write a 1 to the bit.interrupt request), write a 1 to the bit.


ESIEE, Slide 63

IF16–IF23 Bits in IFR1IF16–IF23 Bits in IFR1/IF2–IF15 Bits in IFR0/IF2–IF15 Bits in IFR0

These are flag bits in IFR1 or IFR0These are flag bits in IFR1 or IFR0 If Interrupt flag IFx is:If Interrupt flag IFx is:

0 then the interrupt associated with 0 then the interrupt associated with interrupt vector x is not pending.interrupt vector x is not pending.

1 then the interrupt associated with 1 then the interrupt associated with interrupt vector x is pending.interrupt vector x is pending.

To clear a flag bit to 0 (and clear its To clear a flag bit to 0 (and clear its corresponding interrupt request), write corresponding interrupt request), write a 1 to the bit.a 1 to the bit.


ESIEE, Slide 64

Interrupt Enable Registers (IER0, IER1)Interrupt Enable Registers (IER0, IER1)

To enable a maskable interrupt, set its To enable a maskable interrupt, set its corresponding bit in IER0 or IER1 to 1.corresponding bit in IER0 or IER1 to 1.

To disable a maskable interrupt, clear To disable a maskable interrupt, clear its corresponding enable bit to 0. its corresponding enable bit to 0.

At reset, all the IER bits are cleared to At reset, all the IER bits are cleared to 0, disabling all the maskable interrupts.0, disabling all the maskable interrupts.

IER1 and IER0 are not affected by a IER1 and IER0 are not affected by a software reset instruction or by a DSP software reset instruction or by a DSP hardware reset.hardware reset.

Initialize these registers before you Initialize these registers before you globally enable (INTM = 0) the globally enable (INTM = 0) the maskable interrupts.maskable interrupts.


ESIEE, Slide 65

RTOSINTE, DLOGINTE, BERRINTE and RTOSINTE, DLOGINTE, BERRINTE and IE16–IE23 Bits in IER1 IE16–IE23 Bits in IER1& IE2–IE15 Bits in IER0& IE2–IE15 Bits in IER0

RTOSINTE is the Enable bit for the RTOSINTE is the Enable bit for the real-time operating system real-time operating system interrupt,RTOSINTinterrupt,RTOSINT

DLOGINTE is the Enable bit for the DLOGINTE is the Enable bit for the data log interrupt, DLOGINTdata log interrupt, DLOGINT

BERRINTE is the Enable bit for the bus BERRINTE is the Enable bit for the bus error interrupt, BERRINTerror interrupt, BERRINT

IE16–IE23 bits are enable flags IE16–IE23 bits are enable flags interrupt associated with interrupt interrupt associated with interrupt vector x.vector x.

IE2–IE15 bits are enable flags interrupt IE2–IE15 bits are enable flags interrupt associated with interrupt vector x.associated with interrupt vector x.


ESIEE, Slide 66

Debug Interrupt Enable Registers Debug Interrupt Enable Registers (DBIER0, DBIER1)(DBIER0, DBIER1)

DBIER1 and DBIER0 are used only when the DBIER1 and DBIER0 are used only when the CPU is halted in the real-time emulation CPU is halted in the real-time emulation mode of the debugger.mode of the debugger.

A maskable interrupt enabled in a DBIER is A maskable interrupt enabled in a DBIER is defined as a time-critical interrupt.defined as a time-critical interrupt.

When the CPU is halted in the real-time When the CPU is halted in the real-time mode, the only interrupts that are serviced mode, the only interrupts that are serviced are time-critical interrupts that are also are time-critical interrupts that are also enabled in an interrupt enable register (IER1 enabled in an interrupt enable register (IER1 or IER0).or IER0).

Write the DBIERs to enable or disable time-Write the DBIERs to enable or disable time-critical interrupts. To enable an interrupt, set critical interrupts. To enable an interrupt, set its corresponding bit.its corresponding bit.


ESIEE, Slide 67

Registers for Controlling Repeat LoopsRegisters for Controlling Repeat Loops

Single-Repeat Registers (RPTC, CSR)Single-Repeat Registers (RPTC, CSR) Block-Repeat Registers (BRC0–1, Block-Repeat Registers (BRC0–1,

BRS1, RSA0–1, REA0–1)BRS1, RSA0–1, REA0–1) These CPU registers are mapped in These CPU registers are mapped in

memorymemory


ESIEE, Slide 68

Status Registers (ST0_55–ST3_55)Status Registers (ST0_55–ST3_55) The four 16-bit registers (ST0_55, ST1_55, ST2_55 The four 16-bit registers (ST0_55, ST1_55, ST2_55

and ST3_55) contain control bits and flag bitsand ST3_55) contain control bits and flag bits Control bits affect the operation of the C55x DSP Control bits affect the operation of the C55x DSP Flag bits reflect the current status of the DSP or Flag bits reflect the current status of the DSP or

indicate the results of operations.indicate the results of operations. ST0_55, ST1_55, and ST3_55 are each accessible at ST0_55, ST1_55, and ST3_55 are each accessible at

two addressestwo addresses At one address, all the TMS320C55x bits are available.At one address, all the TMS320C55x bits are available. At the other address (the protected address), some of the bits At the other address (the protected address), some of the bits

cannot be modified.cannot be modified. The protected address is provided to support TMS320C54x The protected address is provided to support TMS320C54x

code that was written to access ST0, ST1, and PMST (the code that was written to access ST0, ST1, and PMST (the C54x counterpart of ST3_55).C54x counterpart of ST3_55).


ESIEE, Slide 69

Contents of Status RegistersContents of Status Registers


ESIEE, Slide 70

ST0_55 ContentsST0_55 Contents

ACOV0, ACOV1, ACOV2, and ACOV3 bits ACOV0, ACOV1, ACOV2, and ACOV3 bits give for each of the four accumulators its own give for each of the four accumulators its own overflow flag overflow flag

CARRY: this bit is the Carry/borrow CARRY: this bit is the Carry/borrow detection and depends on the M40 bit in detection and depends on the M40 bit in ST1_55:ST1_55: M40 = 0: Carry/borrow is detected with respect to M40 = 0: Carry/borrow is detected with respect to

bit position 31.bit position 31. M40 = 1: Carry/borrow is detected with respect to M40 = 1: Carry/borrow is detected with respect to

bit position 39.bit position 39.

For compatibility with TMS320C54x code, For compatibility with TMS320C54x code, make sure M40 = 0.make sure M40 = 0.


ESIEE, Slide 71

DP Status Bits in ST0_55DP Status Bits in ST0_55 DP is a copy in ST0_55 of the 9 most DP is a copy in ST0_55 of the 9 most

significant bits of the data page register (DP)significant bits of the data page register (DP) This 9-bit field is provided for compatibility This 9-bit field is provided for compatibility

with the TMS320C54x DSPs.with the TMS320C54x DSPs. TMS320C55x DSPs have a data page pointer TMS320C55x DSPs have a data page pointer

independent of ST0_55. independent of ST0_55. Any change to bits 15–7 of the data page registerAny change to bits 15–7 of the data page register

DP(15–7) is reflected in the DP status bits. DP(15–7) is reflected in the DP status bits. Any change to the DP status bits is reflected in Any change to the DP status bits is reflected in

DP(15–7). DP(15–7).


ESIEE, Slide 72

TC1 and TC2 Bits of ST0_55TC1 and TC2 Bits of ST0_55 TC1 and TC2 are Test/Control flag TC1 and TC2 are Test/Control flag The main function of a test/control bits is to hold the The main function of a test/control bits is to hold the

result of a test performed by specific instructions.result of a test performed by specific instructions. All the instructions that affect a test/control flag allow All the instructions that affect a test/control flag allow

you to choose whether TC1 or TC2 is affected.you to choose whether TC1 or TC2 is affected. TCx (where x = 1 or 2) or a Boolean expression of TCx (where x = 1 or 2) or a Boolean expression of

TCx can be used as a trigger in any conditional TCx can be used as a trigger in any conditional instruction.instruction.

You can clear and set TC1 and TC2 with the You can clear and set TC1 and TC2 with the following instructions:following instructions:

o BCLR TC1 ; Clear TC1BCLR TC1 ; Clear TC1o BSET TC1 ; Set TC1BSET TC1 ; Set TC1o BCLR TC2 ; Clear TC2BCLR TC2 ; Clear TC2o BSET TC2 ; Set TC2BSET TC2 ; Set TC2


ESIEE, Slide 73

ASM Bit Field of ST1_55ASM Bit Field of ST1_55 ASM is the Accumulator shift mode bitASM is the Accumulator shift mode bit In the TMS320C54x-compatible mode , In the TMS320C54x-compatible mode ,

ASM supplies a shift value in the range –16 ASM supplies a shift value in the range –16 through 15 (5 bits in 2’s complement).through 15 (5 bits in 2’s complement).

If C54CM=1: C54x code running on the If C54CM=1: C54x code running on the C55x DSP, and ASM contains the shift C55x DSP, and ASM contains the shift count for instructions that specify a shift of count for instructions that specify a shift of an accumulator value.an accumulator value.

If C54CM = 0: ASM is ignored and the If C54CM = 0: ASM is ignored and the shift count for an accumulator shift shift count for an accumulator shift operation comes from the temporary operation comes from the temporary register (T0, T1, T2, or T3) specified in the register (T0, T1, T2, or T3) specified in the C55x instruction or from a constant C55x instruction or from a constant embedded in the C55x instruction.embedded in the C55x instruction.


ESIEE, Slide 74

BRAF Bit of ST1_55BRAF Bit of ST1_55 BRAF: Block-repeat active flag is used in the BRAF: Block-repeat active flag is used in the

TMS320C54x-compatible mode (C54CM = 1).TMS320C54x-compatible mode (C54CM = 1). BRAF indicates/controls the status of a block-repeat BRAF indicates/controls the status of a block-repeat

operation.operation. If C54CM = 1 (C54x mode): BRAF is saved and If C54CM = 1 (C54x mode): BRAF is saved and

restored with ST1_55 during context switches caused restored with ST1_55 during context switches caused by calls, interrupts, and returns. by calls, interrupts, and returns.

BRAF is automatically cleared when a far branch BRAF is automatically cleared when a far branch (FB) or far call (FCALL) instruction is executed.(FB) or far call (FCALL) instruction is executed.

If C54CM = 0: If C54CM = 0: BRAF is not used.BRAF is not used. The status of repeat The status of repeat operations is maintained automatically by the CPU operations is maintained automatically by the CPU (see CFCT )(see CFCT )

To stop or set an active block-repeat operation in the To stop or set an active block-repeat operation in the C54x-compatible mode, you can use the following C54x-compatible mode, you can use the following instruction:instruction: BCLR BRAF ; Clear BRAFBCLR BRAF ; Clear BRAF BSET BRAF ; Set BRAFBSET BRAF ; Set BRAF


ESIEE, Slide 75

C16 Bit of ST1_55C16 Bit of ST1_55 C16 is the Dual 16-bit arithmetic mode bit used in C16 is the Dual 16-bit arithmetic mode bit used in

the C54x-compatible mode (C54CM = 1), execution of the C54x-compatible mode (C54CM = 1), execution of some instructions is affected by C16.some instructions is affected by C16.

The arithmetic performed in the D-unit ALU depends The arithmetic performed in the D-unit ALU depends on C16:on C16: If C16 =0 then for an instruction that is affected by C16, the D-unit If C16 =0 then for an instruction that is affected by C16, the D-unit

ALU performs one 32-bit operation (double-precision arithmetic) .ALU performs one 32-bit operation (double-precision arithmetic) . If C16=1 then an instruction that is affected by C16, the D-unit If C16=1 then an instruction that is affected by C16, the D-unit

ALU performs two 16-bit operations in parallel (dual 16-bit ALU performs two 16-bit operations in parallel (dual 16-bit arithmetic).arithmetic).

If C54CM = 0: The CPU ignores C16. The instruction If C54CM = 0: The CPU ignores C16. The instruction alone determines whether dual 16-bit arithmetic or alone determines whether dual 16-bit arithmetic or 32-bit arithmetic is used.32-bit arithmetic is used.

You can clear and set C16 with the following instructions:You can clear and set C16 with the following instructions: BCLR C16 ; Clear C16BCLR C16 ; Clear C16 BSET C16 ; Set C16BSET C16 ; Set C16


ESIEE, Slide 76

C54CM Bit of ST1_55C54CM Bit of ST1_55 C54CM is the TMS320C54x-compatible mode bitC54CM is the TMS320C54x-compatible mode bit The C54CM bit determines whether the CPU will The C54CM bit determines whether the CPU will

support code that was developed for a TMS320C54x support code that was developed for a TMS320C54x DSP:DSP:

If C54CM=0 then the CPU supports code written for If C54CM=0 then the CPU supports code written for a TMS320C55x (C55x) DSP.a TMS320C55x (C55x) DSP.

If C54CM=1 then you can use code that was If C54CM=1 then you can use code that was originally developed for a TMS320C54x (C54x) DSP.originally developed for a TMS320C54x (C54x) DSP.

In C54 mode all the C55x CPU resources remain In C54 mode all the C55x CPU resources remain available; the additional features on the C55x can be available; the additional features on the C55x can be used for code optimization.used for code optimization.

Change modes with the following instructions and Change modes with the following instructions and assembler directives:assembler directives: BCLR C54CM ; Clear C54CM (happens at run time)BCLR C54CM ; Clear C54CM (happens at run time) BSET C54CM ; Set C54CM (happens at run time)BSET C54CM ; Set C54CM (happens at run time)


ESIEE, Slide 77

CPL Bit of ST1_55CPL Bit of ST1_55 CPL is the Compiler mode bit and determines CPL is the Compiler mode bit and determines

which of two direct addressing modes is active:which of two direct addressing modes is active: CPL=0 then Direct accesses to data space are CPL=0 then Direct accesses to data space are

made relative to the data page register (DP).made relative to the data page register (DP). CPL=1 then Direct accesses to data space are CPL=1 then Direct accesses to data space are

made relative to the data stack pointer (SP). The made relative to the data stack pointer (SP). The DSP is said to be in compiler mode.DSP is said to be in compiler mode.

Change modes with the following instructions Change modes with the following instructions and assembler directives:and assembler directives: BCLR CPL ; Clear CPL (happens at run BCLR CPL ; Clear CPL (happens at run

time)time) BSET CPL ; Set CPL (happens at run time)BSET CPL ; Set CPL (happens at run time)


ESIEE, Slide 78

FRCT Bit of ST1_55FRCT Bit of ST1_55

FRCT is the Fractional mode bit that FRCT is the Fractional mode bit that sets the fractional mode on or off:sets the fractional mode on or off:

FRCT=0 then results of multiply FRCT=0 then results of multiply operations are not shifted.operations are not shifted.

FRCT=1 then results of multiply FRCT=1 then results of multiply operations are shifted left by 1 bit for operations are shifted left by 1 bit for decimal point adjustment. decimal point adjustment. This is required when you multiply two This is required when you multiply two

signedQ15 values and you need a Q31 signedQ15 values and you need a Q31 result.result.

You can clear and set FRCT with :You can clear and set FRCT with : BCLR FRCT ; Clear FRCTBCLR FRCT ; Clear FRCT BSET FRCT ; Set FRCTBSET FRCT ; Set FRCT


ESIEE, Slide 79

HM Bit of ST1_55HM Bit of ST1_55 HM is the Hold mode bit used when the DSP HM is the Hold mode bit used when the DSP

acknowledges an active HOLD signal. It acknowledges an active HOLD signal. It places its external interface in the high-places its external interface in the high-impedance state. impedance state.

Depending on HM, the DSP may also stop Depending on HM, the DSP may also stop internal program execution:internal program execution:

HM=0 then the DSP continues executing HM=0 then the DSP continues executing instructions from internal program memory.instructions from internal program memory.

HM=1 then the DSP stops executing HM=1 then the DSP stops executing instructions from internal program memory.instructions from internal program memory.

To clear and set HM:To clear and set HM: BCLR HM ; Clear HMBCLR HM ; Clear HM BSET HM ; Set HMBSET HM ; Set HM


ESIEE, Slide 80

INTM Bit of ST1_55INTM Bit of ST1_55 INTM is the Interrupt mode bit, it globally enables INTM is the Interrupt mode bit, it globally enables

or disables the maskable interrupts. or disables the maskable interrupts. If INTM =0 All unmasked interrupts are enabled.If INTM =0 All unmasked interrupts are enabled. If INTM=1 All maskable interrupts are disabled.If INTM=1 All maskable interrupts are disabled.

Software interrupt instruction and software reset Software interrupt instruction and software reset instruction, set INTM before branching to the instruction, set INTM before branching to the interrupt service routine.interrupt service routine.

Before executing an interrupt service routine (ISR), Before executing an interrupt service routine (ISR), the CPU automatically sets the INTM bit to the CPU automatically sets the INTM bit to globally globally disabledisable the maskable interrupts. The ISR can re- the maskable interrupts. The ISR can re-enable the maskable interrupts by clearing the INTM enable the maskable interrupts by clearing the INTM bit.bit. BCLR INTM ; Clear INTMBCLR INTM ; Clear INTM BSET INTM ; Set INTMBSET INTM ; Set INTM

A return-from-interrupt instruction restores the A return-from-interrupt instruction restores the INTM bit from the data stack.INTM bit from the data stack.


ESIEE, Slide 81

M40 Bit of ST1_55M40 Bit of ST1_55

M40 is the computation mode bit for the D unitM40 is the computation mode bit for the D unit

M40 bit selects one of two computation modes for the M40 bit selects one of two computation modes for the D unit:D unit:

If M40=0 then the sign bit is extracted from bit If M40=0 then the sign bit is extracted from bit position 31:position 31: During arithmetic, the carry is determined with respect to During arithmetic, the carry is determined with respect to

bit position 31.bit position 31. Overflows are detected at bit position 31.Overflows are detected at bit position 31. During saturation, the saturation value is 00 7FFF FFFFh During saturation, the saturation value is 00 7FFF FFFFh

(positive overflow) or FF 8000 0000h (negative overflow).(positive overflow) or FF 8000 0000h (negative overflow). Accumulator comparisons versus 0 are done using bits 31–Accumulator comparisons versus 0 are done using bits 31–

0.0. Shift or rotate operations are performed on 32-bit values.Shift or rotate operations are performed on 32-bit values.


ESIEE, Slide 82

M40 BitM40 Bit Note: In the TMS320C54x compatible Note: In the TMS320C54x compatible

mode (C54CM = 1), CM=0mode (C54CM = 1), CM=0 An accumulator’s sign bit is extracted from bit An accumulator’s sign bit is extracted from bit

position 39.position 39. Accumulator comparisons versus 0 are done Accumulator comparisons versus 0 are done

using bits 39–0.using bits 39–0. Signed shifts are performed as if M40 = 1.Signed shifts are performed as if M40 = 1.

M= 40-bit mode. In this mode the sign bit is M= 40-bit mode. In this mode the sign bit is extracted from bit position 39, the same as extracted from bit position 39, the same as before on 40 bits.before on 40 bits.

To clear and set M40 :To clear and set M40 : BCLR M40 ; Clear M40BCLR M40 ; Clear M40 BSET M40 ; Set M40BSET M40 ; Set M40


ESIEE, Slide 83

SATD Bit of ST1_55SATD Bit of ST1_55 SATD is the Saturation mode bit, it determines SATD is the Saturation mode bit, it determines

whether the CPU saturates overflow results in the D whether the CPU saturates overflow results in the D unit:unit:

SATD =0 No saturation is performed.SATD =0 No saturation is performed. SATD=1 If an operation result gives an overflow, the SATD=1 If an operation result gives an overflow, the

result is saturated. The saturation depends on the result is saturated. The saturation depends on the value of the M40 bit:value of the M40 bit: M40 = 0 The CPU saturates the result to 00 7FFF FFFFh M40 = 0 The CPU saturates the result to 00 7FFF FFFFh

(positive overflow) or FF 8000 0000h (negative overflow).(positive overflow) or FF 8000 0000h (negative overflow). M40 = 1 The CPU saturates the result to 7F FFFF FFFFh M40 = 1 The CPU saturates the result to 7F FFFF FFFFh

(positive overflow) or 80 0000 0000h (negative overflow).(positive overflow) or 80 0000 0000h (negative overflow).

To clear and set SATD :To clear and set SATD : BCLR SATD ; Clear SATDBCLR SATD ; Clear SATD BSET SATD ; Set SATDBSET SATD ; Set SATD


ESIEE, Slide 84

SXMD Bit of ST1_55SXMD Bit of ST1_55 SXMD is the Sign-extension mode bit. It sets SXMD is the Sign-extension mode bit. It sets

and resets the sign-extension mode, which and resets the sign-extension mode, which affects accumulator operations that are affects accumulator operations that are performed in the D unit:performed in the D unit:

If SXMD=0 then sign-extension mode is off:If SXMD=0 then sign-extension mode is off: For 40-bit operations, 16-bit or smaller For 40-bit operations, 16-bit or smaller

operands are zero extended to 40 bits.operands are zero extended to 40 bits. For the conditional subtract instruction, any For the conditional subtract instruction, any

16-bit divisor produces the expected result.16-bit divisor produces the expected result. When the D-unit arithmetic logic unit (ALU) When the D-unit arithmetic logic unit (ALU)

is locally configured in its dual 16-bit mode, is locally configured in its dual 16-bit mode, 16-bit values used in the higher part of the D-16-bit values used in the higher part of the D-unit ALU are zero extended to 24 bits.unit ALU are zero extended to 24 bits.


ESIEE, Slide 85

SXMD SXMD If SXMD=1 then 40-bit operations, 16-bit or smaller

operands are sign extended to 40 bits. When the D-unit ALU is locally configured in its dual

16-bit mode, 16-bit values used in the higher part of the D-unit ALU are sign extended to 24 bits.

16-bit accumulator halves are sign extended if they are shifted right.

During a signed shift of an accumulator, if it is a 32-bit operation (M40 = 0), bit 31 is copied into the accumulator’s guard bits (39–32).

Set and reset SXMD by: BCLR SXMD ; Clear SXMD BSET SXMD ; Set SXMD


ESIEE, Slide 86

XF Bit of ST1_55XF Bit of ST1_55

The XF bit is a general-purpose output The XF bit is a general-purpose output bit that can be manipulated by software bit that can be manipulated by software and exported to XF pin of the DSPand exported to XF pin of the DSP

To clear and set XF:To clear and set XF: BCLR XF ; Clear XFBCLR XF ; Clear XF BSET XF ; Set XFBSET XF ; Set XF


ESIEE, Slide 87

AR0LC–AR7LC Bits of ST2_55AR0LC–AR7LC Bits of ST2_55

AR0LC–AR7LC Bits are the AR0LC–AR7LC Bits are the linear/circular configuration bits of the linear/circular configuration bits of the eight auxiliary registers, AR0–AR7.eight auxiliary registers, AR0–AR7. If ARnLC= 0 ARn is used for linear If ARnLC= 0 ARn is used for linear

addressingaddressing If ARnLC=1 ARn is used for circular If ARnLC=1 ARn is used for circular

addressingaddressing To clear and set the ARnLC bits To clear and set the ARnLC bits

BCLR AR0LC ; Clear AR0LCBCLR AR0LC ; Clear AR0LC BSET AR0LC ; Set AR0LCBSET AR0LC ; Set AR0LC


ESIEE, Slide 88

ARMS Bit of ST2_55ARMS Bit of ST2_55 ARMS AR mode switch bit determines the CPU mode ARMS AR mode switch bit determines the CPU mode

used for the AR indirect addressing mode:used for the AR indirect addressing mode:

ARMS=0 « DSP mode operands », provides efficient ARMS=0 « DSP mode operands », provides efficient execution of DSP intensive applications. Among these execution of DSP intensive applications. Among these operands are those that use reverse carry operands are those that use reverse carry propagation when adding to or subtracting from a propagation when adding to or subtracting from a pointer. Short-offset operands are not available.pointer. Short-offset operands are not available.

ARMS=1 « Control mode operands », enables ARMS=1 « Control mode operands », enables optimized code size for control system applications. optimized code size for control system applications. The short-offset operand *ARn(short(#k3)) is The short-offset operand *ARn(short(#k3)) is available. available. BCLR ARMS ; Clear ARMS (happens at run time)BCLR ARMS ; Clear ARMS (happens at run time) .ARMS_off ; Tell assembler ARMS = 0.ARMS_off ; Tell assembler ARMS = 0 BSET ARMS ; Set ARMS (happens at run time)BSET ARMS ; Set ARMS (happens at run time) .ARMS_on ; Tell assembler ARMS = 1.ARMS_on ; Tell assembler ARMS = 1


ESIEE, Slide 89

CDPLC Bit of ST2_55CDPLC Bit of ST2_55

CDPLC is the CDP linear/circular CDPLC is the CDP linear/circular configuration bit. It determines whether configuration bit. It determines whether the coefficient data pointer (CDP) is the coefficient data pointer (CDP) is used for linear addressing or circular used for linear addressing or circular addressing:addressing: CDPLC=0 Linear addressingCDPLC=0 Linear addressing CDPLC=1 Circular addressingCDPLC=1 Circular addressing

To clear and set CDPLC :To clear and set CDPLC : BCLR CDPLC ; Clear CDPLCBCLR CDPLC ; Clear CDPLC BSET CDPLC ; Set CDPLCBSET CDPLC ; Set CDPLC


ESIEE, Slide 90

DBGM Bit of ST2_55DBGM Bit of ST2_55 DBGM: Debug mode bit gives the ability to DBGM: Debug mode bit gives the ability to

block debug events during time-critical block debug events during time-critical portions of a program:portions of a program:

If DBGM=0 Debug is enableIf DBGM=0 Debug is enable If DBGM=1 Debug is disable, emulator If DBGM=1 Debug is disable, emulator

cannot access memory or registers.cannot access memory or registers. Software breakpoints still cause the CPU to Software breakpoints still cause the CPU to

halt, but hardware breakpoints or halt halt, but hardware breakpoints or halt requests are ignored.requests are ignored.

Before interrupt service routine CPU sets the Before interrupt service routine CPU sets the DBGM bit to disable. DBGM bit to disable.

Return-from-interrupt instruction restores Return-from-interrupt instruction restores the DBGM bit from the data stack.the DBGM bit from the data stack.


ESIEE, Slide 91

EALLOW Bit of ST2_55EALLOW Bit of ST2_55/RDM Bit of ST2_55/RDM Bit of ST2_55

EALLOW is the Emulation access enable bit. EALLOW is the Emulation access enable bit. It enables or disables write access to non-CPU It enables or disables write access to non-CPU emulation registers:emulation registers: If EALLOW =0 Emulation access is disabledIf EALLOW =0 Emulation access is disabled If EALLOW=1 Emulation is enabledIf EALLOW=1 Emulation is enabled

RDM, Rounding mode bit, defines the type of RDM, Rounding mode bit, defines the type of rounding performed by the CPU:rounding performed by the CPU: If RDM =0 the mode is Round to the infinite. If RDM =0 the mode is Round to the infinite. CPU adds 8000h (2CPU adds 8000h (21515) to the operand then clears ) to the operand then clears

bits 15 through 0 to generate a rounded result in a bits 15 through 0 to generate a rounded result in a 24- or 16-bit representation.24- or 16-bit representation.


ESIEE, Slide 92

Round Mode RDMRound Mode RDM

If RDM=1 then Round to the nearest.If RDM=1 then Round to the nearest.

The rounding depends on bits 15 through 0 of The rounding depends on bits 15 through 0 of

the operand, and bits 15–0 are clearedthe operand, and bits 15–0 are cleared

•For compatibility with TMS320C54x code,For compatibility with TMS320C54x code,

RDM must be 0 and C54CM = 1. RDM must be 0 and C54CM = 1.

•To clear or setTo clear or set

BCLR RDM ; Clear RDMBCLR RDM ; Clear RDM

BSET RDM ; Set RDMBSET RDM ; Set RDM


ESIEE, Slide 93

CACLR Bit of ST3_55CACLR Bit of ST3_55 CACLR, Cache clear bit, enables to check CACLR, Cache clear bit, enables to check

when the process for clearing the program when the process for clearing the program cache is complete:cache is complete: CACLR=0 Complete. The cache hardware clears CACLR=0 Complete. The cache hardware clears

the CACLR bit when the process is complete.the CACLR bit when the process is complete. CACLR=1 Not complete. All cache blocks are CACLR=1 Not complete. All cache blocks are

invalid. The number of cycles needed to clear the invalid. The number of cycles needed to clear the cache depends on the memory architecture.cache depends on the memory architecture.

If cache is cleared, the content of the prefetch If cache is cleared, the content of the prefetch queue in the instruction buffer unit is queue in the instruction buffer unit is automatically flushed.automatically flushed.

CACLR bit can be changed (pipeline protect):CACLR bit can be changed (pipeline protect): BCLR CACLR ; Clear CACLRBCLR CACLR ; Clear CACLR BSET CACLR ; Set CACLRBSET CACLR ; Set CACLR


ESIEE, Slide 94

CAEN Bit of ST3_55CAEN Bit of ST3_55

CAEN is the Cache enable bit that CAEN is the Cache enable bit that enables or disables the program cache:enables or disables the program cache:

CAEN =0 then cache is disabled. CAEN =0 then cache is disabled. All program requests are handled either All program requests are handled either

by the internal memory or the external by the internal memory or the external memory, depending on the address memory, depending on the address decoded.decoded.

CAEN=1 Cache is enabled. Program CAEN=1 Cache is enabled. Program code is fetched from the cache, from the code is fetched from the cache, from the internal memory, or from the external internal memory, or from the external memory, depending on the address memory, depending on the address decoded.decoded.


ESIEE, Slide 95

CAFRZ Bit of ST3_55CAFRZ Bit of ST3_55

CAFRZ is « Cache freeze bit » that freezes CAFRZ is « Cache freeze bit » that freezes the program cache. the program cache.

IF CAFRZ =0, the cache is in its default IF CAFRZ =0, the cache is in its default operating mode (updated)operating mode (updated)

If CAFRZ=1, the cache is frozen (the cache If CAFRZ=1, the cache is frozen (the cache content is locked).content is locked).

To change CAFRZ bit use:To change CAFRZ bit use: BCLR CAFRZ ; Clear CAFRZBCLR CAFRZ ; Clear CAFRZ BSET CAFRZ ; Set CAFRZBSET CAFRZ ; Set CAFRZ


ESIEE, Slide 96

CBERR Bit of ST3_55CBERR Bit of ST3_55 CBERR is the « CPU bus error flag »CBERR is the « CPU bus error flag » The CBERR bit is set when an internal bus error is The CBERR bit is set when an internal bus error is

detected. An error causes the CPU to set the bus detected. An error causes the CPU to set the bus error interrupt flag (BERRINTF) in IFR1. error interrupt flag (BERRINTF) in IFR1.

The interrupt service routine for the bus error The interrupt service routine for the bus error interrupt (BERRINT) must clear the CBERR bit interrupt (BERRINT) must clear the CBERR bit before it returns control to the interrupted programbefore it returns control to the interrupted program

using: using: BCLR CBERRBCLR CBERR ; Clear CBERR ; Clear CBERR If CBERR =0 The flag has been cleared by program If CBERR =0 The flag has been cleared by program

or by a reset.or by a reset. CBERR=1 An internal bus error has been detected.CBERR=1 An internal bus error has been detected.


ESIEE, Slide 97

CLKOFF Bit of ST3_55CLKOFF Bit of ST3_55

CLKOFF bit disables CLKOUT CLKOFF bit disables CLKOUT If CLKOFF = 1, the output of the If CLKOFF = 1, the output of the

CLKOUT pin is disabled and remains CLKOUT pin is disabled and remains at a high level.at a high level.

Set and clear by:Set and clear by: BCLR CLKOFF ; Clear CLKOFFBCLR CLKOFF ; Clear CLKOFF BSET CLKOFF ; Set CLKOFFBSET CLKOFF ; Set CLKOFF


ESIEE, Slide 98

HINT Bit of ST3_55HINT Bit of ST3_55

HINT: Host interrupt bit is used to send HINT: Host interrupt bit is used to send an interrupt request to a host processor an interrupt request to a host processor by the way of the host port interface.by the way of the host port interface.

To produce an active-low interrupt To produce an active-low interrupt pulse clear and then set the HINT bit:pulse clear and then set the HINT bit:

BCLR HINT ; Clear HINTBCLR HINT ; Clear HINT BSET HINT ; Set HINTBSET HINT ; Set HINT


ESIEE, Slide 99

MPNMC Bit of ST3_55MPNMC Bit of ST3_55

• MPNMC defines the Microprocessor / Micro-MPNMC defines the Microprocessor / Micro-computer mode computer mode

• MPNMC reflects the logic level on the MP/MC MPNMC reflects the logic level on the MP/MC pin when the pin is sampled at resetpin when the pin is sampled at reset

• The MPNMC bit enables or disables the on-chip The MPNMC bit enables or disables the on-chip ROM.ROM.

If MPNMC=0 Microcomputer mode. The on-chip If MPNMC=0 Microcomputer mode. The on-chip ROM is enabled; it is addressable in program ROM is enabled; it is addressable in program

space.space.

If MPNMC=1 Microprocessor mode. The on-chip If MPNMC=1 Microprocessor mode. The on-chip ROM is disabled; it is not in the program-space map.ROM is disabled; it is not in the program-space map.


ESIEE, Slide 100

SATA Bit of ST3_55SATA Bit of ST3_55 SATA is the Saturation mode bit for the A SATA is the Saturation mode bit for the A

unitunit SATA bit determines whether the CPU SATA bit determines whether the CPU

saturates overflow results of the A-unit saturates overflow results of the A-unit arithmetic logic unit (A-unit ALU):arithmetic logic unit (A-unit ALU): If SATA=0 No saturation is performed.If SATA=0 No saturation is performed. If SATA=1 On. If result is in overflow, If SATA=1 On. If result is in overflow,

result is saturated to 7FFFh or 8000h (for result is saturated to 7FFFh or 8000h (for positive or negative overflow respectively).positive or negative overflow respectively).

Can be cleared and set by:Can be cleared and set by: BCLR SATA ; Clear SATABCLR SATA ; Clear SATA BSET SATA ; Set SATABSET SATA ; Set SATA


ESIEE, Slide 101

SMUL Bit of ST3_55SMUL Bit of ST3_55 SMUL is the Saturation-on-multiplication SMUL is the Saturation-on-multiplication

mode bit:mode bit: If SMUL =0 OffIf SMUL =0 Off If SMUL =1 On. If SMUL =1 On. SMUL=1 forces the product of the two SMUL=1 forces the product of the two

negative numbers to be a positive number.negative numbers to be a positive number. For multiply-and-accumulate/subtract For multiply-and-accumulate/subtract

instructions, the saturation is performed after instructions, the saturation is performed after the multiplication and before the the multiplication and before the addition/subtraction.addition/subtraction.

Clear and set SMUL with :Clear and set SMUL with : BCLR SMUL ; Clear SMULBCLR SMUL ; Clear SMUL BSET SMUL ; Set SMULBSET SMUL ; Set SMUL


ESIEE, Slide 102

SST Bit of ST3_55SST Bit of ST3_55

SST is the Saturate-on-store mode bit SST is the Saturate-on-store mode bit used in the C54-compatible mode used in the C54-compatible mode (C54CM=1)(C54CM=1)

If C54CM=0 SST is ignored by the C55x. If C54CM=0 SST is ignored by the C55x. If C54CM = 1: SST turns the saturation-If C54CM = 1: SST turns the saturation-

on-store mode on or off.on-store mode on or off. SST= 0 no saturationSST= 0 no saturation SST=1 CPU saturates a shifted or SST=1 CPU saturates a shifted or

unshifted accumulator value before unshifted accumulator value before storing it. The saturation depends on the storing it. The saturation depends on the value of the sign-extension mode bit value of the sign-extension mode bit (SXMD)(SXMD)

Copyright © 2003 Texas Instruments. All rights reserved. DSP C5000 Architecture Overview.

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