Copyright © 2000, Daniel W. Lewis. All Rights Reserved. CHAPTER 4 A PROGRAMMER'S VIEW OF COMPUTER ORGANIZATION.

Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

CHAPTER 4

A PROGRAMMER'S VIEW OF COMPUTER ORGANIZATION


Two Alternative Input/Output Configurations

I/OI/O CPUCPU Memory

Memory

CPUCPU Memory

Memory

I/OI/ODirect Memory Access (DMA).

CPU coordinates transfer between I/O and memory.


Central Processing Unit and Main Memory of a Computer.

Address Bus

Control Bus

Data Bus

CPUCPU MemoryMemory

Operations performed here.

Operations performed here.

Operands and results are stored here.

Operands and results are stored here.


The Central Processing Unit

General Purpose

Registers

General Purpose

Registers

Arithmetic and Logic Unit (ALU)Arithmetic and

Logic Unit (ALU)

Program CounterProgram Counter

Instruction Register


Instruction DecoderInstruction Decoder

Memory Address Register

Memory Address Register

Memory Data Register

Memory Data Register

Data Bus

Address Bus

Control Bus

Control Unit


ALU Data Paths for Dyadic Operations Using a Single Accumulator Register.

ALUALU

AccumulatorAccumulator

Operand #1: Current contents of accumulator

Operand #1: Current contents of accumulator

Result: Replaces old contents of accumulator

Result: Replaces old contents of accumulator

Operand #2: Read from memoryOperand #2: Read from memory

Memory Data Bus

Memory Data Bus

A B


result op1 + op2

ACC MEM[adrs_of_op1]ACC ACC + MEM[adrs_of_op2]MEM[adrs_of_result] ACC

REG[r] MEM[adrs_of_op1] REG[r] REG[r] + MEM[adrs_of_op2] MEM[adrs_of_result] REG[r]

Single Accumulator Machine:

Register Machine:


The Fetch-Execute Cycle

Fetch The Next Instruction

Fetch The Next Instruction

Execute the Fetched

Instruction

Execute the Fetched

Instruction

Program counter provides the address.

Program counter provides the address.

Additional instruction bytes retrieved here as necessary.

Additional instruction bytes retrieved here as necessary.


The Fetch Phase

1. Memory_Address_Bus Program_Counter

2. Start Memory Read Operation3. Increment Program_Counter4. Wait for Memory Read to Complete5. Instruction_Register

Memory_Data_Bus6. Go to execute phase.


1000100010001001

1000 LDA [x]1001 ADD [y]1002 STA [z]

1000 LDA [x]1001 ADD [y]1002 STA [z]

1000 LDA [x]1001 ADD [y]1002 STA [z]

The Fetch Phase

+1

Address

Data

Program Counter


Main Memory

LDA [x]


Control Flow Portion of a CPU

Instruction

Register

Instruction

Register

Control Unit

(Opcode decoding and sequencing)

Control Unit

(Opcode decoding and sequencing)

ControlSignals

Memory Data Bus

Memory Data Bus

Memory Address Bus

Memory Address Bus

Opcode bits.Opcode bits.

Program CounterProgram Counter+1

Branch Address


The Intel Processor Family Processor Year MIPS

CPU Frequency

Register Size Data Bus Address Space CPU Cache

8086 1978 0.8 8.0 MHz 16 16 1 MB None

286 1982 2.7 12.5 MHz 16 16 16 MB None

386 1985 6.0 20 MHz 32 32 4 GB None

486 1989 20 25 MHz 32 32 4 GB 8 KB L1

Pentium 1993 100 60 MHz 32 64 4 GB 16 KB L1

Pentium Pro 1995 440 200 MHz 32 64 64 GB16 KB L1; 512 KB L2

Pentium II 1997 466 266 32 64 64 GB32 KB L1;512 KB L2

Pentium III 1999 1000 500 32 64 64 GB32 KB L1;512 KB L2


Operating Modes of Intel IA

• Real-address Mode: This mode corresponds to the original 8086 processor and is supported by all processors in the IA family. It is the initial operating mode when a hardware reset signal is applied to the processor at start-up. Only a limited number of processor features are available in real mode and the physical address space is limited to one megabyte.

• Protected Mode • System Management Mode



• Real-address Mode • Protected Mode: This mode was originally

introduced with the Intel 286, and later enhanced in the Intel 386. Protected mode offers greater performance than real mode. All of the features of the processor are available and a much larger physical address space.

• System Management Mode



• Real-address Mode • Protected Mode• System Management Mode: This mode was

originally introduced with the Intel 386SL. This mode is primarily used to implement power management and system security. It is not described in this text.


Four Types of Instruction Operands

1. A constant embedded within the instruction representation, or

2. The contents of a register, or

3. The contents of a memory location, or

4. The contents of an I/O port.


Instruction Formats

Operand Fields Example Description0 CLC Clear the carry flag to 0.

1 INC AX Increment contents of register AX

2 MOV AX,BX Copy contents of BX into AX.

“Source” operand“Destination” operand


General Purpose Registers31 16

15 0

(E)AX: Accumulator

(E)BX: Base Register

(E)CX: Count Register

(E)DX: Data Register

(E)SP: Stack Pointer

(E)BP: Base Pointer

(E)SI: Source Index(E)DI: Destination Index

MSW of EAX AH AL

MSW of EBX BH BL

MSW of ECX CH CL

MSW of EDX DH DL

MSW of ESP SP

MSW of EBP BP

MSW of ESI SI

MSW of EDI DI


Segment Registers

79 016 15

CS

DS

SS

ES

FS

GS

“Hidden” Part “Visible” Part

Segment SelectorCopies of GDT entries

corresponding to value of segment selectors

(not used in Real Mode)


EFlags and EIP Registers

(E)Flags Register:

(E)IP: Instruction Pointer

MSW of EFLAGS FLAGS

MSW of EIP IP

31 0


Flags Register15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Flag Bit DescriptionOverflow 11 Previous result caused arithmetic overflow.Direction 10 1 = auto-decrement, 0 = auto-increment.

Interrupt Enable 9 Interrupts are enabledTrap 8 Single step mode enabledSign 7 Previous result was negativeZero 6 Previous result was zero

Auxiliary Carry 4 Previous result produced a BCD carryParity 2 Previous result had even parityCarry 0 Previous result produced a carry put of MSB


Byte Ordering of 32‑bit Value With Little Endian Format.

0001 0010 0011 0100 0101 0110 0111 1000

Byte N+3 Byte N+2 Byte N+1 Byte N

32‑bit value = 1234567816

32‑bit value = 1234567816

In little endian format, the address of a 32‑bit quantity is the same as the address of its least significant byte.

In little endian format, the address of a 32‑bit quantity is the same as the address of its least significant byte.


The Stack

Instruction sequence: Address Memory contents

PUSH EBX SS:[ESP+10]

value from EBX(32 bits)

Stack "grows" downward.PUSH AX SS:[ESP+8] value from AX

(16 bits)

PUSH CS SS:[ESP+4] value from CS(32 bits)

PUSH EDX SS:[ESP] value from EDX(32 bits)

Top of stack


Real-Mode Addressing16-bit segment 0000 16-bit offset

12 MSBs of offsetpadded with four 0's

on the left

4 LSBsof offset

16-bit Adder

16 MSBsof result

4 LSBsof result

20-bit physical address


Memory

Operand 8B40316

The segment value establishes a reference point to the beginning of a 64kb block of memory; the offset is a positive displacement from this reference.

Offset = 012316

Segment = 8B2E16 8B2E016

Real-Mode Addressing


Instruction Operands

Constant• Immediate Mode

– Embedded within representation of instruction.

Register• Register Mode

I/O Port

Memory Location• Real Mode:

Address = RB + RI + constant

• Protected Mode:Address = R1 + C1 R2 + C2


Immediate Mode(Example: MOV AX,12345)

opcode 16-bit operand Operand is embedded withininstruction representation.






I/O Port





Register Mode(Example: MOV AX,CX)

opcode code registersAH AL BH BLCH CL DH DLAX BX CX DX

Instruction has code to select SI DI SP BPregister contents as operand DS CS SS ES






I/O Port





ADDRESSING MEMORYIN

REAL MODE


Real-Mode Addressing

BX

BP

None

BX

BP

None

SI

DI

None

SI

DI

None

16-bit

8-bit

None

16-bit

8-bit

None

++

Base Index Constant


Direct Addressing Mode(Example: MOV AX,[TOTAL])

opcode 16-bit offset Instruction provides memoryoffset

operand



Register Indirect Mode(Example: MOV AX,[BX])

opcode code memory

BX, BP, SI, or DI operandRegister provides offset


Address = RB + RI + constantor


Indexed and Based Address Mode(Example: MOV AX,[BX+3])

opcode code displacement Offset is sum of selected memoryregister and displacement.

Code selectsregister to use + operand

BX, BP, SI, DI Based: BX or BPIndexed: SI or DI


Address = RB + RI + constantor


Based-indexed Address Mode(Example: MOV AX,[BX+SI+3])

opcode code code displacement memory

BX or BP + operand

SI or DI



ADDRESSING MEMORYIN

PROTECTED MODE


How Segment Registers are Used

16-bit Segment Selector16-bit Segment Selector

32-bit offset from effective address calculation32-bit offset from effective address calculation

+

Global Descriptor Table

Segment Start Address

Physical Address (& Length) of Global Descriptor Table

Physical Address (& Length) of Global Descriptor Table

PhysicalAddress

Resides in Main

Memory

Resides in Main

Memory

. . .

GDTR Register

Segment Register

+

32 bits

16 bits

32 bits

32 bits


The Flat Memory Model

• GDT configured so that all segments start at physical address zero and have a size of 4GB.

• There's a one-to-one correspondence between physical addresses and the 32-bit offsets produced by effective address calculations.

• Memory looks like a single continuous space, called a linear address space.






I/O Port





Protected-Mode Addressing

EAXEBXECXEDXESIEDIEBPESPNone

EAXEBXECXEDXESIEDIEBPESPNone

EAXEBXECXEDXESIEDIEBPNone

EAXEBXECXEDXESIEDIEBPNone

1

2

3

4

1

2

3

4

None

8-bit

16-bit

32-bit

None

8-bit

16-bit

32-bit

++

Base Index Scale Factor

Displacement


Restrictions: MOV dst,src

• No more than 1 operand in memory.

• No more than 1 operand in a segment register.

• Only 8, 16, or 32 bit operands.

• Operand sizes must match (or else extend the length using MOVSX or MOVZX).

• If destination is a segment register, source cannot be an immediate constant.


Operand Sizes

May be implicit: INC EAX– Size of register EAX is 32 bits.

May be inferred: MOV AL,[EBX]– AL is 8 bits, so register EBX contains the address of

an 8-bit memory operand.

May be explicit: INC DWORD [EBX]– Ambiguous without “DWORD”!


Real Mode Defaults

• Address Field of Instructions is 16 bits– Precede instruction by 0x67 to use 32 bits:

DB 67HMOV AX,[BX]

• Operands are either 8 or 16 bits– Precede instruction by 0x66 to use 32 bits:

DB 66HMOV AX,[BX] Equivalent to MOV EAX,[BX]

Equivalent to MOV AX,[EBX]


Protected Mode Defaults

• Address Field of Instructions is 32 bits– Precede instruction by 0x67 to use 16 bits:

DB 67HMOV EAX,[EBX]

• Operands are either 8 or 32 bits– Precede instruction by 0x66 to use 16 bits:

DB 66HMOV EAX,[EBX]

Equivalent to MOV AX,[EBX]

Equivalent to MOV EAX,[BX]


16 vs. 32-bit Operands

Real Mode

Protected Mode

0101 0000PUSH AX

PUSH EAX

0110 01100101 0000

PUSH AX

PUSH EAX

Prefix Byte (66h)


16 vs. 32-bit Operands

Real Mode

Protected Mode

1011 1000MOV AX,imm16

(2 bytes follow)

MOV EAX,imm32

(4 bytes follow)

0110 01101011 1000

MOV AX,imm16

(2 bytes follow)

MOV EAX,imm32

(4 bytes follow)

Prefix Byte (66h)


16 vs. 32-bit Address Field

Real Mode

Protected Mode

1010 0001MOV AX,[mem16]

(2-byte adrs field)

MOV EAX,[mem32]

(4-byte adrs field)

0110 01111010 0001

MOV AX,[mem32]

(4-byte adrs field)

Prefix Byte (67h)

MOV EAX,[mem16]

(2-byte adrs field)


Data Movement Instructions

MOV dst,src ; dst src

LEA reg32,mem ; reg32 offset32 (mem)

MOVZX reg32,src ; reg32 zero extended src

MOVSX reg32,src ; reg32 sign extended src

XCHG dst,src ; temp dst

dst src

src temp


Stack InstructionsPUSH src16 ; ESP ESP-2, MEM[SS:ESP] src16

PUSH src32 ; ESP ESP-4, MEM[SS:ESP] src32

PUSHF ; ESP ESP-4, MEM[SS:ESP] EFlags

PUSHA ; Pushes EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI

POP dst16 ; dst16 MEM[SS:ESP], ESP ESP+2

POP dst32 ; dst32 MEM[SS:ESP], ESP ESP+4

POPF ; EFlags MEM[SS:ESP], ESP ESP+4

POPA ; Pops EDI, ESI, EBP, skip, EBX, EDX, ECX, EAX


Arithmetic Instructions

ADD dst,src

ADC dst,src

SUB dst,src

SBB dst,src

INC dst

DEC dst

NEG dst

MUL src ; unsigned

IMUL src ; signed

DIV src ; unsigned

IDIV src ; signed

CBW

CWD/CDQ

CMP dst,src


Extended Precision ADD/SUB

MOV EAX,[x]

ADD EAX,[y]

MOV [z],EAX

MOV EAX,[x+4]

ADC EAX,[y+4]

MOV [z+4],EAX

31 063 32

[x+4] [x]

31 063 32

[y+4] [y]

31 063 32

[z+4] [z]

MOV instructions have no effect on EFlags!


MUL & IMUL

Example Operation Product

MUL src8 AL src8 AX

MUL src16 AX src16 DX.AX

MUL src32 EAX src32 EDX.EAX


DIV & IDIV

Example Operation Quotient Remainder

DIV src8 AX src8 AL AH

DIV src16 DX.AX src16 AX DX

DIV src32 EDX.EAX src32 EAX EDX


CBW, CWD, & CDQ

Opcode Source Destination

CBW AL AX

CWD AX DX.AX

CDQ EAX EDX.EAX


Signed vs. Unsigned Division

unsigned int a, b, c ;…

a = b / c ;

MOV EAX,[b]

SUB EDX,EDX

DIV DWORD [c]

MOV [a],EAX

signed int a, b, c ;…

a = b / c ;

MOV EAX,[b]

CDQ

IDIV DWORD [c]

MOV [a],EAX


Bitwise Logical Instructions

AND dst,src ; dst dst & src

OR dst,src ; dst dst | src

XOR dst,src ; dst dst ^ src

NOT dst ; dst ~dst

TEST dst,src ; dst & src


Shift Instructions: opc dst,count

RCL:

ROL:

SAL:

SHL:

RCR:

ROR:

SAR:

SHR:

0

0 0


64-bit Logical Right Shift

63 32

[x+4]

CF

31 0

[x]

CF

Step #1:

Step #2:

SHR [X+4],1

RCR [X],1


Conditional Jump Instructions

Signed Tests:

JG/JNLE label

JGE/JNL label

JL/JNGE label

JLE/JNG label

Equality Tests:

JE/JZ label

JNE/JNZ label

Unsigned Tests:

JA/JNBE label

JAE/JNB label

JB/JNAE label

JBE/JNA label

Other Tests:

JC, JNC, JO, JNO, JS,

JNS, JPO, JNP, JECXZ


Other Jump Instructions

Unconditional:

JMP label

JMP regptr

JMP memptr

Loops (count in register ECX):

LOOP short-label

LOOPE/LOOPZ short-label

LOOPNE/LOOPNZ short-label

Copyright © 2000, Daniel W. Lewis. All Rights Reserved. CHAPTER 4 A PROGRAMMER'S VIEW OF COMPUTER ORGANIZATION.

Documents

memory memory data bus

main memory ldax slide

bus program

l2 slide

branch address slide

cpu instruction

b slide

single accumulator register