CHAPTER 1 CONVOLUTION IMPLEMENTED ON FPGA 1.1 Introduction The main aim of implementing convolution on FPGA is to design hardware that can reduce the convolution processing time and implement the discrete convolution of two finite length sequences (NXN). Many image processing operations such as scaling and rotation require resampling or convolution filtering for each pixel in image. Convolutions on digital images are important since they represent operations more general than the operations that can be performed on analog images. Filtering of signals is very important in order to determine which one to accept and which one to reject, and all of this is done by convolution. 1.2 Scope Implementation of discrete linear convolution for finite length sequences on FPGA kit, the purpose to prove the feasibility of an FPGA that performs a convolution on an acquired image in real time. is used in DSP applications. For example, it is used in image compression. The image compression takes place in 3 steps. Image consists of number of pixels. Each pixel is encoded in the first step. In the second step this encoded data will be transferred to the DWT (Discrete Wavelet Transform). The function of this DWT is to analyze the image means it tells how many lower order pixels and how many higher order pixels in the image. Compared to DFT, FFT, DWT having more accuracy. DWT consists of 1
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CHAPTER 1
CONVOLUTION IMPLEMENTED ON FPGA1.1 IntroductionThe main aim of implementing convolution on FPGA is to design hardware that can reduce the
convolution processing time and implement the discrete convolution of two finite length
sequences (NXN). Many image processing operations such as scaling and rotation require
resampling or convolution filtering for each pixel in image. Convolutions on digital images are
important since they represent operations more general than the operations that can be performed
on analog images. Filtering of signals is very important in order to determine which one to
accept and which one to reject, and all of this is done by convolution.
1.2 ScopeImplementation of discrete linear convolution for finite length sequences on FPGA kit, the
purpose to prove the feasibility of an FPGA that performs a convolution on an acquired image in
real time. is used in DSP applications. For example, it is used in image compression. The image
compression takes place in 3 steps. Image consists of number of pixels. Each pixel is encoded in
the first step. In the second step this encoded data will be transferred to the DWT (Discrete
Wavelet Transform). The function of this DWT is to analyze the image means it tells how many
lower order pixels and how many higher order pixels in the image. Compared to DFT, FFT,
DWT having more accuracy. DWT consists of filters. Pixels are analyzed by using these filters.
The DWT uses MAC unit. By using convolution, the operation of MAC unit is possible. In the
third step quantization will be done. By using this lower order pixels are quantized to zero. In
this way the image is compressed.
1.3 Technical ApproachSemicustom refers an integrated circuit that has been designed either by using existing blocks of
design elements or is made on an existing array of gates which are just connected together to
form a new circuit. Custom design means making for specific application. Pre-designed library
cells and routing and placing in semi custom technology. SPARTAN 2E FPGA kit having
XC2S100 device, TQ144 package with speed 5. SPARTAN2E having several features.
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Features of FPGA
The FPGA contains an on-board power supply and an on-board crystal oscillator for clock
pulses. The SPARTAN2E TQ144 package in FPGA has 15,000 to 100,000 gates. Some of the
features are ,On board reset software,20 user designable switches, four 7 segment displays,16
user definable LEDs, 4x4 keyboard, power indicator LED,I/O voltage configurability, user
hardware interface, slave serial/JTAG mode of configuration, compatible with all freely
available software’s
The proposed implementation uses a modified hierarchical design approach, Hardware
resources area significantly. The efficiency of the proposed convolution circuit is tested by
embedding it in a top level FPGA.
1.4 Literature SurveyThe most important operation performed on signals is linear filtering, which can be performed by
convolution. The reason that linear filtering is so important to signal processing is that it solves
many problems and is relatively simple to describe mathematically. Convolution helps to
determine the effect a system has on an input signal. It can be shown that a linear, time-invariant
system is completely characterized by its impulse response. Using the sampling property of the
delta function for continuous time signals and the unit sample for discrete time signals
decompose a signal into an infinite sum / integral of scaled and shifted impulses.
By knowing how a system affects a single impulse, and by understanding the way a
signal is comprised of scaled and summed impulses, it seems reasonable that it should be
possible to scale and sum the impulse responses of a system in order to determine what output
signal will results from a particular input. This is precisely what convolution does - convolution
determines the system's output from knowledge of the input and the system's impulse response.
The presented circuit uses less power consumption and delay from input to output. It also
provides the necessary modularity, expandability, and regularity to form different convolutions
for any number of bits.
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1.5 Software RequirementsSimulation purpose the modelsim software and for the synthesize purpose the Xilinx ISE 10.1
software are used. Simulation means compilation and verification of code will be done.
Synthesize means it will generate the gate level net list for the given code. For these software’s
we are using the VHDL language. A hardware description language is a language that describes
the hardware of digital systems in a textual form. It resembles a programming language, but is
specifically oriented to describing hardware structures and behavior. It can be used to represent
logic diagrams, boolean expressions, and other more complex digital circuits. HDL is used to
represent document digital systems in a form that can be ready by both humans and computers
and is suitable as an exchange language between designers.
There are two applications of HDL processing.
1. Simulation
2. Synthesis.
Logic simulation is the representation of the structure and behavior of a digital logic
system through the use of a computer. A simulator interprets the HDL description and produces
readable output, such as a timing diagram, that predicts how the hardware will behave before it is
actually fabricated, simulation allows the detection of functional errors in a design without having
to physically create the circuit. Errors that are detected during simulation can be created by
modifying the appropriate HDL statements.
Logic synthesis is the process of deriving a list of components and their interconnection
from the model of a digital system describing in HDL. The gate level net list can be used to
fabricate an integrated circuit. Logic synthesis is simulation to compiling a program in a
conventional high level language. Logic synthesis is based on formal exact procedures that
implement digital circuits and consists of that part of a digital design that can be automated with
computer software. In this project we used Xilinx ISE 10.1version for the synthesis purpose.
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1.6 Organization of ThesisTo design and implement the linear convolution on FPGA kit requires some hardware modules.
This can be explained in chapter2.
The linear convolution. Basically what is convolution and brief explanation of
convolution can be explained in chapter3.
For implementing linear convolution FPGA kit used. The FPGA technology can be
explained in chapter4. For simulation and synthesis some software’s must be used.
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CHAPTER 2
FPGA TECHNOLOGY2.1 IntroductionFixed-Logic Devices are the circuits in a fixed logic device are permanent, they perform one
function or set of functions - once manufactured, they cannot be changed. The time required to a
final manufacturing run can take from several months to more than a year, depending on the
complexity of the device. Programmable logic devices (PLDs) are standard that offer customers
a wide range of logic capacity, features, speed and these devices can be changed at any time to
perform any number of functions. During the design phase customers can change the circuitry as
often as they want until the design operates to their satisfaction.
SPLD (Simple PLD) is a programmable logic device that provides a small logic block
that can be programmed. The logic block typically contains a handful of macrocells, which have
multiple inputs and the ability to perform a limited amount of logic. Complex PLD consists of an
arrangement of multiple SPLD-like blocks on a single chip. These devices contain 10-1000
macrocells. Each macro cell is equivalent to around 20 gates support up to 200 I/O pins. CPLDs
provide logic capacity up to the equivalent of about 50 typical SPLD devices, but it is somewhat
difficult to extend these architectures to higher densities. For the very high logic capacity, a
different approach is needed that is FPGA (Field Programmable Gate Array).
FPGA is an integrated circuit that contains many identical logic cells that can be viewed
as standard components. Individual cells are interconnected by a matrix of wires and
programmable switches. Field programmable means that the FPGA’s function is defined by a
user’s program rather than by the manufacturer of the device or its function is defined by a
program written by someone other than the device manufacturer.
FPGA is fully programmable alternative to a customized chip. It is also called as
reconfigurable processing unit. FPGAs are great for more complex applications. It is a RAM-
based digital logic chip.
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2.2 Structure of FPGAA Field-programmable Gate Array(FPGA) is an integrated circuit designed to be configured by
the customer or designer after manufacturing—hence “field programmable".
Figure 2.1 Structure of FPGA.
The general structure of an FPGA is illustrated in above figure 2.1. The figure depicts the
essential elements of an FPGA organized as a 2-D array of cells. An FPGA consists of the
following main types of resources.
1. Rectangular array of configurable logic blocks (CLBs) capable of implementing a variety
of logic functions.
2. Wiring tracks to route signals between the cells.
3. Crossbar switches to connect horizontal and vertical wires, and
4. Input/Output pads for signal conditioning at the chip input and output pins.
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2.2.1 Configurable Logic Blocks (CLBs)
A major consideration in the selection of logic blocks is generality. The logic blocks are
generally arranged in a 2-D array.
Each logic block in a FPGA typically has a small number of inputs and one output. A
number of FPGA products are on a market, featuring different types of logic blocks. The most
commonly used logic block is a lookup table(LUT), which contains storage cells that are used to
implement a small logic function. Each cell is capable of holding a single logic value, either 0 or
1. The stored value is produced as the output of the storage cell. LUTs of various sizes may be
created, where the size is defined by the number of inputs.
Figure 2.2 Circuit for a Two-input LUT.
The above figure 2.2 has two inputs, x1 and x2, and one output f. It is capable of implementing
any logic function of two variables. Because a two-variable truth table has four rows, this LUT
has four storage cells. One cell corresponds to the output value in each row of the truth table. The
input variables x1 and x2 are used as the select inputs of the three multiplexers, which depends
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on the valuation of x1 and x2. Select the content of one of the four storage cells as the output of
the LUT.
2.2.2 Interconnects
The interconnection problem essentially consists of connection of two conductors together. All
internal connections are composed of metal segments with programmable switching points to
implement device routing. CLBs and I/Os are distributed on four sides of the blocks providing
additional routing flexibility.
These are three types. They are
1. Single length lines.
2. Double length lines.
3. Long lines.
1. Single length lines:
These are the grid of horizontal and vertical lines that intersects at a switch matrix between each
block. Its surrounds are CLBs in the array. Each switch matrix consists of programmable n-
channel pass transistors, used to establish the connection between the single length lines.
2. Double length lines:
These lines consist of a grid of metal segments twice as long as single length lines. These are
grouped in pair with the switch matrix.
3. Long lines:
The long lines form a grid of metal of interconnect segment that run the entire length or width of
the array.
2.2.3 Input/ Output Blocks
The input/output blocks provide the interface between external package pins and internal logic.
Each IOB controls are package pins and can be defined to I/O or bidirectional signals I/O are
programmable registers. Input signals are sent to the registers, output signals are passed directly
to the pad or be stored in an edge triggered flip-flop. Programmable pull up/pull down transistors
are useful for tying unwanted pins to Vcc and GND to minimize power consumption. Separate
input clock signals are provided for input and output registers.
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2.3 FPGA FlowThe basic implementation of design on FPGA has the following steps.
Design Entry
Logic Optimization
Technology Mapping
Placement
Routing
Programming Unit
Configured FPGA
Above shows the basic steps involved in implementation. The initial design entry of may
be VHDL, schematic or Boolean expression. The optimization of the Boolean expression will be
carried out by considering area or speed.
In technology mapping, the transformation of optimized Boolean expression to FPGA
logic blocks, that is said to be as Slices. Here area and delay optimization will be taken place.
During placement the algorithms are used to place each block in FPGA array. Assigning the
FPGA wire segments, which are programmable, to establish connections among FPGA blocks
through routing. The configuration of final chip is made in programming unit.
2.4 Advantages
The following are the advantages of the FPGA technology.
Reduced time to market.
Lower non-recurring engineering costs.
Reprogrammable.
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2.5 ApplicationsThe following are the applications of the FPGA technology.
FPGA can be applied to a very wide range of applications including: random logic,
integrating multiple SPLDs, device controllers, communication encoding and filtering,
small to medium sized with SRAM blocks.
Prototyping of designs later to be implemented in gate arrays. Prototyping might be
possible using only a single large FPGA (which corresponds to a small gate array in
terms of capacity).
Emulation of entire hardware systems.
2.6 Future ScopeIn this the 4x4 convolution and the data width is 4 bits shown. The convolution can be
done for NXN and the width can be extended to N bits.
2.7 ConclusionIn this chapter the basics of FPGA, structure of FPGA, advantages and applications of FPGA
are illestrated. The convolution process is explained in the next chapter 3.
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CHAPTER 3
CONVOLUTION3.1 IntroductionConvolution provides the mathematical framework for DSP. It is the single most important
technique in Digital Signal Processing. Convolution is a mathematical way of combining two
signals to form a third signal. Using the strategy of impulse decomposition, systems are
described by a signal called the impulse response. In signal processing, the impulse response, or
impulse response function (IRF), of a dynamic system is its output when presented with a brief
input signal, called an impulse. More generally, an impulse response refers to the reaction of any
dynamic system in response to some external change. It has applications that include statistics,
computer vision, image and signal processing, electrical engineering, and differential equations.
One of the most important concepts in Fourier theory, and in crystallography, is that of a
convolution.. Because of a mathematical property of the Fourier transform, referred to as the
convolution theorem, it is convenient to carry out calculations involving convolutions.
3.2 Convolution Definition
The convolution of ƒ and g is written ƒ∗g, using an asterisk or star. It is defined as the integral
of the product of the two functions after one is reversed and shifted. As such, it is a particular
kind of integral transform.
While the symbol t is used above, it need not represent the time domain. But in that context, the
convolution formula can be described as a weighted average of the function ƒ(τ) at the moment t
where the weighting is given by g(−τ) simply shifted by amount t. As t changes, the weighting
function emphasizes different parts of the input function.