Control Building Fiber Preliminary Design Review December 5, 2001.

Control Building Fiber Preliminary Design Review

December 5, 2001

IF Signal Path

ArrayTermination

Panel

I FPatch Panel

12 WDM per FIber

LOPatch Panel

M&CPatch Panel(TX & RX)

EmergencyCommunication

Patch Panel

TelephonePatch Panel

73 Fibers 73 Fibers 146 Fibers 73 Fibers 146 Fibers

Array FO TerminationRoom

North Arm FiberEntrance

(288 Fibersincl. spares)

East Arm FiberEntrance

(288 Fibersincl. spares)

West Arm FiberEntrance

(300 Fibersincl. spares)

E Array Option(180 Fibersincl. spares)

CB Main Distribution Frame

Cable Type Required

• Plenum Cable is required in the building

• 30-Fiber tight buffer cables will be used

Control BuildingMain Distribution Frame

MDF Components

Termination Panel

• 876 fibers• Provisions for 1200

Rack Mount EDFA

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Data Quality and Format Preliminary Design Review

December 5, 2001

Bit Error Rates

• Continuous On-Line Monitoring– Hardware and software – Part of Receiver– MCB access

• Error Flag Sent to the Correlator – Single threshold error flag

Transmitter Power

• Automated Test– Measured at Each Laser

• Manual Test– Can be measured at the Mux output– Can be measured at the output of the De-Mux

Optical Power

• Continuous Optical Power will be measured– 1% tap – The EDFA will measure the Optical Power– MCB access

• Total optical power is not a good indicator of BER

Eye Pattern

• Patch Panel– Manual measurements during reconfiguration

• Complete Diagnostic– Jitter– Q Factor– Noise Margin– Rise / Fall times

Test Patterns

• Generated at each Transmitter

• Nine Test Patterns– No Sync, alternating 1/0, all Ones, all Zeros

• MCB controlled

Frame Format

Frame Implementation

selector

32 bits

@

250 MHz

64 bitlatch

64 bitlatch

16 bit partioningand re-ordering

multiplexby 5

multiplexby 5

selector

multiplexby 16

16 Format bits@ 62.5 MHz

16 Format bits@ 62.5 MHz

64 bits@ 62.5 MHz

64 bits@ 62.5 MHz

80 bits@ 62.5 MHz

80 bits@ 62.5 MHz

16 bits@ 312.5 MHz

16 bits@ 312.5 MHz

16 bits@ 625 MHz

1 bit@ 10 GHz

160 bit Frames @10 GHz

Divided Sync Word

• Required to Identify Correct 1/2 Sequence

• 10 Bits long, – 6 bit identify Start-of-Frame– Barker Sequence - equal Ones versus Zeros

• Three Stage Synchronization Process

Three Stage Synchronization

• Stage 1 - Search bits for frame pattern

• Stage 2 – Monitor for “Correct” sync

• Stage 3 – If two “Bad” frames in a row

or 2-out-of-8 fames are “Bad”

Then Start Search Again

Scrambling

• Frame Synchronous Scrambling– Entire frame – except sync bits– Select pattern is modulo 2 added

• Pattern results in– Equal number of Ones/Zeros providing

• Balance ac content, sufficient transitions• Minimize low frequency content

Timing Signals

• Metaframe Index

• Metaframe count

• 1 PPS

• 1 Pulse per 10 seconds

Data Valid Signal

• Initiated at the antenna– Toggle Switch– MCB controlled

• Passed to correlator

Check Sum - BER

• Each 19 bits Generate a check Sum

• Only odd # of errors per 19 bits Detected

One error per frame is an

Error Rate of about 10-3

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