ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE Control And Readout Electronics For DNA Biosensor Arrays by Nicolas Huguenin-Virchaux in the LSM - Microelectronic Systems Laboratory Professor Yusuf Leblebici Supervisor Yuksel Temiz CoSupervisor Sevil Zeynep Temel June 2010
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Because the analog comparator is very sensitive to process variations, the gate length is
chosen to be three times larger than the minimal gate length. By doing this, the small
variations in the transistor dimensions have much less impact on the behavior of the
transistor. The model parameters are shown in Appendix C.1.
Biasing Circuit
The transistor NM3 has to be in strong inversion and saturation for a desired biasing
current of 10uA. The inversion factor is therefore chosen to be around 40 for very strong
inversion. The ratio can be calculated as:
(
W
L
)
NM3
=10µA
2 · nµCox · IF · U2t
≈ 1.54 ≈ 820
540
The transistor in the left branch, has a 10 times larger WL
ratio in order to conduct a
ten times larger current:
(
W
L
)
NM4
=100µA
2 · nµCox · IF · U2t
≈ 1.54 ≈ 8200
540
Chapter 4. Building Blocks in .18u Technology 17
The large width is divided up into 10 fingers to get a better aspect ratio2. The voltage
difference between vdd and the drain of NM4 is still relatively large. Therefore a high
resistor would be needed to generate a small current of 100uA. To reduce the high value
of the resistor and thus the layout size, an additional diode connected transistor is in-
serted. This transistor MN5 with the same dimensions as MN4 produces an additional
voltage drop and allows to decrease the resistor considerably by having the same current
100uA.
Comparator Circuit
The comparator function is implemented by the negative feedback transistor (NM1,
NM2) and the positive feedback transistors (PM1, PM2, PM3, PM4). The NMOS
transistors are also sized to operate in strong inversion and saturation, but this time the
current that flows through the transistors is only 5uA. The inversion factor IF is chosen
to be around 30, to get a nice ratio of:
(
W
L
)
NM1,NM2
=I02
2 · n · µ · Cox · IF · U2T
≈ 1 ≈ 720n
720n
The remaining PMOS positive feedback transistors (PF3, PF4, PF5, PF6)have to be
sized in order to get the desired feedback factor which in return defines the hysteresis
level 3.
Vth = V ref ±√
2 · n · IBias
β
(√k − 1√k + 1
)
Solving for k and considering a hysteresis of ∆ 250mV and βNM1,NM2 = KP · WL
defines
k as 3.35. this Feedback factor k is defined by the ratio of
k =W/LPM2
W/LPM1
=W/LPM3
W/LPM4
=2412/540
720/540= 3.35
. Simulation with these values and a reference at zero volt, makes the comparator switch
around ±118mV. Therefore the width W of PM2 and PM3 are slightly increased to get
switching later at ± 125mV.
k1 =W/LPM2
W/LPM1
=2620/540
720/540k2 =
W/LPM3
W/LPM4
=2680/540
720/540
2common method to reduce the aspect ratio of large transistors3lecture notes Analog 2, Prof.Maher Kayal, EPFL 2010
Chapter 4. Building Blocks in .18u Technology 18
The increase of the feedback factor (the width of PM2 and PM3) seems to be necessary,
because the bulk of the input differential pair cannot be connected to its source as it is
shown in the lecture notes4. For the layout the bulk of all NMOS transistors have to be
connected to the lowest potential (vss).
Output Stage
To get a rail to rail single ended output of the comparator, a special output stage is
needed consisting of the transistors PM5, PM6, NM6 and NM7. This output stage
provides reasonable voltage swing and output resistance. The chosen topology makes a
conversion from differential input to single ended output [5]. Because the load of the
comparator is not expected to be very large, the capacitive drive is not further increased
with an inverter chain. The transistor sizes of the output stage are chosen to be three
times larger then the minimum dimensions:
(
W
L
)
PM5,PM6,NM6,NM7
=720
540
The final dimensions in [nm] for the comparator are:
PM1 PM2 PM3 PM4 PM5 PM6 R
W 720 2620 2680 720 720 720 1000
L 540 540 540 540 540 540 3670
Table 4.1: PMOS Transistor Sizes for comparator
NM1 NM2 NM3 NM4 NM5 NM6 NM7
W 720 720 820 8200 8200 720 720
L 720 720 580 580 580 950 950
Table 4.2: NMOS Transistor Sizes for comparator
The simulation result of this comparator is shown in Appendix B.1.
4.2 3-level Comparator Block
Two of the above comparators are used to form a three level hysteretic comparator
Block. The upper comparator produces a signal D1, that rises to high, as soon as the
input exceeds the upper threshold at 250mV, and will be set back when the input voltage
reaches 0V again (lower threshold). Similar is the behavior of the lower comparator. If
4lecture notes: Analog 2 of Prof. Maher Kayal, EPFL 2010
Chapter 4. Building Blocks in .18u Technology 19
the input voltage decreases below -250mV the signal is going high, but as soon as it rises
above 0V it changes to low again (fig 3.4).
Figure 4.2
Figure 4.3: input outputtransfer characteristic of 3level hysteretic comparator
block
Unfortunately by applying the reference voltage ± 125mV to the comparators, the turn-
ing points change slightly due to unsymmetry of the circuit. It’s therefore necessary to
change again the sizes of the positive feedback resistor PM1, PM2, PM3 and PM4 for
the upper and the lower comparator. The final values after some simulations yields:
PM1 PM2 PM3 PM4
W 720 2570 2590 720
L 540 540 540 540
Table 4.3: comparator producing D1
PM1 PM2 PM3 PM4
W 720 2900 2650 720
L 540 540 540 540
Table 4.4: comparator producing D2
The simulation of the changed schematic with optimized transistor sizes shows the right
behavior for the signals D1 and D2. Those two signals will later be used to trigger the
reset of the integrator capacitor. Because the reset happens very fast, the comparators
will only produce very short pulses (spikes) at the output.
Chapter 4. Building Blocks in .18u Technology 20
Figure 4.4: Simulation results of 3 level Comparator Block
4.3 Sign Detection Block
Counting the number of these spikes in a fixed time window will provide just informa-
tion about the magnitude of the current. To make a decision about its direction, it
becomes necessary to make a distinction between spikes from each comparator output.
The simplest idea would be to use two counters, one for each comparator output. By
observing the total number of spikes from D1 and D2 it becomes possible to make a
decision about the direction of the current during that sampling interval.
ΣD1 > ΣD2: the current is negative
ΣD1 < ΣD2: the current is positive
ΣD1 = ΣD2: the current is 0 A
This implementation is not very efficient because two 10bit counters require a lot of
space. But by taking into account that the input current varies only slowly during one
sampling period, the problem can be simplified. In most of the samples, the spikes come
all from one comparator output while the other one does not produce spikes. Therefore
it’s no problem to sum up both spikes from D1 and D2 with the same counter. The
only problem arises when the current direction changes within a sampling period and
produces first spikes in one comparator, and then afterwards in the second. But this
case is very rare and occurs just in the zero crossing points of the voltogram (fig. 1.5).
Chapter 4. Building Blocks in .18u Technology 21
The idea of the simplification is to observe which comparator produced the first spike,
and to decide with this information the sign of the current. After that, all spikes re-
gardless of which comparator output, are summed up and provide the magnitude of the
current during that sample.
The following circuit is used to detect which comparator produced the first spike. The
D-FF, XOR and inverter where done using minimal dimension transistors because the
digital circuit is not that much sensitive to process variations. The schematic of the
D-FF is shown in Appendix A.3.
Figure 4.5: Edge detection circuit to sense the direction of the current
The two Delay FF and the XOR Gate form an edge detection circuit with output Q1
(Q2). This output will be reset after every sampling period with an active low signal.
The output Q1(Q2) goes high, when two conditions are fulfilled: the first spike comes
from D1(D2) and the other circuit has not detected a spike yet Q2N (Q1N).
The simulation results that where obtained explain the idea:
The current direction bits Q1 and Q2 are reset after every 300us with an active low reset
signal. Depending on the first spike (marker A or B) one of these two bits is set to high,
and prevents the other bit of going high in the same sample period as it is shown in the
period after the 4th reset.
4.4 Counter Block
Both comparator outputs are connected through an XOR-gate to the counter. This
10Bit counter detects all the spikes, regardless from which comparator they are coming
and will be reset after each sampling Period. The number of spikes is used to calculate
Chapter 4. Building Blocks in .18u Technology 22
Figure 4.6: Simulation of sign detection circuit
the magnitude of the sensor current during each sampling period. The counter is imple-
mented using 10 toggle flipflops with an active low reset. The schematic of the T-FF is
shown in Appendix A.4.
The Counter has been simulated to count up to 1000 and was then reset with an active
low RST signal at around 19ms. All the 10 output ports will be connected to the negated
output of its Toggle FF, to get a binary up counter.
Figure 4.7: Simulation result, counting up to 1000
Chapter 4. Building Blocks in .18u Technology 23
It’s important to note, that the reset signal puts the counter back into its initial state
[111...1] and the first spike will be denoted with output vector [000...0]. The number of
counted spikes is therefore always equal to the output of the counter +1.
Chapter 5
Layout
According to the project description, it was planned to draw the layout of the overall
system. But the migration from AMS.035 to UMC.18 Technology turned out to be very
time consuming. Because the schematics and layout of the FF are no longer available,
the layout of the sign detection block and counter was not done. For the final simulation
of the overall system, the schematic will be used instead for these missing blocks.
5.1 Layout Of The Comparator
Drawing the layout of the comparator required several trials and changes in the schematic.
The ideal resistor had to be changed into a real resistor (rnrhm1000 mm) from
UMC18 CMOS library. Then the biasing current mirror had to be sized properly with
a finger structure for the transistors NM4 and NM5. Also the input differential pair
transistors had to be changed with their bulk connection to vss. This made resizing of
the feedback transistors necessary. After solving these problems in the schematic the
layout was started. The transistors where arranged trying to keep the arrangement of
the schematic whenever possible. This allows the current to flow in one direction from
vdd to vss. Also the high current from the biasing circuit was put to the side like in
the schematic, in order not to interfere with the sensible comparator. The PMOS are
mostly on top near vdd and in the n-well, and the NMOS are more on the bottom near
the vss contacts. The layout was finally compressed as much as possible using minimal
distances between the metal lines, transistors, contacts, ...
24
Chapter 5. Layout 25
Figure 5.1: Layout after passing DRC check
Figure 5.2: Transistor placement
Figure 5.3: Extracted layout showing parasitic capacitances and resistors
Chapter 6
Simulation Results And
Discussion Of The Overall System
6.1 Putting It All Together
The overall system was put together using the extracted layout of the integrator op
amp1 and the 3 level comparator block. The other parts, such as sign detection block
and counter, where simulated using their schematic in place of the missing layout.
Figure 6.1: Final system showing all blocks
The final system in fig:6.1 has some minor changes compared to the schematic in chap-
ter3 fig:3.1. The six transistors in front of the op amp are necessary for the disconnection
of the WE from the readout electronics during the reset of the integrator. The disconnec-
tion of the WE happens when either D1, D2 or RST is high, thus building a connection
through one of the three parallel NMOS transistors to ground. In all other cases, the
path to ground is open, and the three serial NMOS switches are closed (D1∧D2∧RST )
1work of Gmel Gerrit, working on the same topic
26
Chapter 6. Results and Discussion 27
leading the current directly to the integrator. By applying this principle, the shorting
of the integrator capacitor, does not influence the working electrode.
6.1.1 Sizing Of The Reset Transistors
Another thing that had to be changed, was the size of the reset transistors for shorting
the capacitor. Using minimum dimensions provided first very disappointing results. The
reset happened too fast with an undershoot of nearly 100mV. The Comparator switched
then back to zero, and the next integration started from -100mV instead of zero volt.
Therefore the sizes had to be changed to around WL
= 240n2.3u
in order to increase the
resistance. The reasoning was, that the RC time constant should be increased so that
the reset takes more time, goes slower to 0V without a large (over)undershoot. This
resizing also helped to increase the pulse width of the comparator signals D1 and D2
from 30ns to 190ns. This was in fact considered an advantage, since the setup times of
the D-FF and T-FF where not checked. Simulation results where obtained for a 200pA
current, thus producing 2 spikes within the sampling window. A detailed zoom of the
spike at around ≈ 1.25ms is shown in Appendix B.2.
6.2 Simulation Results
Several simulations where performed using different input currents. Applying 100pA
should produce 1 spike in the 2.5ms time interval and defines also the resolution limit
of this architecture. Increasing the current should lead to proportionally more spikes.
This behavior was verified using multiples of Imin as it is shown in 6.2:
The behavior of the sign detection block is simulated by applying an input current that
changes from +700pA to -700pA within one sampling period. It is shown, that the first
spike coming from D1 sets Bit1 and prevents the other bit from going high in the same
sampling period until it is reset by the RST signal. In the second sampling period it’s
shown that the first spike coming from D2 sets Bit2 until it is again reset at 5ms. The
result of this simulation is shown in fig: 6.3.
Applying higher currents at the input was used to check if the counter is working and
if the accuracy of the overall system holds up to the expectations. Simulation with
1nA, corresponds to 10 times the minimal current Imin and produces 10 spikes. The
counter, which after the initial reset is in state [11...1] changes with the first spike into
[00...0]. For the next 9 spikes he is continueously incremented to 9, which is shown in
the simulation (fig. 6.4) by the waveforms [Q0, Q1, Q2, Q3].
Chapter 6. Results and Discussion 28
Figure 6.2: Simulation result of integrator voltage and comparator output for multi-ples of Imin [100pA, 200pA, 300pA, 400pA, 500pA] from bottom to top
Using the maximum current, produces a large number of peaks as shown int fig. 6.6.
By zooming in, it is shown, that the final values of the counter is not near to 1000. It
only shows someting around 768 with [Q0, ...Q9]= [1111111101].
The accuracy is therefor not quite satisfying. Due to the sizing of the reset transistors
(section 6.1.1) the error has increased. The reset time can not be ignored anymore for
high currents, and has to be included for the calculation and timing. If for example
1024 spikes where counted during the sampling period, then the overall reset time of
all spikes is about: ≈ 1024 · 350ns = 358.4µs which corresponds to approximately one
spike missing in the end of the sampling period, and an error of Imin. Another problem
concerns the accuracy of the 3 level comparator block. When tested seperetly, it worked
very accurate 4.4. But in the final system, the input waveform is different. Instead of
the triangular signal between vss and vdd, there is now a sawtooth input signal, that
barely crosses ±250mV . Simulating with Imin showed that the comparator switched
already at 248mV up and 0 V down. For Imax it switched at 250mV up and 2mV down.
Therefore the comparator behaves slightly different, depending on the input current
and its corresponding sawtooth signal Vint. These effects have to be included in for the
interpretation of the counter output.
Chapter 6. Results and Discussion 29
Figure 6.3: Simulation result of sign detection block using a changing input current
Figure 6.4: Simulation result of 1nA input current and 4 bits of counter
Chapter 6. Results and Discussion 30
Figure 6.5: Simulation result of 100nA, showing the ten bits of the counter
Figure 6.6: Simulation result of 100nA, showing the ten bits of the counter at 2.5ms
Chapter 7
Conclusion
The electrical interface for an electrochemical biosensor array was examined. Three
topologies where simulated using ideal components from .35µ design kit of Austria Mi-
crosystems. For the final implementation using the UMC.18 process technology, the
current to frequency conversion technique was chosen. This architecture was imple-
mented using only NMOS and PMOS transistors from SP 018 library. The layout of
opamp1 and comparator block was drawn. The final simulation results where obtained
using the extracted layouts of op amp and comparator block. The other parts such as
counter and sign detection block where simulated with the schematic.
7.1 What Remains To Be Done
Unfortunately, the intention to draw the layout of the overall system was too ambitious.
The sign detection block and counter layout will have to be done in a later step. Also
the error calculation and estimation could be done more seriously. So that the system is
more accurate for high currents. The timing of the reset phase and the exact switching
of the comparator will be necessary to get the best performance out of this architecture.
Very crucial for the performance will be the noise analysis. Since the application uses
very low frequencies, the 1fstarts to play an important role and begins to dominate over
the thermal noise. On a higher level, the sample points can be interpolated to get a
smooth voltogram curve. Time multiplexing of the different sensor cells can help to save
hardware space and power. Also the error that was introduced before by adding the
spikes from D1 and D2 with the same counter, might be further reduced by averiging
the sample point at the zero crossings of the voltogram.
1work of Gmel Gerrit, working on the same topic
31
Appendix A
Schematics
Figure A.1: Dual Slope Architecture proposed by Levine [1]
Figure A.2: Current to frequency conversion (bidirectional)
32
Appendix 1. schematics 33
Figure A.3: schematic for D-FF, from A-Cells library of Austria Microsystems)
Figure A.4: schematic of a T-FF, from A-Cells library of Austria Microsystems)
Appendix B
Simulation Results
Figure B.1: Simulation results of the Comparator with 250mV hysteresis andVref=0V
34
Appendix 2. parameters 35
Figure B.2: Comparison of reset transistors with minimal dimensions and optimizedvalues
Appendix C
UMC.18 Model Parameters
Figure C.1: Model parameters for UMC.18 process technology, source
36
Bibliography
[1] Peter M Levine, Student Member, Ping Gong, Rastislav Levicky,
and Kenneth L Shepard. Active CMOS Sensor Array for Elec-