F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/1 DESIGN OF CMOS ANALOG INTEGRATED CIRCUITS Franco Maloberti Integrated Microsistems Laboratory University of Pavia Continuous Time and Switched Capacitor Filters
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F. Maloberti
:
Design of CMOS Analog Integrated Circuits -
”Continuous Time and Switched Capacitor Filters” 8/1
D
ESIGN
OF
CMOS A
NALOG
I
NTEGRATED
C
IRCUITS
Franco Maloberti
Integrated Microsistems LaboratoryUniversity of Pavia
Continuous Time and SwitchedCapacitor Filters
F. Maloberti
:
Design of CMOS Analog Integrated Circuits -
”Continuous Time and Switched Capacitor Filters” 8/2
OUTLINE
Electrical Filters
Single op-amp realization
Cascade and multiple loop feedback
Switched capacitor technique
Biquadratic SC filters
SC N-path filters
Finite gain and bandwidth effects
Layout consideration
Noise
F. Maloberti
:
Design of CMOS Analog Integrated Circuits -
”Continuous Time and Switched Capacitor Filters” 8/3
ELECTRICAL FILTERS
Electrical filters is an interconnection network of electrical components which operates a modification of the frequency spectrum of an applied electrical signal.
The network is linear and time invariant.
F
ILTER
DESIGN
PROCEDURE
:
•
Filter specifications
•
Design of the network that implements the specifications
•
Component values evaluation
F. Maloberti
:
Design of CMOS Analog Integrated Circuits -
”Continuous Time and Switched Capacitor Filters” 8/4
Filter specification:
Is usually defined by a mask which specifies the range of allowed fre-quency responses.
The frequency range is divided into:
•
Pass band
•
Stop band
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Pass band Stop band
F. Maloberti
:
Design of CMOS Analog Integrated Circuits -
”Continuous Time and Switched Capacitor Filters” 8/5
Usually, they are specified:
•
Ripple in the pass band
•
Attenuation in the stop band
Specification of the phase response:
•
Usually linear phase response
Type of filters:
•
Low pass, low pass notch
•
High pass, high pass notch
•
Band pass, band reject
•
All pass
Φ f( ) k f f0–( )=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/6
Networks:
Filter specifications are met with linear networks which determine atransfer function of the form:
Pm(s) and Qn(s) are polynomial of order m and n respectively. The ze-ros of Pm(s) are the zeros of the transfer function. The zeros of Qn(s)are the poles of the transfer function. Always n ≥ m.
The number of poles gives the order of the filter.
• The ripple in the pass-band and the transition between the
stop-band and the pass-band determine the order of the filter
H s( )Pm s( )Qn s( )----------------=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/7
• Transmission zeros in the
stop-band help in getting
a sharper transition
• Very elementary specifications are met with first order or second
order filters.
First order:
Second order filter or biquadratic (biquad) filter:
|H||H|
f f
R
C
C
R
in out in out
LOW PASS HIGH PASS
HLP1
1 sRC+----------------------=
HHPsRC
1 sRC+----------------------=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/8
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/25
Design problem: group together pole and zero pairs (pole-zero pairing): it affects the dynamic range and the sensitivity.
Unfortunately there are not general and consistent rules for the pole-zero pairing in order to minimize the sensitivity.
Two opposite approaches are suggested in the literature:
• Pair the high-Q poles with far away zeros
• Pair the high-Q poles with closed zeros
The only solution is to try different pairing and to compare them with Monte Carlo analysis.
For order > 6 the cascade design is inherently more sensitive to component variation than multiple-loop feedback realizations.
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/26
MULTIPLE LOOP FEEDBACK REALIZATIONS
Several topologies:
• Follow the leader feedback (FLF)
• Inverse follow the leader (IFLF)
• Generalize follow the leader feedback (GFLF)
• Primary resonator block (PRB)
• Leapfrog feedback (LF)
• Modified leapfrog feedback (MLF)
• Coupled biquad (CB)
• Minimum sensitivity feedback(MSF)
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/27
LEAPFROG TOPOLOGY Simulate passive ladder networks, via signal flow graph
Vin
RS
C1 C3 C5
L2 L4
R6
I0
I4I2
V1 V3 V5 Vout
I6
I01
Rs------ Vin V1–( )=
V11
sC1---------- I0 I2–( )=
I21
sL2--------- V1 V3–( )=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/28
If we multiply each current by an arbitrary resistance R, we define new“dummy” voltage variables
V31
sC3---------- I2 I4–( )=
I41
sL4--------- V3 V5–( )=
V51
sC5---------- I4 I6–( )=
I61
R6-------V5=
Vout V5=
V0 RI0= V2 RI2= V4 RI4= V6 RI6=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/29
The equations becomes:
V0RRs------ Vin V1–( )=
V11
sRC1--------------- V0 V2–( )=
V2R
sL2--------- V1 V3–( )=
V31
sRC3--------------- V2 V4–( )=
V4R
sL4--------- V3 V5–( )=
V51
sRC5--------------- V4 V6–( )=
V6RR6-------V5=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/30
The original set of equations and the modified one can be repre-sented with the signal flow graphs:
1/Rs 1/sC1 1/sC3 1/sC51/sL2 1/sL4
+ _ + + +
+ _ + _ + _
1/R6
Vin V1 V5V3
I6I4I 2I0
R/Rs 1/s 1/s 1/s 1/s
+ _ + + _ +
+ _ + _ + _
R/R6
Vin V1 V5V3
V6V4V2Vs
t4t3 t51/s
___
t1 t1
_
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/31
Scaling of the flow graph:
Variable transformation Scaling by constants
1/sL2
+ _
_ +
V1 V3
I2
R/sL2
+ _
1/R +1/R
V1 V3
V2
1/sC3
1V3
I2
1/sRC3
V3
V2I4 V4+ _ + _
_ + _ +
_
1/s
1V3
V2
k/s
V3
V2V4 V4+1/k 1/k
_ + _ +
t3 t3
1/s
1V3
V2
1/s
V3
V2V4 V4+_
_ + _ +
t3 t3
+ _
+ _
_
_
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/32
The scaling of the flow graph is used in order to obtain realizable ac-tive implementations
• Inverting
integrators
• Inverters
• Summators
Interconnection ofsecond order loops(R ≈ Rs ≈ R6)
R/Rs 1/s 1/s 1/s 1/s
+ _ _ _ _ _ _
+ + + + + +
R/R6
Vin V1 V5V3
V6V4V2Vs
t1 t4t3 t51/s t2_ _ _ _ _ _
t1 t
2
t3 t
4
t5
1 1 1 1
1 1 1 1 1 1
1
-1 -1 -1
in
out
_ _
_ _
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/33
The scaling is also useful for dynamic range optimization:
V1 is too small
V2 is too high
Result: all the op-amp saturate (at different frequency) with the sameinput level.
Perform a SPICE simulation of the active (or passive) network in order to determine the scaling factors.
H1
Hout
H2
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f
Gai
n (d
B)
V1 K1V1→
V2 V1 K2⁄→
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/34
If the passive prototype has transmission zeros at the finite (elliptic filters), it hasthe form (low pass).
Before to describe the network and sketch the flow diagram it is worth to removethe bridging capacitors C2 and C4 through the use of the Thevenin’s theorem
Vin
RS
C1 C3 C5
L2 L4
R6
V1 V3 V5
Vout
C2 C4
C1 C3
L2V1 V3
C2
C1 + C2 C3 + C2
L2V1 V3
+ +
V3a1 V1a2
a1 =C2 /(C1 +C2 ) a2 =C2 /(C3 +C2 )
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/35
Similar modification follows if C4 is removed
The equations concerning the state variables V1, V3 and V5 change:
C1’ = C1 + C2
C3’ = C2 + C3 + C4
C5’ = C4 + C5
Vin
RS
C2+C3+C4
L2 L4
R6
V1 V3 V5 Vout
C1+C2
+
V3a1
C4+C5
+
V3a4a2
+
a1 =C2 /(C1+C2 ) a2 =C2 /(C3+C2)
a3 =C4 /(C3+C4 ) a4 =C4 /(C5 +C4)
V1+a3 V5
V11
sC ′1------------ Is I2–( )
V3C2
C1--------------+=
V31
sC ′3------------ I2 I4–( )
V1C2
C1 C3+--------------------
V5C4
C3 C4+--------------------+ +=
V51
sC ′5------------ I4 I6–( )
V3C4
C5--------------+=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/36
After scalings, aimed to the active realization:
R/Rs 1/s 1/s 1/s 1/s
+ _ _ _ _ _ _
+ + + + + +
R/R6
Vin V1V5
V3
V6V4V2Vs
t1 t4t3 t51/s t2_ _ _ _ _ _
t1
t2
t3 t
4
t5
1 1 1 1
1 1 1 1 1 1
1
-1 -1 -1
in
out
a1
a2
a3
a4
_ _
_ _
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/37
SWITCHED CAPACITOR TECHNIQUE
An active filter is made of op-amps, resistors and capacitors.
The accuracy of the filter is determined by the accuracy of the realized time costants since the capacitors and resitors are realized by uncorrelated technological steps
In CMOS technology ; ; hence , unacceptable for most of the applications
Hybrid realization with functional trimming
δττ-----
2 δRR
------- 2 δC
C-------
2+=
δR R⁄ 40%≈ δC C⁄ 30%≈ δττ----- 50%≈
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/38
Problems for a fully integrated realization• Accuracy
• Values of capacitors and resistors: for 70 nm oxide thickness 1 pF --
> 2000 µ2; 10 pF is a large capacitance. To get τ = 10-4 sec R = 107
Ω
The above problems are solved by the use of simulated resistorsmade of switches and capacitors.
MOS technology is suitable because:
Offset free switches
Good capacitors
Satisfactory op-amps
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/39
Simple SC structures
∆Q = C1 (V1 - V2) every ∆t = T
1
2
Φ1 2
I
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1
2
C1
C1
I
T
T
V1 V2
V1 V2
Φ
ΦΦ
Φ
Φ
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/40
The two SC structures are(on average) equivalent to a resistor
If the SC structures are used to get an equivalent time constant τeq = ReqC2it results:
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V1 V2
T
t
I
∆Q i∆tV1 V2–
R-------------------T= =
ReqT
C1-------=
τeq TC2
C1-------=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/41
• Its accuracy depends on the clock and on the capacitor matching
accuracy
• If τeq=40 T C2 = 40 C1 (acceptable spread) regardless of the value of τeq
A more complex SC structure:
The charge is transferred twice per clock period T or we assume asclock period half of the period of phases Φ1 and Φ2.
Φ1V1
Φ2
V2Φ2
Φ1
∆Q 2C1 V1 V2–( )=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/42
SC INTEGRATOR
Starting from the continuous-time circuit of the Integrator, we can ob-tain a SC integrator by replacing the continuous-time resistor with theequivalent resistances as follows:
+
_
R1
C2
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/43
Φ1 Φ2+
_
C1
C2
+
_
C1
C2
+
_
C2
C 1
Φ1
Φ1
Φ1
Φ2
Φ2
Φ2
Φ2
Φ1
Φ1
Φ1
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/44
We consider the samples of the input and of the output taken at the same times nT (the end of the sampling period).
• Structure 1:
taking the z-transform:
• Structure 2:
taking the z-transform:
Vout n 1+( )T[ ] Vout nT( )C1
C2-------Vin nT( )–=
Vout z( )Vin z( )-------------------
C1
C2------- 1
z 1–------------⋅–=
Vout n 1+( )T[ ] Vout nT( )C1
C2-------Vin n( 1 )T ]+–=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/45
• Structure 3:
taking the z-transform:
Remember that for the continuous-time integrator:
Comparing the sampled-data and continuous-time transfer functions we get:
Vout z( )Vin z( )-------------------
C1
C2------- z
z 1–------------⋅–=
Vout n 1+( )T[ ] Vout nT( )C1
C2------- Vin n 1+( )T[ ] Vin nT( )+ –=
Vout z( )Vin z( )-------------------
C1
C2------- z 1+
z 1–------------⋅–=
Vout s( )Vin s( )------------------- 1
sR1C2------------------–=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/46
• Structure 1:
FE approximation
• Structure 2:
BE approximation
• Structure 3:
Bilinear approximation
It does not exist a simple SC integrator which implement the LD approximation.
Note: the cascade of a FE integrator and a BE integrator is equivalent to the cascade of two LD integrators.
R1T
C1------- s
1T--- z 1–( )→→
R1T
C1------- s
1T--- z 1–( )
z-----------------→→
R1T
2C1---------- s
2T--- z 1–( )
z 1+( )-----------------→→
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/47
The key point is to introduce a full period delay from the input to the output
The same result is got with:
Φ1 Φ2
+
_
Φ2Φ1 +
_
C2
C1
C1
C2'
'
Φ1 Φ2
+
_Φ2 Φ1
+
_
C2
C1
C2
'
'
C1
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/48
STRAY INSENSITIVE STRUCTUREThe considered SC integrators are sensitive to parasitics.
Toggle structure:
• The top plate parasitic capacitance Ct,1
is in parallel with C1
• It is not negligible with respect to C1
and it is non linear
• The top plate parasitic capacitance Ct,1
acts as a toggle structure
Φ1 Φ2C1
Ct,1 Cb,1
Φ1
Φ2C1
Ct,1 Cb,1
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/49
Bilinear resistor:• Both the parasitic
capacitances Ct,1, Cb,1 act
as toggle structures. Their
values are different (of a
factor ≈ 10) and they are
non linear.
• Stray insensitivity can be
got for the first two
structures if one terminal is
switched between points at
the same voltage.
Φ1
Φ1
Φ2
Φ2
C1
Ct,1
Cb,1
C1
Φ1Φ2
Φ1Φ2
Virtualground
C1
Φ1Φ2
VirtualgroundΦ2
Φ1
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/50
• The right-side parasitic capacitor is switched between the virtual
ground and ground (note: even in DC Vv.g. must equal Vground)
• The left side capacitor is connected, during phase 1, to a voltage
(or equivalent) source.
• The charge injected into virtual ground is important, not the one
furnished by the input source.
• Structure A is equivalent to the toggle structure, but the injected
charge has opposite sign.
• Equivalent negative resistance allows to implement non inverting
integrators.
• It is possible to easily realize a stray insensitive bilinear resistor
with fully differential configuration.
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/51
SC BIQUADRATIC FILTERSConsider a (continuous-time) biquadratic transfer function
If the bilinear transformation is applied, it results a z-biquadratic trans-fer function
----------- IC IE GF– GB–+( )z2 FH BH BG JC– JE– IE–+ +( )z EJ BH–( )+ +
DB DF+( )z2 AC AE 2DB– DF–+( )z DB AE–( )+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------= =
H2
V0 2,Vin
----------- DIz2 AG DI– DJ–( )z DJ AH–( )+ +
DB DF+( )z2 AC AE 2DB– DF–+( )z DB AE–( )+ +-------------------------------------------------------------------------------------------------------------------------------------------= =
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/57
• Scaling for minimum total capacitance in the groups of
capacitors connected to the virtual ground of the op-amp1 and
the op-amp2.
• Since there are 9 conditions, one capacitor can be set equal to
zero
E = 0 “F type”
F = 0 “E type”
Firstly the 6 equations are satisfied. Later capacitors D and Aare adjusted in order to optimize the dynamic range. Finally allthe capacitor connected to the virtual ground of the op-amp arenormalized to the smaller of the group.
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/58
Scaling for minimum total capacitance
Assume that C3 is the smallest capacitance of the group. In order to makeminimum the total capacitance C3 must be reduced to the smallest value al-lowed by the technology (Cmin)
• Multiply all the capacitors of the group by
+
_
C2
C1
C3
C4
Cn
kCmin
C3------------=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/59
• All these design steps can be performed with a suitable computer
program
Equivalences for input structures:
G
H
G-H
H
G
H-G
G
for G>H
for G=H
for G<H
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/60
SC LADDER FILTERSOrchard’s observationDoubly-terminated LC ladder network that are designed to effect max-imum power transfer from source to load over the filter passband fea-ture very low sensitivities to value component variation.
Syntesis of SC Ladder Filters:
Symple approach
• Replace every resistance Ri in an active ladder structure with
a switched capacitor Ci = T/Ri.
• Use a full clock period delay along all the two integrator loop (it
results automatically verified in single ended schemes).
It results an LD equivalent, except for the terminations.
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/61
Quasi LD transformation:
Prewarp the specifications using sin(ωT/2)
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sin( pb T/2) sin( sb T/2)
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/62
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/66
Example: 5th order filter
Passive prototype
Flow diagram
SC implementa-tion
Vin
RS
C1 C3 C5
L2 L4
R6
IS
I4I2
V1 V3 V5 Vout
I6
R/Rs 1/s 1/s 1/s 1/s
+ _ _ _ _ _ _
+ + + + + +
R/R6
Vin V1 V5V3
V6V4V2Vs
τ1 τ4τ3 τ51/s τ2_ _ _ _ _ _
_
_ _
_+-
+-
+-
+-
+-
1 1
1
1 1 11 1
1
1 1
τ1T
τ3T
τ2T
τ4T
τ5T
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/67
EXACT DESIGN OF SC LADDER FILTERS A continuous-time network is exactly transformed into a sampled-
data network through the mapping z = exp(sT).
We can assume that an exact transformation is realized even through the LDI or the bilinear mapping, provided that the required pre-warping is made.
The exact LD design of ladder filter is not possible because of the error given by terminations.
The exact bilinear design is realizable through a suitable scaling.
Let us define the complex variables:
γ 12--- z1 2⁄ z 1 2⁄–
–( ) 12--- esT 2⁄ e sT 2⁄–
–( ) sT2---
sinh= = =
µ 12--- z1 2⁄ z 1 2⁄–
+( ) 12--- esT 2⁄ e sT 2⁄–
+( ) sT2---
cosh= = =
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/68
They are related by the relationships:
Note: the γ plane is the LDI plane and the λ plane is the bilinear plane (2/Tnormalized to 1)
To implement an exact LD equivalent s should be replaced by γ
To implement an exact bilinear equivalent s should be replaced by λ
Unfortunately, SC circuits having transfer function of the form 1/λ can not be realized in stray-insensitive form
Solution: suitable scaling of the ladder network (or equivalently the flow diagram): if we divide all impedance of a network by the same scaling factor, the transfer function remains unchanged
λ z 1–z 1+------------ z1 2⁄ z 1 2⁄–
–
z1 2⁄ z 1 2⁄–+
------------------------------- sT2---
tanh= = =
λ γ µ⁄= µ2 1 γ2+= z1 2⁄ µ γ+=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/69
Scaling of bilinear elements by µ:
Scaling changes:
• A resistor into a frequency dependent element
• A bilinear capacitor into an LD capacitor
• A bilinear inductance into parallel of L - LD inductance with a 1/L
- LD capacitor
RRµ----→
1λC------- 1
µλC-----------→ 1
γC-------=
λLλLµ------→ λµL
µ2---------- γL
1 γ2+
--------------- 11γL------ γ
L---+
----------------= = =
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/70
Consider a 5th order elliptic filter (bilinear)
After scaling by µ
Vin
RS
1/λC1 1/λC3 1/λC5
RL
Vout
1/λC2 1/λC4
λL2 λL4
Vin
RS/µ
1/λC1 1/λC3 1/λC5
λ/L2 λ/L4
RL/µ
Vout
1/λC2 1/λC4
L2 /γ L4 /γ
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/71
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/79
The z-transfer function of the N-path and the one of the low pass arethe same, but the sampling frequencies are one N times the other
The N-path filter realizes the transformation
In the transfer function of the low pass filter.
The gain requirement and the sensitivities are the one posed by the low-pass filter specifications
Implementation:
First order prototype:
zLP es NT( ) e( sT )N
zN= = =
z zN→
+
_
C2
C1
C
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/80
Parallel implementation:
Note that the op-amp work onlyduring a small period. They canbe multiplexed.
+
-
C2
C1
C
+
-
C2
C1
C
+
-
C2
C1
C
1
2
N N
2
1
Φ1
Φ2
ΦN
Φ3
+
-Φ1
Φ2
C2
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Φ
Φ
C(1)
C(2)
C(N)
Φ2
Φ3
Φ1
Φ
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/81
In order to have same LP transfer function all the integrating capaci-tors C(1), C(2), ..., C(n) must be matched. This requirement is over-came with the analog RAM-type scheme.
+
_
Φ1
C2
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ΦΝ
Φ
Φ
C
C
C
Φ'1
Φ
Φ1'
ΦΝ'
ΦΦ
Φ'1
Φ'2
Φ'2
Analog RAM
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/82
Or better:
Problem:Clock feedthrough noise appears at 1/TSolutions:
• Pseudo N-path with circulating memory
• Use of high-pass prototype and z –>z-N transformations
+
_Φ
C
ΦΦ
Φ
Φ Φ+
Φ
Φ
C
C
ΦN
Φ2
Φ3
Φ1
Φ
Φ2
Φ1
Analog RAM
C
C2
C1
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/83
FINITE GAIN AND BANDWIDTH EFFECT
If the op-amp has finite gain A0 the “virtual ground” voltage is V0/A0
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/86
Effect of the finite bandwidth:
+
_
C2
+
_
C2
C1
Coutgm vi gm vi
e-t/τ1e-t/τ
time time
inpulse response inpulse response
C2 =10 C1
τ 1ω0------ τ1 τ
C1 C2+
C2--------------------= =
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/87
Since the charge is injected when the capacitor C1 is connected to the virtual ground, during this phase the output will display a considerable transient.
During the phase when C1 is disconnected a residual transient is performed by the output. This transient does not correspond to any charge transfer into C2 (off course).
If T/2 is comparable with τ1 or τ2 we have two effects:
1 Incomplete charge
transfer
2 Virtual ground voltage
shift, which totally (in real
situations) disappears
during the successive
half clock period
Vout
timeAA
F1 F2
value before thechargeinjection
immediately after the closure of the switch
the virtual ground is not settled
error due to theincorrect charge transfer
ideal response
AA
Virtualgroundvoltage
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/88
• If we sample the output during Φ2 we have only a magnitude
error
• If we sample the output during Φ1 we have an additional voltage
error that will be “forgotten”. It corresponds to a phase error
For inverting and non inverting integrators:
+
_
C2
C1
Φ2Φ1
Φ2Φ1 Φ2
m ω( ) e
C2C1 C2+---------------------ω0T 2⁄–
1C2
C1 C2+-------------------- ωTcos–=
θ ω( ) e
C2C1 C2+---------------------ω0T 2⁄–
ωTsin=
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/89
Reduction of the finite gain effect:
The effect of the finite gain can be reduced with techniques based on principles that similar to the autozero used in comparators.
The virtual ground voltage must be sampled and held without changing the output voltage.
+
_
C2
C1
Φ2Φ1
Φ2 Φ1Φ2
m ω( ) 1C2
C1 C2+--------------------–
e
C2C1 C2+---------------------ω0T 2⁄–
=
θ ω( ) 0≅
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/90
During the S/H of the virtual ground voltage the integrating capacitor must be disconnected in order to preserve its stored charge.
A simple unity gain closed loop connection destroys the output dependent virtual ground voltage.
A slave capacitor Cs previously charged to the output voltage helps in solving the problem
+
_
C2
Φ2
Φ1
Φ1
Φ1
Φ2
+
_
C2
Φ2
Φ1
Φ1
Φ1
Cs
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/91
The output voltage changesonly of the global offset (if Cs isnot required to integrate chargeduring Φ2)
Three solutions:
Cs is required to discharge the injecting capacitor C1 to the global input offset.
Cs is required to discharge an extra-capacitor C2, which, during Φ1 acts as a battery, creating a virtual ground at the node N.
+
_
C2
Φ2
Φ1
Φ1
Φ1
Cs
Φ1 Φ2
C1
+
_
CI
Φ 1
Φ1
Φ1
C1
Φ2 Φ2
C2
Φ2
Φ1
N
Cs
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/92
The slave capacitor Cs is precharged at (Vout-Vin). During Φ2 if C1 = Cs the charge redistribution between C1 and Cs is such that Vout does not change.
Notes:
• The parasitic capacitance of the node A acts as a toggle SC
which inject charge into the small Cs during Φ2.
• Only inverting integrator
+
_
C2
Φ1
Φ1
Cs
Φ1
Φ2
C1
Φ1
Φ2
A
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/93
• Magnitude error is reflected into a frequency error
• Phase error is reflected into a Q error
Same circuit solutions can be applied do SC amplifiers andconverters.
Circuit Magnitude error Phase error
#1 ++ =
#2 = +
#3 = ++
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/94
FULLY DIFFERENTIAL CIRCUITS
Fully differential configurations reduce the clock feedthrough noise and increase the dynamic range.
They allow an increase design flexibility
Simple integrator (inverting and non inverting)
+
_
C2
C1
Φ1
Φ2Φ2
Φ1Φ2
(Φ2)
(Φ1)
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/95
Immediate sampling (inverting and non inverting) integrator:
Delayed sampling (inverting and non inverting) integrator:
Φ1
+
_
Φ1Φ2Φ2
Φ1Φ1Φ2Φ2
Vin
-Vin
-Vin
Vin
Φ1
Φ1
Φ1
+
_
Φ1Φ2Φ2
Φ1Φ1Φ2Φ2
Vin
-Vin
-Vin
VinΦ2
Φ2
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/96
It is possible to reduce the op-amp finite bandwidth dependence by the use of delayed sampling inverting and non inverting integrators along a second order loop.
Φ1
+
Φ1Φ2Φ2
Φ1Φ1Φ2Φ2
Φ2 Φ2
Φ2Φ2
Φ1 Φ1
Φ1 Φ1
+_
_
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/97
The peaking in the frequency response due to the phase error is strongly reduced
It is easy to realize bilinear integrators
Φ1
+
Φ1
Φ2
Φ1
Φ1 Φ2
Vin
Vin
Φ2
Φ2
C2C1
C2
C1
_
_
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/98
LAYOUT CONSIDERATIONS IN SC CIRCUITSA SC circuit is the interconnection of
• Op-amp
• Switches
• Capacitors
We have different lines of interconnections:• Signal
• Bias
• Clock
General rules:• Separate as far as possible, clock lines and signal lines
• Top plate of capacitors connected to virtual ground
• Maximum area switch and, when possible, only one transistor to
realize the switch (minimum clock feedthrough)
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/99
FLOOR PLANING FOR SINGLE ENDED CIRCUITS
Choose the dimension of the capacitor’s array in order to fit the op-amps dimension
Input and output of the op-amps in the proper position
CLOCKS
SWITCHES
CAPACITORS
SIGNAL + BIAS
OP-AMPS
BIAS
AN
AL
OG
DIG
ITA
L
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/100
FLOOR PLANING FOR DIFFERENTIAL CIRCUITS
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CLOCKS
SWITCHES
CAPACITORS
SIGNAL + BIAS
OP-AMPS
AN
AL
OG
DIG
ITA
L
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CLOCKS
SWITCHES
CAPACITORS
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/101
SWITCHES LAYOUT
CAPACITOR LAYOUT Use parallel connection of
unity capacitors
The residual capacitance must have the same perimeter/area ratio as the unity capacitors
Common centroid only if is effectively necessary
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A
AA
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AA
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A
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AA
AAAA
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/102
NOISE IN SC CIRCUITSThe noise sources in a SC network are:
• Clock feedthrough noise
• Noise coupled from power supply lines and substrate
• kT/C noise
• Noise generators of the op-amp
The first two sources are the same as in mixed analog-digital circuits.
kT/C noise:
Consider the simple network:
In the “on” state the switch can bemodeled with a noisy resitor
vin
CS1
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/103
Noise equivalent circuit:
The white spectrum of the “on” resistance is shaped by the low passaction of the RonC filter.The noise voltage across the capacitor C has spectrum:
4kTR fCS1
on
R on
Sn,c vn c,2 4kTRon H f( ) 2∆f
4kTRon∆f
1 2πfRonC( )2+
-----------------------------------------= = =
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/104
When the switch is turned “off” the noise voltage vn,c is sampled andheld onto C
The folding of the spectrum in band-base gives a white spectrum.AAAAA
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AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
f
S
fAAAAAAAAAAAA
AAAAAv n,c
f CK/2
*
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/105
It power (the dashed area) is equal to the integral of Sn,c
Procedure for the noise calculation in SC networks:
Assume all the noise sources uncorrelated
Neglect the direct coupling input-output
Consider, in the sampled-data domain, the contribution to the output of each noise source (SC structures + op-amps)
Superpose quadratically all the contributions
vn c,2 4kTRon∆f
1 2πfRonC( )2+
-----------------------------------------0
∞
∫ df4kT2πC----------- xatan( )0
∞ kTC-------= = =
F. Maloberti: Design of CMOS Analog Integrated Circuits - ”Continuous Time and Switched Capacitor Filters” 8/106