Conjoining Soft-Core FPGA Processors David Sheldon a , Rakesh Kumar b , Frank Vahid a* , Dean Tullsen b , Roman Lysecky c a Department of Computer Science and Engineering University of California, Riverside *Also with the Center for Embedded Computer Systems at UC Irvine b Department of Computer Science and Engineering University of California, San Diego c Department of Electrical and Computer Engineering University of Arizona This work was supported in part by the National Science Foundation, the Semiconductor Research Corporation, and by hardware and software donations from Xilinx
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Conjoining Soft-Core FPGA Processors David Sheldon a, Rakesh Kumar b, Frank Vahid a*, Dean Tullsen b, Roman Lysecky c a Department of Computer Science.
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Conjoining Soft-Core FPGA Processors
David Sheldona, Rakesh Kumarb, Frank Vahida*, Dean Tullsenb ,
Roman Lyseckyc
aDepartment of Computer Science and EngineeringUniversity of California, Riverside
*Also with the Center for Embedded Computer Systems at UC IrvinebDepartment of Computer Science and Engineering
University of California, San DiegocDepartment of Electrical and Computer Engineering
University of Arizona
This work was supported in part by the National Science Foundation, the Semiconductor Research Corporation, and by hardware and software
donations from Xilinx
David Sheldon, UC Riverside 2 of 22
FPGA Soft Core Processors
Soft-core Processor HDL description
Flexible implementation
FPGA or ASIC
Technology independent
HDLDescription
FPGA ASIC
Spartan 3Virtex 2 Virtex 4
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FPGA Soft Core Processors
Soft Core Processors can have configurable options Datapath units Cache Bus architecture
Current commercial FPGA Soft-Core Processors Xilinx Microblaze Altera Nios
FPGA
μP
Cache
FPU
MAC
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Conjoinment Overview
Base micro-processo
r FPU
Base micro-processo
rFPUFPU FPU
FPU
Application 1 Application 2
“Conjoining”
Add necessary units to both processors
Conjoin the FPU Unit Conjoined FPU unit
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Conjoinment Background Conjoinment proposed for multicore desktop processing (Kumar 2004) Reduces size with reasonable performance overhead
e.g., cache conjoinment overhead: 1%-13%
ICache Sharing DCache Sharing
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Outline Conjoinment for soft-core FPGA processors
Area savings
Performance overhead
Tuning heuristic for two configurable soft-cores with conjoin option
size
perf
?
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Area Savings
Significant potential area savings Limitations
Does not consider multiplexing costs Due to absence of FPGA synthesis tools supporting conjoinment
But good potential justifies further investigation
BaseMicroBlaze
Multiplier
Barrel ShifterDivider
FPU
Unit Size
Multiplier
Barrel Shifter
Divider
FPU
1331
228
122
2738
0
2000
4000
6000
8000
10000
bs div mul fpuUnit instantiated w ith base processor
Equivalent LUTs
unconjoined
conjoined
6% 4%23%
32%
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Outline Conjoinment for soft-core FPGA processors
Area savings
Performance overhead
Tuning heuristic for two configurable soft-cores with conjoin option
size
perf
?
David Sheldon, UC Riverside 9 of 22
Performance Overhead No simulator exists for conjoined processors We developed our own