Concept HDL Libraries Reference Product Version 14.2 January 2002 1997-2002 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 1-800-862-4522. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. This statement grants you permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used solely for personal, informational, and noncommercial purposes; 2. The publication may not be modified in any way; 3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement; and 4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be discontinued immediately upon written notice from Cadence. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.
222
Embed
Concept HDL Libraries Reference - Istituto Nazionale di ...statistics.roma2.infn.it/~sabene/CADENCE MANUALS/chdllref.pdf · Library Level Files ... Physical Part Table File Format
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Concept HDL Libraries Reference
Product Version 14.2January 2002
1997-2002 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.
Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA
Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in thisdocument are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks,contact the corporate legal department at the address shown above or call 1-800-862-4522.
All other trademarks are the property of their respective holders.
Restricted Print Permission: This publication is protected by copyright and any unauthorized use of thispublication may violate copyright, trademark, and other laws. Except as specified in this permission statement,this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, ordistributed in any way, without prior written permission from Cadence. This statement grants you permission toprint one (1) hard copy of this publication subject to the following conditions:
1. The publication may be used solely for personal, informational, and noncommercial purposes;2. The publication may not be modified in any way;3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other
proprietary notices and this permission statement; and4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be
discontinued immediately upon written notice from Cadence.
Disclaimer: Information in this publication is subject to change without notice and does not represent acommitment on the part of Cadence. The information contained herein is the proprietary and confidentialinformation of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customerin accordance with, a written agreement between Cadence and its customer. Except as may be explicitly setforth in such agreement, Cadence does not make, and expressly disclaims, any representations or warrantiesas to the completeness, accuracy or usefulness of the information contained in this document. Cadence doesnot warrant that use of such information will not infringe any third party rights, nor does Cadence assume anyliability for damages or costs of any kind that may result from use of such information.
Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth inFAR52.227-14 and DFAR252.227-7013 et seq. or its successor.
Cadence provides extensive digital libraries and simulation models for system designersusing the family of Electronic Design Automation (EDA) tools from Cadence. These librariessupport design entry, simulation, timing, test and physical layout - a complete front-to-backEDA solution for designing digital systems.
This guide describes how to maintain and modify the digital libraries. This manual is primarilyfor the system librarian who maintains, modifies, and creates libraries. This manual is alsouseful to system designers who use the digital libraries.
This guide assumes familiarity with a system text editor, HDL language concepts, and thefollowing Cadence tools used to create component symbols and models:
■ Concept-HDL, which lets you crete logic designs by drawing schematics using symbolsand functional blocks.
■ Packager-XL, which lets you prepare your schematic for PCB layout.
■ HDL Direct, which lets you create the netlist of your design.
■ PCB Librarian Expert, which lets you generate symbol and physical information(chips.prt) files.
Brief Outline of All the Chapters
Chapter 1, “Library Fundamentals,” covers the physical organization of libraries and the libcell view architecture in which the libraries are stored. This chapter also explains the librarylevel files and the category view of the libraries.
Chapter 2, “Development Decisions and Processes,” details the decisions that need to betaken while creating libraries and its components. This chapter also describes the processinvolved in the development of libraries.
Chapter 3, “Cadence Digital Library Standards,” covers the standards that should be followedwhile creating schematic part symbols and the standards used for symbols and physicalinformation or properties.
January 2002 17 Product Version 14.2
Concept HDL Libraries ReferencePreface
Chapter 7, “Reference Libraries,”covers the components of the reference libraries as suppliedby Cadence. These components are required by the Cadence tools to operate successfully.
Chapter 5, “Testing Libraries,” describes the tools provided by Cadence to test the librariesand components. The libraries and components need to be tested before being released toproduction to ensure that they work properly.
Chapter 4, “Simulation Views,” describes the need and use model of the Verilog wrappers.These wrappers are used for simulating the components.
Chapter 6, “Technology Independent Libraries,”covers the technology independent librariesthat are being released in the PSD 14.0 release. This chapter covers the library structure andthe method to access the components of the technology independent libraries.
Typographical conventions
This list describes the syntax conventions used for tools used in the Design Synchronizationprocess. Where applicable, exceptions to these conventions are explicitly indicated.literal (LITERAL) Nonitalic or (UPPERCASE) words indicate key words that you
must enter literally. These keywords represent command(function, routine) or option names.
argument Words in italics indicate user-defined arguments for which youmust substitute a value.
| Vertical bars (OR-bars) separate possible choices for a singleargument. They take precedence over any other character.
For example, command argument | argument
[ ] Brackets denote optional arguments. When used with OR-bars,they enclose a list of choices. You can choose one argumentfrom the list.
{ } Braces are used with OR-bars and enclose a list of choices. Youmust choose one argument from the list.
... Three dots (...) indicate that you can repeat the previousargument. If they are used with brackets, you can specify zero ormore arguments. If they are used without brackets, you mustspecify at least one argument, but you can specify more.
argument...: specify at least one argument, butmore are possible
[argument]...: you can specify zero or morearguments
January 2002 18 Product Version 14.2
Concept HDL Libraries ReferencePreface
,... A comma and three dots together indicate that if you specifymore than one argument, you must separate those arguments bycommas.
Courier font Indicates command line examples.
January 2002 19 Product Version 14.2
Concept HDL Libraries ReferencePreface
January 2002 20 Product Version 14.2
Concept HDL Libraries Reference
1Library Fundamentals
What is a library?
Libraries are a collection of parts that enable you to successfully design a schematic usingschematic editors such as Concept-HDL. The libraries consist of a collection of cells thatdescribe:
■ Components of a single design.
■ Components of the same technology or family. For example, lsttl.
■ Common components potentially used in many designs.
How is a library stored on the disk?
The libraries get installed during the time of the setup of the Cadence tools. By default, thelibraries get copied at <your_install_dir>/share/library. Each of the libraries arefurther organized into separate directories, one for each technology (for example, HCMOScomponents are in a directory called hcmos). Each library contains many subdirectories, one
for each of the parts (for example, hc00, hc02). Under each part, there are furthersubdirectories, such as entity, chips etc. which describes the part in a unique manner.
This structure is also know as the lib-cell-view architecture, where each of thesubdirectories, such as chips, entity etc. represent different views (schematic, symbolic andlayout) about the same part. Each of the views themselves contain files which store the actualinformation about the view. These files are fixed in both name and extension, or contain avariable portion controlled by the tools (for example, multisheet schematics). For example, thechips folder stores the chips.prt file which stores information like pin names andelectrical information for the part.
Lib-Cell-View Architecture
The libraries are based on a library-cell-view architecture. Each part (cell) has several views,each describing the part in a unique way.
The symbol view is the logical representation of a part in a Concept-HDL drawing. Each partcan have one or more symbol views that are in effect different versions of the logicalrepresentation. These different versions of the symbols are stored as sym_1, sym_2 and soforth. For example, sym_1 may describe the part as a single section, sym_2 may describethe part as a multisection part and sym_3 may store the DeMorgan view of the part.
For example, the figure below shows two versions of the LS377 part.
The first sym view usually shows only one representative section of a package. The secondsym view typically shows all the sections. (In the case of a simple gate, the second versionusually shows the DeMorgan equivalent of the gate.)
By default, Concept-HDL uses VERSION 1 of a symbol. You can, however, use the versioncommand in Concept-HDL to specify a different version of the symbol.
Note: This is the Cadence convention for defining symbol versions. You are not restricted tothese conventions.
Sizeable Body
Since all sections of the LS377 are identical, the first sym view can be used to represent
The VERSION 1 symbol of the LS377 is called a sizeable body. The drawing can be used torepresent multiple sections by using vectored signal names and attaching the SIZE propertyto the drawing (after it has been added to a Concept-HDL logic schematic).
Flat Symbol
The VERSION2 symbol of the LS377 shows all the logical pins of the part. This is called aflat symbol. This symbol resembles the physical package of an LS377. The LS377 packagecontains eight identical sections, and the VERSION 2 drawing shows eight input pins andeight output pins.
In most cases, the two body versions must have equivalent pin names. An exception to thisrule occurs in parts with asymmetrical sections. In this case, the versions of the part thatrepresent the different sections must have no identical pin names, so that you can distinguishthe different sections.
If a part has sections that are not interchangeable (such as the LS51), then there areadditional views that describe the additional sections. The following figure shows the differentsections of an LS51 component.
Some simple logic gates have versions (the DeMorgan equivalents) that represent the twodifferent logical functions performed by the gate depending on the polarity of the input signal.An LS08, for example, performs an AND operation on high-asserted signals or an ORoperation on low-asserted signals. Different versions of the LS08 allow a designer to addeither form of the gate to a drawing.
Package (chips) View
The package view or the chip view stores the package information like pin names andelectrical information for the part. This view connects the logical view of a component to itsphysical view.
The pin information like pin names, types, loading and physical numbers is stored in thechips.prt file located in chips directory.
Typical chips.prt file
FILE_TYPE=LIBRARY_PARTS;TIME=’COMPILATION ON THU JAN 10 14:52:02 1991’;primitive ‘74LS01’,’74LS01_DIP’;
This view contains the verilog.v file. This file contains the names of all the pins on thesymbol. This view is created when a symbol view is saved to the disk.
Simulation View
When a symbol view is saved to disk, an entity view is automatically created. In the entity viewis a verilog.v file that contains the names of all the pins on the symbol (known as amodule). The simulation view maps the symbol (or module) to a simulation model. The nameof the module is mapped to the name of the simulation model. The pin names in the moduleare mapped to the pin names in the simulation model. This file is sometimes called a‘wrapper’ because it contains mapping data only. The actual model is stored in an HDL modellibrary (for example, veriloglib).
During simulation, the verilog.v file in the schematic view is used as the netlist. Each partin this netlist has an entity and a simulation view.
Verilog-XL replaces the parts in the netlist with the simulation models as defined by thewrapper.
Part Table View
The part table view consists of .ptf files in the part table folder. Using this file, you cancustomize a part to fit your company needs. For example, you can add company part number,part description or any in-house or vendor information you require. A part_table view also letsyou override a property defined in the chips view. For example, you can override theJEDEC_TYPE property in the chips view with the name of another Allegro package symbolin your PCB library.
Map Views
The vlog_map, swift_map, and hw_map views have been added to the cells (whereapplicable) to support Vloglink style simulation. These views contain the verilog.map mapfile. The verilog.map file maps the signal names in the chips.prt file to the port namesin the Verilog HDL shell file (verilog.v). If you want to use Verilog-XL to simulate a design thatuses Concept symbols, you need to create a verilog.map file.
Following is the verilog.map file for the ls160 part in the lsttl library.
The PRIMITIVE section describes all the information related to a specific primitive. The nameused for the primitive is either the body name used in Concept-HDL or the part namegenerated by ValidCOMPILER using the PART_NAME property. For example, in the lsttllibrary, ls00 has a PART_NAME = 74LS00 property and, therefore, the primitive name is74LS00. The verilog.map file can contain different primitive sections for different primitivenames, for example:
Note that if there is a verilog.v file present under the hw_map view, it will be migrated tover_HW models directory created for that purpose under the vlog_model view (the cell namebeing the same except being case sensitive) as it is in the corresponding HDL library. Forexample, the cell i8086 becomes I8086 in the ver_HW models library.
A given cell view will always have exactly one master representation. When derivedrepresentations exist for a cell view, tools such as the edit server might need additionalinformation in the library to indicate which data is master and which data is derived. Themaster.tag file contains information about the physical file or files that represent the masterlogical file for any given view. This file is located in the view directory.
In some cases, a master representation may be split among more than one file. For example,different pages of a multi-sheet schematic may be saved in separate files, but all the pagestogether represent a single master representation. In this kind of situation, the master.tag filewill point to one of the files which is part of the master representation. For example, it mightpoint to the index sheet.
If the master.tag file is not present in the view directory, then the following rules are appliedto determine the master representation:
■ If there is only one file in the view directory, it is treated as the master representation.
■ Otherwise an error exists and the master cannot be determined.
The cds.lib File
When tools access library data, a library list is used to indicate the libraries that are accessibleto the tool and where they are located. This library list is present in the cds.lib file, whichis automatically created whenever any Cadence tool is installed. The cds.lib file present inthe Cadence installation hierarchy specifies the location of read-only libraries that areshipped with all installations of tools. This file is maintained by the installation procedures ofvarious tools.
The cds.lib file for the Cadence supplied ConceptHDL libraries is located in the followingdirectories:
your_install_dir/share/library/
This cds.lib file contains the list of all Concept-HDL libraries that are installed on yoursystem and defines logical library names and their physical storage locations.
Sample entries in the cds.lib file located at your_install_dir/share/library/DEFINE lsttl ./lsttl
DEFINE memory ./memory
DEFINE 54alsttl ./54alsttl
DEFINE 54fact ./54fact
The verbs used in the cds.lib file to specify the library list are DEFINE, UNDEFINE, ASSIGN,UNASSIGN, INCLUDE, and SOFTINCLUDE. Verbs are case insensitive. Keywords aredistinguished from library names and paths by their position in the syntax. <lib-name> andattribute names are interpreted in the file system name space, according to the Concept-HDLname mapping specification. This means that the identifier is case sensitive and has arestricted character set.
The following commands are defined:
COMMAND EXPLANATION
DEFINE <lib-name><directory>
Causes the logical library name <lib-name> to be definedwith the ordered list of directories specified in the<directory>. Any current definition of the <lib-name> isreplaced by the new definition. It is an error if the samephysical directory is contained in multiple libraryspecifications.
UNDEFINE <lib-name> Causes the library name <lib-name> to becomeundefined. It is not an error if lib-name is not previouslydefined. This command allows you to remove unneededlibraries from browser display when the libraries aredefined in another included library list file.
INCLUDE <filename> Causes the file <filename> to be read as a cds.lib file. Thefile is interpreted immediately and, except for pathnamesrelative to the cds.lib file, the semantics are identical tothose in the contents of the file. An error is generated if thefile cannot be accessed. It is also an error if recursion isdetected in INCLUDE files.
■ Use the pound sign (#) or the double hyphen ( -- ) to begin a comment. You must precedeand follow the comment character with white space, a tab, or a new line. Examples:
SOFTINCLUDE <filename> This is the same as the INCLUDE statement except thatno error or warning message is generated if the file cannotbe accessed.
ASSIGN <lib attribute path> Assigns an attribute to the library.
Note: TMP is the only attribute that is supported.
The following example defines the lsttl library andassigns the attribute TMP to the library defined as lsttl.The value of TMP is
./lsttl.
DEFINE lsttl ./lsttl
ASSIGN lsttl TMP ./lsttl
See "Binding One Library to Multiple Directories" formore details on TMP libraries.
UNASSIGN <lib attribute> Removes an assigned attribute from the library. No error isgenerated if the attribute has not been assigned to thelibrary. If the library has not been defined, an error isgenerated.
Note: TMP is the only attribute that is supported.
■ Keywords are identified as the first non-whitespace string on a line.
■ Keywords and attributes are case insensitive.
■ You can include symbolic variables (UNIX environment variables like $HOME and CSHextensions such as ~ and ~user). Symbolic variables and library path names are in thefile system domain and are case sensitive.
■ You can enter absolute or relative file paths. Relative paths are relative to the location ofthe file in which they occur, not to the directory where the tool was invoked.
Binding One Library to Multiple Directories
You can bind a library that you have defined in the cds.lib file to a temporary storage directoryby using the ASSIGN statement to assign the TMP attribute to the library. This allows multipledesigners to reference a shared library, but store intermediate objects generated by thecompiler or by the elaborator in separate design directories. When intermediate objects areread, the tools read whatever intermediate objects they need from the original library, and, ifthe objects are not in the original library, from the TMP library.
In the following example, a library called asic_lib is defined as ${PROJECT}/asic_lib. Atemporary storage directory called work/design_lib is created, and the TMP attribute isthen assigned to asic_lib to bind this library to the temporary storage directory.
# Define the shared library
DEFINE asic_lib ${PROJECT}/asic_lib
# Assign a temp storage directory
ASSIGN asic_lib TMP ./work/design_lib
When you compile and elaborate a design that includes design units from the shared library,all new intermediate objects are stored in the TMP library instead of in the asic_lib library.Only one directory can be bound to a master library using the TMP attribute. In the cds.lib file,you must define the library before you reference it with the ASSIGN statement. If thereferenced library has not been defined before the ASSIGN statement is processed, thestatement is ignored with a warning.
Use the UNASSIGN statement to remove the TMP attribute before compiling your designunits into the master library. Many design environments include a set of shared design
libraries that have had their file system permissions set to read-only so that only anauthorized user can add additional design units to, or delete or move, a shared library. Whenelaborating designs that include units from these read-only libraries, the elaborator may needto produce new intermediate files for a design unit that is in a read-only library. Using anexplicit TMP library (that is, one created by assigning the TMP attribute to a library) couldsolve this problem. However, using explicit TMP libraries not only requires you to add extralines to the cds.lib file, but also opens up the possibility that design units could be accidentallyrecompiled into the TMP library, perhaps masking the contents of the shared design library.
Library Level Files
There exists two other files at the same hierarchy as the individual libraries. They are the:
■ Category Files (.cat files) on page 32
■ “Physical Part Table File (.ptf file)” on page 32
Category Files (.cat files)
There often arises a need to classify the components of a library according to some attributeof the cell, such as BUFFER, CLOCK-DISTRIBUTION etc. These sub-classifications arecalled cell categories. A cell can be in any number of categories starting from no category.Cell categories are specified in category (.cat) files.IThis is an optional file.
Physical Part Table File (.ptf file)
The Physical Parts Table (.ptf) file stores the packaging properties for a part in the library. Thisfile contains information about parts such as package types, manufacturers, part numbersand any custom properties. Each physical part must have an entry in the .ptf file in order topackage properly.
Each cell in a library containing logical parts should have a corresponding .ptf file. You canplace all of these file in a single directory which will later be read by Packager-XL duringpackaging. You should maintain packaging information such as Allegro footprint(JEDEC_TYPE), VALUE, TOLERANCE, and PWR_RATING in this file.
In some cases, you may wish to automatically generate .ptf files from an existing MRP(Material-Resource-Planning) system. Preferred parts and user part information could beextracted and used for .ptf file creation. This would ensure accurate and current information.
January 2002 32 Product Version 14.2
Concept HDL Libraries Reference
2Development Decisions and Processes
Library Development Decisions
Before you create or modify libraries, you should make some decisions that are pertinent toyour site requirements. Following are some of the issues that you should resolve:
■ Are you developing mil spec components or standard components?
■ What body standards should you follow?
■ What is the minimum size for a body or the text included within a body?
■ What tools are you currently using?
■ What tools will you be using in the future: Simulator?
■ Should you save time by creating models now for tools you might use in the future?
■ Will designers be developing their own components or will the librarian be the onlydeveloper?
■ Will the librarian test designer-developed components?
■ The standards used in this manual are for commercial components.
■ If you are building ANSI library components, you should follow the ANSI/IEEE std91-1984.
■ What are the minimum test procedures for a completed component?
Library Development Process
As a librarian, you may need to create new libraries to support your development team.Cadence provides the PCB Librarian Expert tool that enables you to successfully create andmanage libraries. However, before PCB Librarian Expert is used to create libraries and parts,it is necessary to understand the steps involved in creation of a library with new parts. Theyare:
January 2002 33 Product Version 14.2
Concept HDL Libraries ReferenceDevelopment Decisions and Processes
1. Creating the symbol view. This involves following the Cadence standards for symbolswhile specifying the schematic part symbols. For more information see:
❑ Schematic Part Symbols on page 35
❑ Standards for Symbols on page 62
2. Creating the packages, i.e creating physical models. This involves creating thechips.prt file, the part table (.ptf) file and specifying the signal property in thechips.prt file. You should follow the Cadence standards for physical information whilecreating packages. For more information see:
❑ The Chips.prt File on page 43
❑ Part Table file on page 46
❑ Signal Property in Chips View on page 45
❑ Standards for Physical Information on page 64
3. Creating the Simulation views. This involves creating the Verilog and VHDL wrappersand map views. For more information, see:
❑ Simulation Views on page 67
When designing components, the librarian must make some decisions about how to assignvalues that are not specified in the data sheets. The librarian must decide what values to useand then maintain consistency for all components in the library. Such decisions should bedocumented in a file and placed in the directory so that other users of the library can readthem.
As a general rule, permissions on component models should be set so that only the librarianor root has the permission to change the models.
January 2002 34 Product Version 14.2
Concept HDL Libraries Reference
3Cadence Digital Library Standards
Overview
As a librarian, you will need to create new libraries and parts or edit existing ones. However,before you create or edit libraries, it is important to understand the schematic part symbolsand the standards used for symbols and physical information or properties. The use of thesestandards is important for the following reasons:
■ All user-generated components will be similar to those supplied by Cadence.
■ You will gain a quicker understanding of a component, because unique symbols are usedfor multiplexers, decoders, ALUs etc.
■ You can easily migrate from one technology to another without completely redoing theschematics.
Schematic Part Symbols
The libraries supplied by Cadence should be used whenever possible. These libraries includeconsistent schematic symbols and packaging data for many commercially available parts. Allof the included underlying information is available right out of the box.
Cadence symbols consist of several elements. They include a minimum of one symbol filecalled symbol.css, which contains the graphical symbol information. Another element ofCadence schematic symbols is the chips.prt file. This file contains the logical to physical pinmapping as well as other pin and part information.
Use Part Developer whenever possible to create new parts. The default settings can be setto create usable standardized symbols and chips.prt files. These symbols can be manuallymodified to suit designers’ preferences. Since the packaging information is automaticallycreated for you, Part Developer will give you an excellent start for most symbols.
The following factors should be addressed when planning schematic symbol standards.
■ Symbol Size on page 36
January 2002 35 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
■ Symbol Versions on page 36
■ Pin Stubs on page 37
■ Pin to Pin Spacing on page 38
■ Pin Bubbles on page 38
■ Pin Types on page 38
■ Pin Naming on page 39
■ Pin Notes on page 40
■ Symbol Notes on page 41
■ Properties on page 41
■ Symbol Naming on page 42
■ Bussed Pins on page 42
■ The Chips.prt File on page 43
■ Signal Property in Chips View on page 45
■ Part Table file on page 46
Symbol Size
Keep the overall symbol size as small as possible while still maintaining legibility. Make theparts with size in mind. The function of the part often dictates the size of the symbol. Try andavoid making smaller logical parts too large. It is very common to end up with a two-inch tallinverter which looks out of place on the schematic.
Use the display grid in Concept-HDL to determine the symbol size. Place all pins and pinstubs on the .100 inch display grid.
Note: Be careful, the snap grid is set to .050 inch in the Concept-HDL symbol editor.
Symbol Versions
Multiple versions of parts can be built to handle a variety of situations. Here are someexamples:
■ Creating horizontal and vertical versions of parts such as resistors and capacitors allowyou to avoid getting rotated property text when the parts are rotated.
January 2002 36 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Rather than rotating symbols, use alternate versions of the symbol. These alternateversions have property placeholders placed right reading and in the ideal text locations.
■ You can use multiple schematic symbols to represent a single part.
This is often the case with analog op- amps and other such parts. Each gate has aunique look and must be built separately.
■ You can functionally break out sectioned parts or parts too big to be built into one symbolinto several symbols, and package these into one device.
■ You can create different versions to enable vectored pins in one version and non-vectored pins in another.
■ You can create aesthetically different parts for functional reasons.
Test points and connector symbols can have multiple versions which represent the samepart. They can appear differently to differentiate signal direction or connector type.
■ You can create versions of DeMorgan equivalent parts to aid in part placement and toprovide correct bubbling capabilities.
Pin Stubs
Draw pin stubs .100 inch long on rectangular parts using a .100 inch visible grid. Leaving thestubs .100 inch long provides a reasonable place for the pin number annotation to appear.When the stubs are longer than .100 inch, the pin numbers appear too far away from thesymbol and look out of place.
If pin stubs utilize the ANSI standard graphic formats, longer pin stubs may be required. Keepthem as short as possible.
Draw low asserted pins with .100 inch diameter circles rather than straight-line pin stubs.When using the BUBBLE property, both graphic pin representations may be required.
Analog and odd-shaped parts should have reasonable pin stubs based on their appearance.
In most cases the default pin number locations should be adequate. The location where thepin number is to be annotated on the schematic can be preset within the symbol by placinga $PN property placeholder on each pin. The value of that property should be a questionmark (?) for a visible number or pound sign (#) for an invisible number. Verify that the text sizeof the placeholder is consistent with the design standard. Also check that the text justificationis set to right for pins on the left side of the part and left for pins on the right.
When the Concept-HDL default setup is used, vertical pin stubs result in vertical pin numbers.
January 2002 37 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Pin to Pin Spacing
Establishing a minimum pin to pin space can help eliminate crowded or off-grid pins andprovides consistent readable schematics. Use the schematic wire to wire spacing minimumas the minimum pin spacing as well.
Pin spacing on bodies should be a minimum of .100 inch and should be placed on a .100 inchgrid. This spacing appears quite readable when plotted at or close to 1X scale. If theschematics get scaled in half, a .200 inch pin spacing standard should be implemented.When editing bodies in Concept-HDL, the default snap grid is .05 inch, but the visible grid is.100 inch. Pins should be placed on visible grids only. Try plotting some example sizesincluded in the supplied Cadence library parts as a baseline to see the difference clearly.
Cadence libraries are shipped with a default pin spacing of .100 inch. The client may desirea larger spacing than the one shipped in the Cadence libraries. Rather than scaling all of thesymbols in the library, you can scale the drawing formats down by a proportional amount. Youcan then plot the schematics at an increased scale to get the desired drawing size and pinspacing. You have to consider text and component size when using this approach.
Pin Bubbles
Use the BUBBLE and BUBBLE_GROUP properties for tracking and checking signal statesand circuit behavior. The pins need to be bubbled correctly while they are being designed inConcept-HDL. Symbols that are built correctly should not cause any problems and shouldsuccessfully complete the design integrity checks within Concept-HDL. These properties alsoprovide for much more readable designs when looked at logically.
Cadence libraries include the DeMorgan equivalent parts as alternate symbol versions.When placing parts, the correct symbol should be used to establish signal states and toprovide design integrity. You can use the bubble command in Concept-HDL to toggle thesignal states on pins.
Pin Types
Designate the pin types and add pin loading information in Part Developer. This informationgets stored in the chips.prt file and is crucial for some Concept-HDL integrity checks andlayout analysis with SigNoise. Signal noise analysis uses the pin type and loading informationto accurately model the behavior of components.
The information can also be input manually into the chips.prt file by using a text editor.However, this requires you to be aware of the syntax and file format.
January 2002 38 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Whenever appropriate the input pins should be placed on the left side of the symbol withoutputs on the right.
Pin Naming
Pins should be designated with functional names. Each pin name must be unique to thatsymbol and must have a matching entry in the chips.prt file. Concept-HDL supports thethe following as valid pin names:
■ alphanumeric characters
■ numbers, but only for scalar pins
■ -
■ #
■ $
■ %
■ +
■ =
■ |
■ ?
■ ^
■ _
■ .
■ (
■ )
Caution
For pins that have ( or ) in their names, hlibftb reports errors if yourun verification checks from within Part Developer. However, you can usesuch pins in Concept HDL schematics by turning off themulti_format_vector option off. Because of this reason, it issuggested that you do not use ( or ) in pin names.
The following are not valid for pin names:
January 2002 39 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
■ All extended character sets
■ /
■ ;
■ !
■ <
■ >
■ :
■ \
■ ”
■ ,
■ *
When creating parts manually, place the SIG_NAME properties outside the symbol, next tothe pin it is attached to. Text size is not too important on these properties since they are notdisplayed on the schematic.
Follow low asserted pin names with an asterisk (*) (for example, OE*) or _N (for exampleOE_N). Do not differentiate low asserted pins with any other nomenclature. All low assertedpins should appear as bubbles and not straight pin stubs.
Pin Notes
Pin notes are used for graphical identification of pins only. In most cases, they should beplaced inside the symbol outline. The minimum text size of pin notes should be .08 inch andthey should appear next to the pin they represent. The names should accurately identify thepin functions, while remaining as short as possible. The text size should be consistent withinthe part and throughout the library.
Use the attribute command in Concept-HDL to properly set the text justification. For bestalignment, set the right side and top notes as right justified and left side and bottom notes asleft justified.
Vertical pins may be labeled with vertical text, but when possible, keep the pin note horizontaland right reading.
Low asserted pins shown with a bubbled pin stub should be labeled with a simple signal name(for example, OE). Do not use *, _L, _ or any other low asserted nomenclature in the pin note.
January 2002 40 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
The bubble alone differentiates this pin as low asserted. Adding another low asserted calloutcauses a double negative situation.
Note: Dual-purpose pins are the exception.
Symbol Notes
The functional part name should be placed inside the symbol when appropriate foridentification purposes. Make the text size large enough to be easily read. A recommendedtext size is .125 inches. Place any note text that aids in part identification on the part. Do notadd any unique package nomenclature such as a user internal part number or speed.
Properties
During the course of the design, several properties usually get annotated to each symbol toaid in simulation and packaging. By default, these properties get annotated in randomlocations on the part. To provide for a more readable schematic, place property placeholdersin the symbol bodies for each key property in the Physical Part Table file (.ptf). Theseplaceholders provide locations to annotate properties when placing parts in Concept-HDL inthe physical mode. Defining these placeholders in the bodies provides for much neaterschematics initially and avoids tedious property manipulation after placement.
You can control the text size and visibility by setting them properly on the placeholder. Simplyplace a property such as $PART_NUMBER on the symbol origin with a value of “?”. You canset the text location, justification and size on the “?”. The “?” will make the annotated propertyappear visible on the schematic when the part is placed. If you prefer the property to appearinvisible, make the “?” invisible in the symbol file.
Ensure that visible properties are placed outside the symbol body. This is because, when thesymbol is instantiated in the schematic, Concept-HDL aligns any instance specific propertiesthat are added with the visible properties. If a visible property is placed on the symbol body,instance specific properties that are added will overlap the symbol.
The dollar sign ($) ensures that the property is initially defined as soft. A property name withno dollar sign ($) sign differentiates it as a hard property. To avoid errors, all hard propertiesmust be defined in Concept-HDL prior to saving. Soft properties allow you to save Concept-HDL schematics without defining values for these properties. The part specifics may not beknown when entering the schematic. All part property placeholders should be defined as softproperties with a dollar sign ($).
Some properties commonly placed in symbols are
■ PART_NUMBER: Used for user or vendor part numbers
January 2002 41 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
■ PACK_TYPE: Used to specify package (DIP, SOIC, LCC, and so forth)
■ LOCATION: Used to specify reference designator
■ VALUE, $TOLERANCE, $PWR_RATING, $VOLTAGE etc.: Used to specify discrete partproperties
For some discrete devices such as resistors and capacitors, you may wish to make the pinnumbers appear invisible on the schematic. This is easily accomplished by placing a $PN=#property on each of the wire pin stubs in the symbol file. When the design getsbackannotated, these properties are invisible and do not clutter up the schematic.
Locate a position for each property that looks best on the schematic. Keep in mind that aminimum overall symbol size will free up room on the schematic.
Symbol Naming
When creating parts, a vendor or common (functional) part name should be used whereverpossible. Some systems require a unique part for each representation of that part. Concept-HDL has the ability to use the same logical symbol for each exact representation of a part.This eliminates having individual symbol copies available for each unique part. (For example,when you use the name LS00 as the symbol name.) Various package types and vendors canbe entered into the .ptf file along with the user internal part numbers and any other criticalpart data. Symbol names are of 0.6 Concept size or more, proportional to the size of the body(1 Concept size = 0.072 inch).
Avoid using user internal part numbers when naming symbols. Use a functional name thatwill be easier to find when scanning libraries.
Bussed Pins
Vectored pins are allowed within the Cadence libraries. These single pins represent multiplebus signals. (For example, A<7..0> represents eight bits of the A bus.) The drawback to usingthese pins is that they do not get annotated with pin numbers during packaging. The systemkeeps track of the pin numbers, but they cannot be displayed on the schematic for the finaldocumentation.
Use the option of placing schematic notes when final documentation schematics arerequired. Whenever possible, break out bussed pins into individual pins.
Always label these pins in descending bit syntax (7..0 instead of 0..7) since this is howConcept-HDL understands significant bit ordering. You could label these pins in the reverseorder as long as you are consistent with labeling. Cadence libraries are labeled in the
January 2002 42 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
descending order, preventing them from use with ascending numbered designs. Thisdecision on labeling order must be made before creating any vectored pin parts.
The Chips.prt File
A Typical chips.prt File
The chips.prt file contains three parts
Chips.prt Section Description
Header This line begins the chips.prt file by declaring the file type. Achips.prt file always starts with theFILE_TYPE=LIBRARY_PARTS statement.
FILE_TYPE=LIBRARY_PARTS;
TIME=’COMPILATION ON THU JAN 10 14:52:02 1991’;primitive ‘74LS01’,’74LS01_DIP’;
Concept HDL Libraries ReferenceCadence Digital Library Standards
A generic default part name is assigned in the primitive line of this file. This name is what issearched for in the .ptf file and during simulation. The PART_NAME property in the bodysection of the file should reference this generic name. For example, the LS00 part shouldhave a PART_NAME and primitive defined as 74LS00.
The pin section defines the logical to physical pin mapping. The pin information included inthis file are pin names, types, loading and physical numbers. The names must match thenames in the Concept-HDL body file. The pins which were defined as low asserted in thebody with an asterisk (*) have a hyphen (-) character prepended to the name in thechips.prt file (for example, OE* in the body is -OE in the chips.prt file).
Vectored pins should be broken out if possible. This alleviates the possible confusion whenmatching up logical bus bits with physical pins. When assigning physical pin numbers tovectored pins, always enter them in the ascending order regardless of the way the pin nameis labeled. For example, a pin named A<31..0> would start with the physical pin for the 0 bit.
The pin type affects the pin’s position on the symbol. The pin type also affects the assignmentof IO and load checking properties in the chip.prt file. If the pin is an input pin, PartDeveloper assigns the INPUT_LOAD property to the pin. If the pin is of the type output, thenPart Developer assigns the OUTPUT_LOAD property to the pin. In case of an output pin tobe treated as open-collector, open-emitter or tri-state, Part Developer assigns theOUTPUT_TYPE property to it. While packaging and sectioning use physical number, someConcept-HDL design integrity checks and SigNoise signal integrity analysis use the type andloading information. Make every effort to find and include the pin information in each part built.Be sure to enter the appropriate information for each package type since the information mayvary.
Each unique package type (PACK_TYPE) requires an entry in this file. You can includepackage types with identical pin mapping in one entry.
For example, the LS00 part has identical pin mapping for the DIP and SOIC packages. Theprimitive statement should appear as 74LS00, 74LS00_DIP, and 74LS00_SOIC. Acompletely separate primitive and part entry is required for the LCC version of that part sinceit has a different pin mapping.
Primitive A primitive is the description of the physical part. A chips.prtusually contains several primitives. Within the primitive are thepin and the body sections.
End This line completes the chips.prt section.
Chips.prt Section Description
January 2002 44 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Use the <partname>_PACK_TYPE naming convention since Concept-HDL and Packager-XL understand this convention. The .ptf file for this part should have a key property calledPACK_TYPE with DIP, SOIC and LCC entries. For more details on the .ptf files, see Part Tablefile on page 46.
If a PART_NAME property is placed in the chips.prt file, it must have a matching primitiveentry. Failing to have this condition causes packaging errors.
The JEDEC_TYPE property maps the Concept symbol to the Allegro package symbol. Thisproperty is the link between Concept and Allegro libraries.
The BODY_NAME property has the same value as the cell name. Packager uses thisproperty to create a backannotate file (pstback.dat).Archiver reads a schematic designand copies the library files into an archive library (so it can be stored with the design). TheArchiver uses the BODY_NAME property in the chips.prt file to locate a reference cell.
When this property is not defined in the chips.prt file, Packager and Archiver will use thePART_NAME property instead.
For technology dependent libraries, cell and part names are the same. For example, the cellname is 74LVT574 and so is the part name. Therefore, the BODY_NAME property is notneeded.
For technology independent libraries, cell and part names will not be the same. For example,the cell name is 574 and the part name is 74LVT574. Therefore in these cases, theBODY_NAME property will be needed.
In summary, the chips.prt file contains physical pin numbers and pin information. Makesure you verify the completed file against the vendor specification before making the partavailable to designers. Since this involves manually inputting data from a paper specification,this is the most probable area for errors to surface. You should always double-check for errors.
Comments in the chips.prt File
You can add comments in the chips.prt file by entering the text between { and }.
Signal Property in Chips View
The chips.prt file has an additional property -- the signal model property -- which gives ita default association with the Signal Integrity device model.
January 2002 45 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
In the absence of any Signal Integrity device model, and an annotation with a part in theschematic, the default signal model gets associated. This would allow designers to test thedesign at the backend for signal integrity with the Analysis tool.
Each primitive section in chips.prt will have the additional property of chips.prt,provided the default signal model exists in the Signal Library (provided by Zeelan). Theproperty also indicates a default manufacturer of the device for which the Signal Integritymodel was developed.
It has to be noted that no such property would exist in the absence of a model for that part inthe Zeelan Library.
An example of the chips.prt section having the signal model property body is given below:
POWER_PINS='(VCC:14;GND:7)';
FAMILY='LSTTL';
PART_NAME='74LS00';
BODY_NAME='LS00';
DEFAULT_SIGNAL_MODEL='SN74LS00D TI';
JEDEC_TYPE='SOIC14';
CLASS='IC';
TECH='74LS';
end_body;
Part Table file
The Physical Parts Table (.ptf) file stores the packaging properties for a part in the library. Thisfile contains information about parts such as package types, manufacturers, part numbersand any custom properties. Each physical part must have an entry in the .ptf file in order topackage properly.
January 2002 46 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
For example, displayed below is a typical entry from a .ptf file
In the above part table file:
■ A unique part number is assigned based on package style.
■ An Allegro package symbol name is assigned based on package style.
Note: The JEDEC_TYPE property may also be defined in the chips.prt file. However, thepart_table view has the priority.
■ A part description is added
The PACK_TYPE property is a key property (its’s on the left hand side of the equal sign). Thisimplies that every 74LVT574 in the schematic must have the PACK_TYPE property assigned.However, if an 74LVT574 is found that does not have a PACK_TYPE property value of eitherDIP, SOIC or LCC, the Packager will abort. To set a default PACK_TYPE value, use the OPTstatement as follows:
When a 74LVT574 part in the schematic fits the key property description (has a PACK_TYPEproperty value of either DIP, SOIC or LCC), then the injected properties (they are all on theright side of the equal sign) are added to the packager netlist files (specifically thepstchip.dat file).
Each cell in a library containing logical parts should have a corresponding .ptf file. You canplace all of these file in a single directory which will later be read by Packager-XL duringpackaging. You should maintain packaging information such as Allegro footprint(JEDEC_TYPE), VALUE, TOLERANCE, and PWR_RATING in this file.
Concept HDL Libraries ReferenceCadence Digital Library Standards
In some cases, you may wish to automatically generate .ptf files from an existing MRP(Material-Resource-Planning) system. Preferred parts and user part information could beextracted and used for .ptf file creation. This would ensure accurate and current information.The preferred parts are determined by a property called STATUS in the .ptf file. The valuesare PREF for preferred parts and NONPREF for the non-preferred ones. This allows you toeasily view and filter the selection of parts based on preferred parts when placing parts in theschematic. CheckPlus can then be used to flag any parts selected from the NONPREFentries.
Physical Part Table File Format
You can create a physical part table using any text editor or the Part Table Editor fromCadence. These files are kept in tabular form, and can easily be read and updated. A physicalpart table file can contain information for one or more part types. A Part Table file begins witha line that identifies the type of file it is
FILE_TYPE = MULTI_PHYS_TABLE;
and ends with the keyword
END.
Between these two lines you can include information for more than one part type. Each parttype definition is a separate part type table. Each table begins with a line with the keywordPART followed by the name of the part type being redefined by the table entries, and endswith the keyword END_PART (notice the absence of a period).
Syntax
The physical part table file has the following general format:
FILE_TYPE = MULTI_PHYS_TABLE;
PART ’part_name’
[ part_type_ prop_list ]
table_format_definition
table_entry
END_PART
PART ’part_name’
January 2002 48 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
.
.
.
END_PART
END.
The figure below shows a generalized picture of a physical part table file, along with theformat of an individual part type table.
The subsections that follow provide detailed syntax information on the format of a part typetable. Each line marked with a bullet in the part type table outline below corresponds to asubsection that follows.
FILE_TYPE = MULTI_PHYS_TABLEpart type table...part type tableEND.
PART ‘part name’part type property listtable format definitiontable entriesEND_PART
PART ‘part name’part type property listtable format definitiontable entriesEND_PART
January 2002 49 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
PART ‘part_name’
The physical part name of the component being redefined by the table entries. Thepart_name must be enclosed in single quotes.
Part_Type Property_List
You use this section of the part tables to add new properties to all instances of a part typewithout having to modify the physical information files or library drawings.
There can be any number of property name/value entries, but there can be only one entry perline.
If a property does not fit on one line, use a tilde (~) as a continuation character. The ~ canappear between any two characters in a line but must be the last character in the line.
For example, this entry is read as if it were all on one line:
CLASS = DIS~
CRETE
Multiple spaces in a line are read as one space. Leading and trailing spaces around propertyvalues are removed. If leading or trailing spaces are required, surround the property valueswith single or double quotes:
part_type_ property_list This is useful when you want to add properties independentof any set of properties attached to a logical part. Thepart_type_ property_list follows the format:
property_name = property_value
property_name A standard HDL property. It is a string of nomore than 16 alphanumeric characters,beginning with an alphabetic character. Theunderscore (_) is considered analphanumeric character.
property_value Any string of characters, terminated by theend of the line.
January 2002 50 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
CLASS = ’ DISCRETE ’
You can include a quote mark in a quoted string by doubling it when used:
HOW_ARE_YOU = ’I’’m OK’
Table Format Definition
This line defines the format of each table entry that follows.
The left-hand side of the table_format_definition describes the key property namesthat are attached to an instance of the part on the schematic. These properties control theselection and customization of the part. More than one property can be specified andproperty definitions can span several lines.
For example, the following definition specifies that the VALUE property is optional on the part:
: VALUE(OPT=’1K’) = PART_NUMBER;
If the VALUE property is not present on the part, the Packager assumes a default value of 1Kand does not generate any warning messages.
If more than one property is specified, all properties must match the values as specified inthe table before the part entry is selected.
The following figure shows a physical part table with two properties specified. For each partinstance, both VALUE and TOLERANCE must match the specified values before the entry is
prop_name A standard property name
OPT Defines whether a property is optional on an instance of a part.
‘def’ The default value for the property if it is not present on an instance of thepart. The default value must be enclosed in single quotes. If the defaultvalue is not included, Packager-XL uses the first entry in the table thatmatches the other key properties.
January 2002 51 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
selected. In this case, changing the TOLERANCE property on a 1K resistor selects a differentpart (with a corresponding change in cost).
separator
If your instance property list or part property list contains more than one entry, you mustchoose a separator character. You indicate your choice of separator character simply by usingan eligible character in your definition. Your character choice as a separator eliminates theuse of that character in expressing a property value. You may use the same separatorcharacter in the instance and part property lists or define a different character for each list.
A separator may be any keyboard character (including a space or multiple spaces) that doesnot have a conflicting definition. It cannot be a letter, a digit, or any of the following specialcharacters:
( ) Opening and closing parentheses, which delimit attributes
{ } Opening and closing braces, which delimit comments
[ ] Opening and closing square brackets, which enclose a range for an R attribute.These characters are ineligible only when the R attribute is used.
= Equal sign, which is an assignment character
: Colon, which introduces the table format definition
; Semicolon, which is a statement terminator
‘ “ Quote marks (single or double), which indicate that spaces should beinterpreted literally
_ Underscore, which is interpreted just as a letter or number
~ Tilde, which is a continuation character
File_Type = MULTI_PHYS_TABLE;
PART ‘1/4W RES’
: VALUE, TOLERANCE = PART_NUMBER COST;
1K, 5% = CB1025 $0.05
1k, 1% = CB1021 $0.50
1.2k, 5% = CB1225 $0.05
1.2K, 1% = CB1221 $0.50
END_PART
END
January 2002 52 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
The characters you define as separators in this format line are the same characters you mustuse as separators for each table entry that follows.
The following example uses a comma to separate the property names VALUE andTOLERANCE.
Example
:VALUE, TOLERANCE = PART_NUMBER, COST;
The second half of the table_ format_definition describes a list of the properties forthe Packager to associate with the new part type. The prop_name and separator are thesame as those defined for the first half of the definition. The separator in this section does nothave to be the same one used previously; any of the legal separator characters are allowed.There is no limit to the number of properties that can be specified.
Part Table Entries
The table_entry section of the part table contains the actual physical part table entries thatPackager-XL searches to determine the new part types to create.
instance_val The value or values of each instance of the property whose namesare defined on the left side of table_format_definition must matchbefore the entry is selected. There must be the same number ofinstance_val entries as there are property names on the left side oftable_ format_definition.
part_type_val The values to attach to the definition subtype in the chips.prt fileof Packager-XL, if this table entry is selected. There must be thesame number of part_type_val entries as there are entries on theright side of table_ format_definition.
January 2002 53 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
added_ prop entries are only used when you need to add new properties for the part typecreated for this table entry.
The figure below shows a physical part table that defines a new property value. Part typescreated for resistors with a VALUE of 1K, a PART_NUMBER of CB1025, and a COST of $0.05will also have a TOLERANCE of 5%. Resistors with a VALUE of 1.2K or 1.5K will not havethe TOLERANCE property added to the new part type.
name_spec The new part subtype name specification for this table entry. This isan optional item in the table entry. name_spec can follow thesethree forms:
■ !
■ subtype_name_suffix
■ ~complete_user_subtype_name
See Part Subtype Names for an explanation of the valuesname_spec can take
added_ prop A list of properties that are added to this part. This allows you toadd properties to specific parts without having to redefine the tableformat for all parts. Each added_ prop must be a standard SCALDproperty name. Commas must separate multiple properties.
‘added_val’ The property value to match added_ prop. The value must beenclosed in single quotes.
FILE_TYPE = MULTI_PHYS_TABLE;
PART ‘1/4W RES’
:VALUE = PART_NUMBER, COST;
1K = CB1025, $0.05: TOLERANCE = ‘=5%’
1.2K = CB1225, $0.05
1.5K = CB1525, $0.05
END_PART
END.
January 2002 54 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Adding Mechanical Parts to the chips.prt File
Part Subtype Names
Parts defined in PPTs are assigned new part subtype names. You can control the subtypename with the name_spec item in each table entry, and with the PACK_TYPE property valueon instances of the part. These subtype names do not affect how Packager-XL selectschips.prt file entries. Refer to the discussion of PACK_TYPE in Chapter 2 of the Packager-XL Reference Manual.
The figure below illustrates some of the ways to define the part subtype name.
Figure 3-1
You can create subtype names in several ways:
■ You can specify the suffix to append to the parent part type name.
■ You can tell Packager-XL to use the instance property values as the suffix. This is thedefault behavior.
■ You can specify the entire subtype name.
FILE_TYPE = LIBRARY_PARTS;
primitive ‘HEATSINK’;
body
NC_PINS = ‘(1)’;
PART_NUMBER = ‘HEATSINK’;
CLASS = ‘MECHANICAL’;
end_body;
end_primitive;
END.
VALUE, TOLERANCE = PART_NUMBER, COST Resulting Name
1K 2% (1K) = 1285 $.50 RESISTOR-1K
2.3K 1% (2.3K) = 1300 $.50 RESISTOR-2.3K
1K 5% (1K, 5%) = 1024 $.24 RESISTOR-1K,5
5K 1% (!) = 1000 $.43 RESISTOR-5K,1%
1K 3% (!) = 1028 $.24 RESISTOR-1K,3%
1K 4% (!) = 1028 $.24 RESISTOR-1K,4%
10K 5% (~R10K) = 1029 $.24 R10K
January 2002 55 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Automatic Subtype Names
If you leave name_spec out of the table entry, Packager-XL uses the instance property valuesas the suffix.
User-Defined Suffixes
If you put a string of text between the parentheses in the name_spec, Packager-XL puts adash in front of the string and appends it to the parent part type name. Lines 2-4 of Figure 3-1on page 55 use this method.
Instance Property Value Suffixes
If you use an exclamation point (!) as the name_spec, Packager-XL constructs a suffix for theparent part type from the value(s) of the instance property or properties (the property valuesthat tell Packager-XL which table entry to use for each instance). Lines 5 and 6 of Figure 3-1on page 55 use this method.
Thus, for all three of the suffixes above, the part subtype names follow the form
parent_partname[ _PACK_TYPE]-suffix
Characters Allowed in a Suffix
The characters that are allowed in a subtype suffix are all letters and digits and the followingspecial characters:
, $ % # & * + _ .
The PART_TYPE_LENGTH directive controls the subtype name length limit. The length of thepart type and the suffix together cannot exceed the value of the PART_TYPE_LENGTH option,which has a maximum value of 255. If the names are longer than this limit, these names aretruncated.
If no suffix is specified, Packager-XL uses the instance property values as the suffix.
Complete User Subtype Names
If you use a tilde (~) followed by a string of text, the packager uses that name as the name ofthe new part. The name is arbitrary, and need not contain or even resemble the parent parttype name. Line 8 of Figure 3-1 on page 55 uses this method.
January 2002 56 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Names from the PACK_TYPE Property Value
Suppose your organization screens LM741 op amps by hand to select low-noise parts, andthat you use LM741s in several different packages. You might attach a propertyLONOISE=TRUE in the schematic to the instances of the part that must be the special low-noise versions. Your part table file would be as follows:
The packager would produce part subtype names like:
■ LM741_DIP-LONOISE
■ LM741_DIP-NOISY
■ LM741_SMD-LONOISE
Here is another example. Consider the part table displayed below:
If there is an instance of a 74LS00 with values of 1, 2, and 3 for the properties A, B, and Crespectively, Packager-XL creates the subtype name MODIFIED_74LS00 and gives the partthe properties PART_NUMBER=001 and COST=30, with the pinouts of the 74LS00 entry inthe chips.prt file.
If there is an instance of the 74LS00 with values of 4, 5, and 6 for A, B, and C, and theproperties PACK_TYPE=DIP and PART_NAME=74LS00, Packager-XL creates a subtype
FILE_TYPE = MULTI_PHYS_TABLE;
PART ‘LM741’
: LOWNOISE
TRUE (LONOISE) = $1.50
FALSE (NOISY) = $0.75
END_PART
END.
FILE_TYPE = MULTI_PHYS_TABLE;
PART ‘74LS00’
:A,B,C = PART_NUMBER, COST;
1, 2, 3, (~MODIFIED 74LS00) = 001, 30
4, 5, 6, (~74LS00NEW) = 002, 40
END_PART
END.
January 2002 57 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
with the name 74LS00NEW with properties PART_NUMBER=002 and COST=40. Thissubtype receives the pinouts of the 74LS00_DIP entry in the chips.prt file, or the 74LS00entry if there is no 74LS00_DIP in the chips.prt file.
It is possible to produce name conflicts when using this syntax in part tables. Suppose thatthe previous example was changed as follows:
Subtype Name Conflict
If your design contained a 74LS00 with the values 4, 5, and 6 for properties A, B, and C, andanother 74LS00 with values 7, 8, and 9 for A, B, and C, Packager-XL would issue an errormessage stating that the last two subtype names are in conflict.
When you use the PACK_TYPE property as one of the instance properties in a table entry,and also use the tilde (~) to specify a complete user subtype name, your subtype name isapplied only to the package subtypes of that value of PACK_TYPE.
In the example below, the first entry is only applied to parts of package subtype 74LS00_SO(that is, parts with the property PACK_TYPE=S0). The second entry is only applied to partsof the subtype 74LS00_DIP.
Creating Subtype Names When PACK_TYPE is in the Table Definition
If PACK_TYPE is declared as optional in the part table, and has a default value, the entrycorresponding to the default value is also applied to the base (parent) part type when it carriesno PACK_TYPE property:
PART ‘74LS00’
:A,B,C = PART_NUMBER, COST;
1, 2, 3, (~MODIFIED 74LS00) = 001, 30
4, 5, 6, (~74LS00NEW) = 002, 40
7, 8, 9, (~74LS00NEW) = 003, 50
PART ‘74LS00’
:A,B,C = PART_NUMBER, COST;
1, 2, 3, S0 (~MODIFIED 74LS00) = 001, 30
4, 5, 6, DIP (~74LS00NEW) = 002, 40
January 2002 58 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Creating Subtype Names When PACK_TYPE is in the Table Definition
In the above figure, the first entry is applied to instances of the 74LS00 withPACK_TYPE=SO. The second entry is applied to instances with no PACK_TYPE property,and to instances with PACK_TYPE=DIP.
If the chips.prt file entries for 74LS00 and the version with PACK_TYPE=DIP are different,the packager would report an error if the design contains 74LS00s both with and without thePACK_TYPE=DIP property. The error occurs because both parts map to the same subtypename, 74LS00-NEW, but have different chips.prt file entries (different pinouts).
Sample Physical Part Table
The table below shows an example of a physical part table for 1/4-watt resistors. Commentsare enclosed in braces and precede the element they describe. The line numbers on the leftare not actually part of the file. They are used to describe the format of the table.
Line 1 Starts the physical part table file and tells Packager-XL that thefile is a multiple physical part table file. It can contain more thanone part type.
Lines 2 through 4 Separates the first line from the lines that follow. Packager-XLignores blank lines and comment lines, but these lines make thefile more easy to read. Comments are enclosed by curly braces ({ } ). Comments can cross line boundaries, but they cannot benested.
Line 5 Starts the physical part table entries for the 1/4W RES part type.The part type name must be enclosed in single quotes. Eithersingle or double quote marks are required if the part nameincludes spaces.
Lines 9 and 10 Indicate that all 1/4-watt resistors have the body propertiesCLASS and JEDEC_TYPE added to the part type, with thevalues DISCRETE and CR1/4W respectively.
Concept HDL Libraries ReferenceCadence Digital Library Standards
Line 14 Describes the format for each line in the table for the 1/4-wattresistor. In this example, the property that can be used to modifythe resistor is VALUE. The properties added to the new parttypes are PART_NUMBER and COST. The comma thatseparates the PART_NUMBER and COST properties in this linedefines the separator character between values within the table.As such you cannot use a comma to express a property valuewithin this part type table.
Lines 18 to 28 The actual physical part table entries which Packager-XL uses todetermine the new part types to be created. For example, line 18specifies that all 1/4-watt resistors with a VALUE property of 1Kare assigned to a new part type. This new part type has the samedefinition as a 1/4-watt resistor without a VALUE property plus theadditional properties PART_NUMBER and COST with the valuesof CB1025 and $0.05 respectively. If the 1/4-watt resistor had aVALUE of 4.7K, the added PART_NUMBER and COST would beCB4725 and $0.05.
Line 32 The end of the part table for the part type 1/4W RES. There canbe additional part type definitions for other part types within thesame physical part table.
Line 36 The end of the file.
January 2002 60 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Sample Physical Part Table
1 FILE_TYPE = MULTI_PHYS_TABLE;
2
3 ( 1/4-watt resistor table )
4
5 PART ‘1/4 W RES’
6
7 ( part_type_prop_list (ALLEGRO specific props )
8
9 CLASS = DISCRETE
10 JEDEC_TYPE = CR1/4W
11
12 ( table_format_definition )
13
14 : VALUE = PART_NUMBER, COST;
15
16 (table_entry section - resistors )
17
18 1K = CB1025, $0.05
19 1.2K = CB1225, $0.05
20 1.5K = CB1525, $0.05
21 2.2K = CB2225, $0.05
22 2.7K = CB2725, $0.05
23 3.3K = CB3325, $0.05
24 3.9K = CB3925, $0.05
25 4.7K = CB4725, $0.05
26 5.6K = CB5625, $0.05
27 6.8K = CB6825, $0.05
28 8.2K = CB8225, $0.05
29
30 ( end of the 1/4 W RES entries)
31
32 END_PART
33
34 ( end of the physical part table file )
35
36 END.
January 2002 61 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Standards for Symbols
The symbols can be created using Concept-HDL. However, you should use the PartDeveloper tool for generating rectangular symbols that have a large number of pins (forexample, VLSI devices). The following are the standards that Cadence uses for creatingconventional symbols:
■ All bodies are drawn using a grid spacing of 0.05 2 grid (grid points are 0.05 inches apartand grid lines are at 0.1 inches interval).
■ Connections to slant or circular bodies and placement of notes are done using 0.01 10grid.
■ By keeping the origin at the center of the body, bodies are drawn symmetrically.
■ Input and output pins are placed such that the body has a balanced look.
■ Input pins are placed at the left and output and I/O pins are placed on the right.
■ Some control pins such as enable, set, and reset may be placed at the top or bottom.
■ All pins are placed on visible grid lines (0.1 inch apart).
■ In some cases, it is necessary to place an output pin between the grid lines but thesepins are still on grid points. These are connected to the body with a 0.1-inch wire (forhigh-asserted pins), a circle of 0.1-inch diameter (for low-asserted pins).
■ Pin names and notes are selected according to the data book information.
■ When names are different in different manufacturers data books, a common name isselected, which can be recognized quickly by the hardware engineers. These names arethen used consistently across all similar parts and libraries. The pin names conform tothe Cadence signal syntax.
■ Pin names are placed on the same grid nearer to the pin.
■ Bottom and top pin names are arranged without overlapping.
■ The shape of the body will generally indicate the function of the part as closely aspossible.
■ Gates have a height of 0.3 inches with a 0.6 inch spacing between input and output pins.
■ Where functions of pins are obvious, no notes are placed inside the gates.
■ All text (properties, signal names, notes, and so on) is entered in uppercase letters.
■ Body names are selected to match the part being developed with technology (LS forLSTTL), revision, speed, and manufacturer name (for unique parts).
January 2002 62 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
■ Body names are of 0.6 Concept size or more, proportional to the size of the body (1Concept size = 0.072 inch).
■ Part functional description is added as a note (for example, SHIFT REGISTER).
■ The text size is smaller than or equal to the body name text size but not bigger.
■ Simple functional gates do not require functional notes since their function is obvious.
■ Pin name notes are placed 0.02 inches from the borders.
■ Pin name notes are of 0.8 Concept size. Since a pin indicates its assertion, the pin namenote does not reflect the pin assertion.
■ For fixed size vector pins, the bit range is specified as subscript to the pin name note.The size of subscript is smaller than the pin name note (0.6 Concept size). Rangesubscripts are not used with size-wide vector pins (pin names with <SIZE-1..0>extension). Subscript range is used only where it makes sense. Therefore, multiplexerdata inputs and decoder outputs are not subscripted.
■ Edge triggered clocks are drawn with a wedge of 0.1 inch near the pin.
■ Pin name note is not required for such pins.
■ Through pins are used wherever possible. Example: Clock, Set, Reset and Enable pins.
■ Through pins are placed on the body lines and can be placed on a 0.05-inch grid ifnecessary. Pin names are associated with the position of through pins but pin namenotes are not required.
■ All properties attached to a body have name and value visible except the propertiesNEEDS_NO_SIZE, HAS_FIXED_SIZE and SECTION, which are made invisible.
■ All visible properties are placed above the body on a grid and invisible properties areplaced near the origin.
Note: When the symbol is instantiated in the schematic, Concept-HDL aligns any instancespecific properties that are added with the visible properties. If a visible property is placed onthe symbol body, instance specific properties that are added will overlap the symbol.
■ All bodies are drawn as small as possible but large enough to prevent overcrowding ofpin name notes.
■ Different versions such as DeMorgan, Flat, and Asymmetrical are drawn for a body withversion 1 being the simplest.
■ All body versions have the same default properties, except SIZE, SECTION, and so on.
■ Asymmetrical body versions use different pin names for different versions (sections).
January 2002 63 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
■ Wherever possible, the bubble group property is used to avoid more versions of the body.
Standards for Physical Information
Physical information or properties is contained in the chips.prt file. For parts with a smallpin count, you can create this file using any text editor. However for complex parts that havea large number of pins, you should use the Cadence Part Developer to create the chips.prtfile. When you use the Cadence Part Developer, you do not need to know the syntax of thechips.prt file.
The standards that Cadence uses when creating the chips.prt file are as follows:
■ The primitive statement in the first section lists the default package and also the mostcommon package of the part (for example, primitive 74LS00, 74LS00_DIP).
■ Identical packages can share the same physical information by including all suchpackages in the same primitive statement. The packager needs to have the sameJEDEC_TYPE (Allegro outline for the part), for example, 54LS00, 54LS00_DIP,54LS00_CERDIP.
■ The chips.prt file can have multiple sections for different packages (for example, DIP,SOIC, LCC, and so on).
■ The pin section of the chips.prt file contains the following pin properties:
Pin Properties Description
PIN_NAME PIN_NAME is the same as the name for the corresponding pinin the Concept HDL drawing, except for low asserted pins. Forlow asserted pins, the asterisk is replaced with a - sign beforethe pin name. Also, suffix <SIZE-1..0> in a Concept-HDL bodydrawing is replaced by <0> in the chips.prt file.
PIN_NUMBER The pin number can be any alphanumeric character includingthe underscore character. The maximum length of a pinnumber is 16 characters. Also, the pin number sequence isfrom MSB to LSB.
PIN_GROUP This property is attached to all swappable pins.
INPUT_LOAD Part Developer assigns this property to an input pin. The inputlocal current is measured in milliamperes.
OUTPUT_LOAD Part Developer assigns this property to an output pin. This ismeasured in milliamperes.
January 2002 64 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
■ The body section of the chips.prt file contains the following properties:
OUTPUT_TYPE Part Developer assigns this property to define an output pin asopen collector, open-emitter or, tri-state. This data is used tomake sure all outputs on a net have the same output type. TheOUTPUT_TYPE property also specified the logic functioncreated by tying the outputs together.
BIDIRECTIONAL Use this property to determine a pin as bidirectional.Bidirectional pins have both input and output load properties.Bidirectional pins also have the property BIDIRECTIONAL =TRUE. In case of three-state output pins, the input loadrepresents three-state leakage current IOZL and IOZH.
NO_LOAD_CHECK This property is used to suppress a check in PackagerXL.
NO_IO_CHECK This property is used to suppress a check in PackagerXL.
ALLOW_CONNECT This property is used to suppress a check in PackagerXL.
UNKNOWN_LOADING This property is used to suppress a check in PackagerXL.
Properties Description
POWER_PINS This property defines the default power and ground requirementsfor the physical part. Power and ground pins which need to beconnected together on the board will share the same name. Thuspins will be named VCC1 and VCC2 only when they are atdifferent voltage levels across the parts. When vcc/gnd pins aredefined in a chips.prt file and have a pin_type assignment,the pinuse does not get set in Allegro.
NC_PINS NC_PINS describes the pins not connected to the logic, butwhich are present in the physical package.
FAMILY FAMILY property specifies logic family property.
PART_NAME Describes the part name
BODY_NAME Describes the body name
JEDEC_TYPE All packages of a chips.prt file have the JEDEC_TYPE property,which provides the name of Allegro physical package to be usedfor component placement on the board.If the Allegro package is not available for any component type, avalue of NONE is used.
Pin Properties Description
January 2002 65 Product Version 14.2
Concept HDL Libraries ReferenceCadence Digital Library Standards
Note: Asymmetrical sections are supported in the chips.prt file.
CLASS This property determines the category of the component. Thevalue this property can take is DISCRETE, IC or IO. DISCRETEis used for discrete components such as resistors, capacitors,and so on. IC is used for semiconductor components and IO isused for passive I/O components such as terminals, connectorsand so on.
Properties Description
January 2002 66 Product Version 14.2
Concept HDL Libraries Reference
4Simulation Views
Overview
In order to proceed with the simulation of parts, you need to create the simulation views. Thecreation of the views and their contents will depend on the following:
■ Whether Verilog or VHDL is used for simulation
■ Whether the simulation flow is based on map files or wrappers.
For map file based simulation using Verilog, you should create a directory and store theVerilog map files in this directory. Although the name of the directory is user-defined, it issuggested the directory be named vlog_map as that it is the convention followed for theCadence supplied libraries. The Verilog map files should be named verilog.map.
For wrapper based simulation using Verilog, create a directory and store the Verilog wrappersin this directory. The name of the directory is user-defined. However, it is suggested that thedirectory be named vlog_model to be consistent with the naming convention followed bythe Cadence supplied libraries. The Verilog wrapper file should be named verilog.v.
For map file based simulation using VHDL, you should create a directory store the VHDL mapfiles in this directory. The directory name is user-defined. The VHDL map files should benamed as vhdl.map.
For wrapper based simulation using VHDL, create a directory and store the VHDL wrappersin this directory. The VHDL wrapper file should be named vhdl.vhd.
Verilog Map File
The Verilog map file (verilog.map) specifies pin-to-port mapping information, and theparameters to be passed to the Verilog modules. Generally this file is only necessary forexternally defined libraries. This file can also be used for user-defined Verilog modules, butthis is not usually necessary.
January 2002 67 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
The Verilog map file must be located under the directory used to stop the expansion of thedesign (for example, vlog_map) and must be called verilog.map.
The following illustrates the format of the Verilog map file:
Note: If an entry is longer than one line, use a tilde (~) as a continuation character. The tildecan appear between any two characters in the entry, but must be the last character in the line.
PRIMITIVE Section
The PRIMITIVE section describes all the information related to a specific primitive. The nameused for the primitive is either the body name used in Concept-HDL or the part namespecified in the PART_NAME property. For example, in the lsttl library the LS00 has aPART_NAME = 74LS00 property and the primitive name 74LS00. You can modify this nameby adding a PACK_TYPE property on a specific instance. For example, if an instance of anLS00 has a PACK_TYPE = DIP property, the primitive name is 74LS00_DIP.
In the Verilog map file you can describe several PRIMITIVE sections for different primitivenames. For example, you can describe a primitive section for a 74LS00, another section fora 74LS00_DIP, and a third section for a 74LS00_SOIC. Netassembler selects the entry based
on the primitive name for a specific instance. If there is no description for a primitive nameobtained with the PACK_TYPE property, Netassembler looks for an entry without thePACK_TYPE suffix.
For example, if there is no entry for a primitive called 74LS00_LCC, Netassembler looks fora 74LS00 entry; if not found, Netassembler generates an error. In most cases, thismechanism lets you describe only one primitive section as long as mapping information isindependent of the PACK_TYPE.
Two special entries can be defined in the PRIMITIVE section:
■ The DEFAULT_MODEL property is used to specify the default name of the Verilogmodel.
This default name is used by Netassembler as a default when no VERILOG_MODELproperty has been used on an instance.
■ The UPPER_CASE property is used to specify that a Verilog module name needs to bemade uppercase in the output netlist.
By default, all module names are lowercase unless changed by an UPPER_CASE=’TRUE’ property.
The following is an example of the PRIMITIVE section for an LS00:
The output in the netlist is the following:
SN74LS00I1P(net1, net2, net3);
MODEL Section
The MODEL section contains all information specific to one or several Verilog modules. Youcan specify several MODEL sections inside one PRIMITIVE section if you have severalVerilog modules available from a library that need different mapping information. At least oneMODEL section must be described in the PRIMITIVE section.
The following is an example of MODEL section for an LS00:
PROPERTY Section
The PROPERTY section inside the MODEL section specifies local properties that apply toonly one specific Verilog module. The PROPERTY section is optional. You can add as manyproperties as you want. Netassembler use the properties described in this section to specifywhich body properties to look for. For example, if a COMPONENT property is defined in theproperty section, Netassembler searches for the property on all instances of this part in thedesign. If found, Netassembler outputs the property as a parameter for the module usingdefparam in the Verilog netlist.
Two important properties are usually defined in this section:
■ The VERILOG_NAME property specifies the actual name of the Verilog model.
Internally, all names for modules are lowercase.
If the module you are using is either uppercase or contains a mixture of lowercase anduppercase characters, use the VERILOG_NAME property to specify the final name thatwill be output in the netlist.
■ The PORT_ORDER property specifies the order of the Verilog model ports.
This information is useful for the connection by position mode when no chips.prt file(with PIN_PROPERTY) has been defined for this module.
FILE_TYPE = VERILOG_MAP;PRIMITIVE ’74LS00’;
....MODEL ’SN74LS00’, ’SIG74LS00’ ;
...END_MODEL
END_PRIMITIVE;...END.
January 2002 70 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
The following is an example of the PROPERTY section for an LS00:
The output in the netlist is the following:
TTL00I4P(NET1, NET2, NET3);
defparamI4P.COMPONENT = "SN74LS00";
PIN MAP Section
The PIN MAP section allows mapping between pin names and Verilog port names, anddescribes the Verilog port names used for each section of a multisection part.
The basic form for a pin map entry is
pin_name = ( port_name );
pin_name is the name of the pin on a Concept-HDL body. The syntax of the Concept-HDLpin name is the same syntax defined in the chips.prt file. If the pin represents a vector(multiple bits) rather than a scalar (single bit), the pin_name of the pin is specified as usual(A<3..0>). The pin_name uses the base name of the Compiler. For example, if a pin isspecified as A<SIZE-1..0>*, the pin name to use is -A<0> to represent the low assertioncharacter replaced by a minus sign (-), with the value 1 substituted for SIZE.
port_name is the name of the Verilog port. If the port represents a vector (multiple bits)rather than a scalar (single bit), the port_name of the port is specified as the following:
Note: The LSB on the left side maps to the first port_name on the right side and the MSB onthe LHS maps to the last port_name on the RHS. In this case A<0> body pin maps to A[0]and A<3> body pin maps to A[3].
If the part has multiple sections, the pin_map must specify the port_map for each section.The form of the pin map for specifying sections is
pin_name = ( port_name, port_name, ...)
where port_name specifies the port name for the same pin but for a different section. Forexample, the output pin of an 74LS00 (a quad NAND gate) is specified as
’Y’<0> = ’(_4Y, _3Y, _2Y, _1Y)’;
You must specify four port names, because the part has four sections.
If a pin is common to each of the four sections, it must be given four port names; the portnames are all identical. For example, the clock pin of a 74LS273 (an octal register) is specifiedas follows:
You must ensure that the port names are consistent for all ports of each section. Each namein the port name list specifies a different section.
For example, Netassembler expects the second name in the list to correspond to the secondsection for every port of the part.
If a sectioned part has vectored pins, its port names are specified in a similar manner. Forexample, a 3-bit pin in a part with two sections might be specified as
’A’<2..0> = ’(<1A2, 1A1, 1A0>, <2A2, 2A1, 2A0>)’;
Asymmetrical parts have multiple sections that are functionally different, such as the74LS241, which has four buffers with active-high enables and four buffers with active-lowenables. A different version of the body is defined for each section in the part. The pins in thedifferent versions all have different pin names, so that a pin of a given name is only presentin one section. The port map values for the pin specify all the sections of the part. Any portthat is not present in a given section is specified with a port name of 0.
January 2002 72 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
For example, the pin map section for an 74LS241 is the following:
The syntax for port mapping also allows for a more compact syntax. In addition to theprevious notation, the following features are also supported:
■ Subranges
Port map (Y4, Y3, Y2, Y1) is equivalent to (Y4..Y1)
■ Repeat sections
Port map (OE, OE, OE, OE) is equivalent to (OE * 4)
■ Vectored pins
Port map (<Y2..Y0> * 2) is equivalent to (<Y2, Y1, Y0>, <Y2, Y1, Y0>)
For example, the previously described 74LS241 can be described using the followingcompact syntax:
Note: Pin names in the Concept-HDL are case insensitive, but port names in Verilog arecase sensitive. Whatever is defined for the port name in the PIN_MAP section is used directlyin the output file.
The following example is a map file for a Verilog model for a part with sections (LS153):
The output in the netlist is the following:
SN74L3153I2P(._1Y(LS153_Y),
.B(LS153_S[1]),
.A(LS153_S[0]),
._1C3(LS153_I3),
._1C2(LS153_I2),
._1C1(LS153_I1),
._IC0(LS153_I0),
._1G_(LS153_E));
Note: To operate on a part that contains sections, Netassembler must have a chips.prtfile. The Cadence-provided standard parts library comes with a chips.prt file, so do notmodify it.
The following example is of an SWIFT model with sections (LS153):
The output in the netlist is the following:
TTL153 PAGE1_2P (.A(LS153.S[0],
.B(LS153_S[1]),
.C10(L153_I0),
.C11(LS153_I1),
.C12(LS153_I2),
.C13(LS153_I3),
.G1(LS153_E),
.Y1(LS153_Y));
defparam PAGE1_2P.COMPONENT = "SN74LS153";
Note: To operate on a part that contains sections, Netassembler must have a chips.prtfile. The standard parts library provided by Cadence comes with a chips.prt file, so donot modify it.
The following example is of a Verilog model for an asymmetrical part (LS241):
The output in the netlist is the following:
SN74LS241 PAGE1_1P (._2Y1(LS241_0),
._2G(LS241_E),
._2A1(LS241_I));
Note: To operate on an asymmetrical part, Netassembler must have a chips.prt file. Thestandard parts library provided by Cadence comes with a chips.prt file, so do not modifyit.
Verilog Wrappers
The Verilog wrapper (verilog.v) is a Verilog module declaration. The ports in the moduleshould match those declared in the Concept symbol. The module instantiates the originalVerilog model, with explicit port mapping to the ports declared in the Verilog model.
The following illustrates the structure of a Verilog wrapper file.
The wrapper follows the standard Verilog syntax. The module ports should be taken from theverilog.v file created under the entity view of the part. For a sizeable part, you shoulddefine the enter the size parameter. Then, you need to create an array of instances of theactual Verilog model. In the array of instances, the range values should be from size-1 to 0and the port declaration should contains the mapping of the model ports to the pin names.For a sizeable part, you should appropriately change the value of the size parameter.
Note: In case you are using the full Verilog model, you should specify the complete port list,even if the ports are not mapped to any symbol pins.
Examples of Verilog Wrappers
This section contains the examples of the following Verilog wrappers:
■ Verilog wrapper for a part without sections (LS145)
■ Verilog wrapper for a part with sections (LS241)
■ Verilog model for an asymmetrical part (LS241)
Verilog Wrapper Without Sections
The following example is of a Verilog wrapper without sections (LS145):
The following example is of a Verilog wrapper for an asymmetrical part (LS241):
‘timescale 1ns/100ps
module ls241 (a, b, oe0, œ1* , y0, y1);
parameter size = 1;
input oe0;
input œ1* ;
input [size-1:0] a;
input [size-1:0] b;
output [size-1:0] y0;
output [size-1:0] y1;
SN74LS241P1 inst1[size-1:0] (/*._1G_*/ œ1* ,
/*._1A4*/ b,
/*._1Y4*/ y1 );
endmodule
January 2002 80 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
VHDL Map File
The VHDL map file (vhdl.map) specifies pin-to-port mapping information and theparameters to be passed to the VHDL descriptions. Generally the file is only necessary forexternally defined libraries. The file can also be used for user-defined VHDL descriptions, butthis is not necessary unless the symbol names differ from the model names.
The VHDL map file must be located under the directory used to stop the expansion of theCompiler (vhdl_map) and must be called vhdl.map.
VHDL Map File Format
The VHDL map file provides information about the following:
■ The VHDL library that contains the components
■ The VHDL package that contains the component declarations
■ Generics and attributes found in the LMC package component declarations
The PRIMITIVE section describes all the information related to a specific primitive. The nameused for the primitive is either the body name used in Concept-HDL or the part namespecified in the PART_NAME property. For example, in the lsttl library the LS00 has aPART_NAME = 74LS00 property and the primitive name 74LS00. You can modify this nameby adding a PACK_TYPE property on a specific instance. For example, if an instance of anLS00 has a PACK_TYPE = DIP property, the primitive name is 74LS00_DIP.
In the VHDL map file you can describe several PRIMITIVE sections for different primitivenames. For example, you can describe a primitive section for a 74LS00, another section fora 74LS00_DIP, and a third section for a 74LS00_SOIC. Netassembler selects the entry basedon the primitive name for a specific instance. If there is no description for a primitive nameobtained with the PACK_TYPE property, Netassembler looks for an entry without thePACK_TYPE suffix.
For example, if there is no entry for a primitive called 74LS00_LCC, Netassembler looks fora 74LS00 entry; if not found, Netassembler generates an error. In most cases, Netassemblerlets you describe only one primitive section if mapping information is independent of thePACK_TYPE.
You can define two special entries in the PRIMITIVE section:
■ Use the DEFAULT_MODEL property to specify the default name of the VHDL model.
This default name is used by Netassembler as a default when no VHDL_MODELproperty has been used on an instance.
■ Use the UPPER_CASE property to specify that a VHDL description name must be madeuppercase in the output netlist.
By default, all description names are lowercase unless changed by an UPPER_CASE =’TRUE’ property.
The following is an example of the PRIMITIVE section for an LS00:
The MODEL section contains all information specific to one or several VHDL descriptions.You can specify several MODEL sections inside one PRIMITIVE section if you have severalVHDL descriptions available from a library that need different mapping information. At leastone MODEL section must be described in the PRIMITIVE section.
The following is an example of MODEL section for an LS00:
PROPERTY Section
The PROPERTY section inside the MODEL section specifies local properties that apply toonly one specific VHDL description. The PROPERTY section is optional. You can add asmany properties as you want. Properties described in this section are used by Netassemblerto specify which specific body properties Netassembler needs to look for. For example, if aproperty OSC is defined in this section, Netassembler searches for this property on allinstances of this part in the design. If the property is found, Netassembler outputs theproperty as a parameter for the description using generics in the VHDL netlist.
Two important properties are usually defined in this section:
■ The VHDL_NAME property specifies the name of the VHDL model.
Internally, all names for descriptions are lowercase.
If the description you are using is either uppercase or contains a mixture of lower- anduppercase characters, use the VHDL_NAME property to specify the final name that willbe output in the netlist.
■ The PORT_ORDER property specifies the order of the VHDL model ports.
This information is useful for the connection by name mode when no chips.prt file(with PIN_PROPERTY) has been defined for this description.
FILE_TYPE = VHDL_MAP;PRIMITIVE ’74LS00’;
....MODEL ’SN74LS00’, ’SIG74LS00’ ;
...END_MODEL
END_PRIMITIVE;...END.
January 2002 83 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
The following is an example of the PROPERTY section for an LS00:
PIN MAP Section
The PIN MAP section allows mapping between pin names and VHDL port names, anddescribes the VHDL port names used for each section of a part that has more than onesection.
The pin_name is the name of the pin on a Concept-HDL body. If the pin represents a vector(multiple bits) rather than a scalar (single bit), the pin_name of the pin is specified as usual(A<3..0>). The pin_name uses the base name of the Compiler. For example, if a pin isspecified as A<SIZE-1..0>* the pin name to use is -A<0> to represent the low assertioncharacter replaced by a minus sign (-), with the value 1 substituted for SIZE.
The port_name is the name of the VHDL port. If the port represents a vector (multiple bits)rather than a scalar (single bit), specify the port name as follows:
If the part has multiple sections, the pin_map must specify the port_map for each section.The form of the pin map for specifying sections is
pin_name = ’’( port_name, port_name, ...)
’’<port_mode>’’<port_type>’’;
where port_name specifies the port name for the same pin but for a different section. Forexample, the output pin of an 74LS00 (a quad NAND gate) is specified as
Y<0> = ’’(Y_4, Y_3, Y_2, Y_1)’’out’’std_ulogic’’;
There must be four port names specified because the part has four sections.
If a pin is common to each of the four sections, it must be given four port names; the portnames are all identical. For example, the clock pin of a 74LS273 (an octal register) is specifiedas follows:
CLOCK = (CLK, CLK, CLK, CLK, CLK, CLK, CLK, CLK);
You must ensure that the port names are consistent for all ports of each section. Each namein the port name list specifies a different section. Netassembler expects the second name inthe list, for example, to correspond to the second section for every port of the part.
If a sectioned part has vectored pins, its port names are specified in a similar manner. Forexample, a 3-bit pin in a part with two sections might be specified as
Asymmetrical parts have multiple sections that are functionally different, such as the74LS241, which has four buffers with active-high enables and four buffers with active-lowenables. A different version of the body is defined for each section in the part. The pins in thedifferent versions all have different pin names, so that a pin of a given name is only presentin one section. The port map values for the pin specify all the sections of the part. Any portthat is not present in a given section is specified with a port name of 0.
For example, the pin map section for 74LS241 is the following:
The syntax for port mapping also allows for a more compact syntax. In addition to theprevious notation, the following features are also supported:
■ Subranges
Port map (Y4, Y3, Y2, Y1) is equivalent to (Y4..Y1)
■ Repeat sections
Port map (OE, OE, OE, OE) is equivalent to (OE * 4)
■ Vectored pins
Port map (<Y2..Y0> * 2) is equivalent to (<Y2, Y1, Y0>, <Y2, Y1, Y0>)
For example, the previously described 74LS241 can be described using the followingcompact syntax:
Note: Pin names in Concept-HDL are case-insensitive, but port names in VHDL are case-sensitive. Whatever is defined for the port name in the PIN_MAP section is used directly inthe output file.
Examples of VHDL Map Files
This section contains examples of the following map files:
VHDL wrappers follow the VHDL model structure, i.e it consists of an entity and anarchitecture. The VHDL entity declaration for a component is stored under the entity view andthe VHDL architecture declaration is stored in the VHDL wrapper view (for example,vhdl_wrapper) of the component.
To create a VHDL wrapper, you only need to create the architecture declaration for thecomponent. The entity declaration is automatically created when the symbol view is saved.Since the entity declaration is picked up from the entity view of the part, it is important tospecify the necessary properties to ensure an accurate entity declaration is generated.Typically, you make these properties invisible in your symbol drawings. The properties can beset for:
■ USE Clause
To ensure that a library clause and a use clause are added to the entity declaration, putthe following property to the origin of the symbol
USE xx = libname
where xx is a unique number and the libname is the name of the library.
For example, to ensure that the entity can access all names declared within theIEEE.std_logic_a1164 package in the library IEEE, give the property
USE LIBRARY = IEEE.std_logic_1164.ALL
This ensures that the following two entries are added to the entity declaration of the part:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
■ VHDL Generics
To ensure that the generic declarations are generated correctly, you need to add thefollowing property to the origin of the symbol
GENERICxx = name:type
where xx is a unique number, name is the name of the generic parameter, and type isthe generic parameter type.
For example, to ensure that the generic declaration GENERIC (delay : = 5 ns) isdeclared in the entity declaration, add the following properties at the origin of the symbol
VHDL_GENERIC1=delay:max_delay
delay = 5 ns
January 2002 89 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
After the entity declaration has been taken care of, you need to create the architecturedeclaration. Following is the general syntax for writing the architecture:
architecture <wrapper_view_name> of <part_name> is
component <VHDL_component>
generic(
generic declarations
)
port (
port declarations
);
end component;
begin
L0: For I in 0 to SIZE-1 generate -- Required only for sizeable parts
L1:block
for inst1: <VHDL_component> use entity lib.vhdl_model(vhdl_arch); -- bindingstatement
begin
inst1: <VHDL_component>
generic map(
generic maps
)
port map (
port maps
)
end block;
end generate L0;
end vhdl_wrapper;
Note: In case the part is not sizeable, you do not need to put the generate statement.
Mapping Scenarios
Following is the description of the various mapping scenarios possible while creating VHDLwrappers.
Mapping Scalar Pins With Scalar Ports
Following is the description of the method by which scalar pins are to be mapped to the scalarports.
January 2002 90 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
Entity of the Input Modelentity model is
port ( Y1N: OUT STD_LOGIC;
A1: IN STD_LOGIC := '0';
B1: IN MVL := '0';
C1: INOUT STD_LOGIC := '0');
end model;
Entity of the Input Symbolentity symbol is
port (
A: IN STD_LOGIC := ‘0’;
B: IN MVL := ‘0’;
C: INOUT STD_LOGIC := ‘0’;
Y: OUT STD_LOGIC);
end symbol;
Architecture of Output Wrapperarchitecture vhdl_wrapper of symbol is
component model
port ( Y1N: OUT STD_LOGIC;
A1: IN STD_LOGIC := '0';
B1: IN MVL := '0';
C1: INOUT STD_LOGIC := '0');
end component;
begin
inst1: model
port map ( Y1N => y,
A1 => a,
B1 => b,
C1 => c);
end vhdl_wrapper;
Mapping Vector Symbol Pins With Scalar Model Ports
Following is the description of the method by which vector symbol pins are to be mapped withthe scalar model ports.
January 2002 91 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
Entity of the Input Modelentity model is
port (inport1: in std_logic;
inport2: in std_logic;
inport3: in std_logic;
outport: out std_logic);
end model;
Entity of the Input Symbolentity symbol is
port (pin_vector: in std_logic_vector (2 downto 0);
pin_sclar: out std_logic);
end symbol;
Architecture of the Output Wrapperarchitecture vhdl_wrapper of symbol is
component model
port (inport0: in std_logic;
inport1: in std_logic;
inport2: in std_logic;
outport: out std_logic);
end component;
begin
inst1: model
port map(
inport0 => pin_vector(0),
inport1 => pin_vector(1),
inport2 => pin_vector(2),
outport => pin_scalar);
end vhdl_wrapper;
Note: You should follow similarly with escaped port names in either the model or the symbol.
Mapping Scalar Pins With Vector Ports
Following is the description of the method by which you should map scalar pins with vectorports.
January 2002 92 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
Entity of the Input Modelentity model is
port (port1: in std_logic_vector (1 downto 0);
outport: out std_logic);
end model;
Entity of the Input Symbolentity symbol is
port (pin1: in std_logic;
pin2: in std_logic;
pin3: out std_logic);
end symbol;
Output Wrapper Architecturearchitecture vhdl_wrapper of symbol is
component model
port (port1: in std_logic_vector (1 downto 0);
outport: out std_logic);
end component;
begin
inst1: model
port map(
port1(0) => pin1,
port1(1) => pin2,
outport => pin3);
end vhdl_wrapper;
Mapping Vector Pins With Vector Ports of Equal Size
Following is the description of the method by which you map the vector pins with the vectorports of equal size.
Input Modelentity model is
port (port1: in std_logic_vector (1 downto 0);
port2: out std_logic_vector (1 to 10));
end model;
January 2002 93 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
Input Symbolentity symbol is
port (pin1: in std_logic_vector (1 downto 0);
pin2: out std_logic_vector (1 to 10));
end symbol;
Output Wrapper
■ When the LSB and the MSB are to be mapped in the same order.architecture vhdl_wrapper of symbol is
component model
port (port1: in std_logic_vector (1 downto 0);
port2: out std_logic_vector (1 to 10));
end component;
begin
inst1: model
port map(
port1 => pin1,
port2 => pin2);
end vhdl_wrapper;
■ When the LSB and the MSB are bit reversedarchitecture vhdl_wrapper of symbol is
component model
port (port1: in std_logic_vector (1 downto 0);
port2: out std_logic_vector (1 to 10));
end component;
begin
inst1: model
port map(
port1(0) => pin1(1),
port1(1) => pin1(0)
port2 => pin2);
end vhdl_wrapper;
Mapping Vector Pins With a Combination of Vector Ports:
Following is the description of how to map vector pins with a combination of vector ports.
January 2002 94 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
Entity of the Input Modelentity model is
port (inport0: in std_logic_vector (15 downto 0);
inport1: in std_logic_vector (15 downto 0);
inport2: in std_logic_vector (15 downto 0);
inport3: in std_logic_vector (15 downto 0);
outport2: out std_logic_vector (1 to 31));
end model;
Entity of the Input Symbolentity symbol is
port (inpin: in std_logic_vector (63 downto 0);
outpin0: out std_logic_vector (1 to 7);
outpin1: out std_logic_vector (1 to 7);
outpin1: out std_logic_vector (1 to 7);
outpin3: out std_logic_vector (1 to 7));
end symbol;
Output Wrapperlibrary ieee;
use ieee.std_logic_1164.all;
entity symbol is
port (inpin: in std_logic_vector (63 downto 0);
outpin0: out std_logic_vector (1 to 8);
outpin1: out std_logic_vector (1 to 8);
outpin2: out std_logic_vector (1 to 8);
outpin3: out std_logic_vector (1 to 8));
end symbol;
architecture vhdl_wrapper of symbol is
component model
port (inport0: in std_logic_vector (15 downto 0);
inport1: in std_logic_vector (15 downto 0);
inport2: in std_logic_vector (15 downto 0);
inport3: in std_logic_vector (15 downto 0);
outport2: out std_logic_vector (1 to 32));
end component;
begin
January 2002 95 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
inst1: model
port map(
inport0 => inpin(15 downto 0),
inport1 => inpin(31 downto 16),
inport2 => inpin(47 downto 32),
inport3 => inpin(63 downto 48),
outport2( 1 to 8) => outpin0,
outport2( 9 to 16) => outpin1,
outport2( 17 to 24) => outpin2,
outport2( 25 to 32) => outpin3 );
end vhdl_wrapper;
Handling Sizeable Parts
The following example symbol has 2 explicit generics and one implicit generic SIZE declaredon it. The symbol has 5 ports declared on it. The VHDL model has 7 generics and 10 ports.The user wants to:
■ Map the two explicit generics
This involves updating the symbol with properties
VHDL_GENERICxx = name:type
Name = value
■ Specify a different default value for the model generics.
■ Leave one of the model sections open
This creates a component declaration with only those model ports that are mapped. Allthose model ports that are not mapped will not be part of the component declaration.
Entity of the Input Symbolentity symbol is
generic ( size:positive := 1;
TW_CONTROL:time := 1 fs;
TW_CLOCK:time := 1 ps
);
port (
cl: IN STD_LOGIC;
CLOCK: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
pr: IN STD_LOGIC;
January 2002 96 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
Q: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
qb: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end symbol;
Entity of the Input modelentity model is
generic (
tw_cntl : time := 5 ns;
tw_clk : time := 5 ns;
tsu_cntl : time := 0 ns;
ts_data : time := 3 ns;
th_data : time := 0.5 ns;
tp_cntl_max : time := 10.5 ns;
tp_clk_max : time := 10.5 ns );
port (
pre1_n : in std_logic := 'U';
clr1_n : in std_logic := 'U';
d1 : in std_logic := 'U';
clk1 : in std_logic := 'U';
q1 : out std_logic;
qb1 : out std_logic;
pre2_n : in std_logic := 'U';
clr2_n : in std_logic := 'U';
d2 : in std_logic := 'U';
clk2 : in std_logic := 'U';
q2 : out std_logic;
qb2 : out std_logic
);
end model;
Output Wrapper
In this example, the symbol is sizeable and the model is a full model with two sections. So,one of the two model sections must be left unconnected. Suppose you specify the mappingonly for the second section of the model, the component declaration as shown below, mustnot have the ports:
■ pre1_n, clr1_n, d1, clk1, q1 and qb1
January 2002 97 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
architecture vhdl_wrapper of symbol is
component model
generic(
TW_CNTL:TIME := 5 NS;
TW_CLK:TIME := 5 NS;
TSU_CNTL:TIME := 0 NS;
TS_DATA:TIME := 3 NS;
TH_DATA:TIME := 0.5 NS;
TP_CNTL_MAX:TIME := 10.5 NS;
TP_CLK_MAX:TIME := 10.5 NS);
port(
PRE2_N: in STD_LOGIC := 'U';
CLR2_N: in STD_LOGIC := 'U';
D2: in STD_LOGIC := 'U';
CLK2: in STD_LOGIC := 'U';
Q2: out STD_LOGIC;
QB2: out STD_LOGIC
);
end component;
begin
L0: For I in 0 to SIZE-1 generate
l1: block
for l2: symbol use entity lib.model(vhdl_arch);
begin l2: model
generic_map (
TW_CNTL => TW_CONTROL ;
TW_CLK => TW_CLOCK;
TSU_CNTL => 10 NS;
TS_DATA => 3.5 NS;
TP_CLK_MAX => 11.25 NS);
port map (
PRE2_N => pr,
CLR2_N => cl,
D2 => D(i),
January 2002 98 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
CLK2 => CLOCK,
Q2 => Q(i),
QB2 => qb(i));
end block;
end generate L0;
end vhdl_wrapper;
Case Sensitivity
VHDL is case insensitive in the normal namespace. However, it is case sensitive when thenames are in the escaped namespace. Escaped names start with a \ and are delimited by \.
For example: 74ac74 in Concept-HDL namespace is \74ac74\ in VHDL namespace.
Here are more examples of case-sensitive names:
Q2 => \QB*\(i),
QB2 => \qb*\(i));
Please note that QB* and qb* are different identifiers here.
January 2002 99 Product Version 14.2
Concept HDL Libraries ReferenceSimulation Views
January 2002 100 Product Version 14.2
Concept HDL Libraries Reference
5Testing Libraries
Library Utilities
After you create libraries and parts, you should validate them before releasing them to thedesigners. The following utilities are available for validation:
■ hlibgenxml
■ hlibftb
■ hlibsim
■ hlibchk
These utilities are located at:
your_install_dir/tools/libutil
You must set the path to your_install_dir/tools/libutil before running theseutilities.
hlibgenxmpl
Overview
The hlibgenxmpl utility instantiates cell(s) of a Concept-HDL library on a design sheet andwrites it to disk. hlibgenxmpl creates one design sheet for each package type. All the cellssupporting a particular package type are instantiated on the sheet of that package type. Foreach created design sheet, hlibgenxmpl makes a .cpm file, which it saves in the workingdirectory.
January 2002 101 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
Functional Diagram
Use Model
Usage:
hlibgenxmpl[-libdir <path to library>]-lib <library>[-cell <cell1> <cell2>...][-symbol <1|2|..|all>]-pack <dip|soic|..|all|default>[-page <b|d>][-ptfdirectivefile <path to ptf directive file>][-product <suite_name>][-advopt <advanced options file>]
Create a list of cell names
Create a list of symbol versions andpackage types for each cell
Generate the script file to berun by Concept-HDL
Invoke Concept-HDL
entity, sch_ for example sheet
January 2002 102 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
Usage Explanation
-libdir <path tolibrary>
(Optional) Specify the path to the library. If you do notspecify the path, hlibgenxmpl looks for the cds.lib file inthe working directory. If there is no cds.lib file in theworking directory, hlibgenxmpl creates a cds.lib file.
Note: If a cds.lib file exists in the working directory, thenthe -libdir option is ignored.
-lib <library> Specify the name of the Concept-HDL library to be tested.The location of the Concept-HDL library is passed eitherthrough the cds.lib file mapping or through the -libdiroption.
-cell <cell1> <cell2>..
(Optional) Specify the cells that need to be selectivelytested. If the selective cells are not specified,hlibgenxmpl tests all the cells in the specified library.
Note: The -cell option can be used only if the -liboption has been used.
-symbol <1|2|..|all> (Optional) Specify the symbol versions to be tested.Specify “1” to test only sym_1. Specify “2” to test onlysym_2. Specify “all” to test all symbols in the cell.If the-symbol option is not used, hlibgenxmpl tests all thesymbols in the specified cell(s).
-pack<dip|soic|..|all|default>
(Optional) Specify the pack types to be tested.
Note: Running hlibgenxmplwithout the -pack option onlibraries that have package types in the chips.prt filecauses hlibgenxmpl to display an error.
-page <b|d> (Optional) Specify the drawing sheet size to be used forinstantiating symbols. The default page size is “b.”
-ptfdirectivefile<path to ptfdirective file>
(Optional) Specify the path from which the ptfdirective filehas to loaded.
-product <suite_name> (Optional) Specify the product suite name, such asConcept-HDL.
January 2002 103 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
Example
An example of the hlibgenxmpl utility run on the SOIC package of the ls00 component inthe lsttl library is:
The hlibsim utility validates the map and wrapper views of the Concept-HDL libraries. Foreach part, the map views and wrapper views are located in the vlog_map and swift_mapand vlog_model and swift_model directories respectively. The vlog_map directorycontains the map files for Cadence Verilog models, and the swift_map directory containsthe map files for LMC Verilog models. Similarly, the vlog_model directory contains thewrapper files for the Verilog models, and the swift_model directory contains the wrapperfiles for the LMC Verilog models.
The hlibsim utility calls hlibgenxmpl to instantiate the cells of a library on a design sheet,write the design, and create a .cpm for the design. Next, wires are added to the cellsinstantiated earlier on the design sheet and Concept-HDL is invoked to update the Verilognetlist for the design. Then, NetAssembler is called, which creates a simulation view with anew verilog.v file after reading the map files.
By default, the vlog_map view is searched under each cell. You can specify any other mapview with the -mapview commandline option. You will be prompted about any missingmapfiles for the mapview specified. Next, the Verilog netlist generated earlier is split intonumber of parts equal to the number of cells instantiated in the Verilog netlist. Each such partgenerated is a complete Verilog design comprising of only one cell. Finally, Verilog simulationis run on netlist for each cell and a report on its success is generated.
Note: If you do not specify either the -mapview or -wrapperview commandline option,then by default only the vlog_map view is searched.
-advopt <advancedoptions file>
(Optional) The options given in the advanced options filesare added as is to the .cpm file within the Concept-HDLoptions block. Use this option to specify options that arenot added by default by the verification utilities.
Usage Explanation
January 2002 104 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
Functional Diagram
Use Model
Usage:
Add wires to each cell andupdate schematic
Create the simulation views(verilog.v file)
Instantiate cells in Concept-HDL
Check parts for incorrect mapviews/wrapper views and reporterrors
Split the Verilog netlist of thedesigns to get netlist for each cell
Run Verilog simulation on eachcell netlist
Report parts for which Verilog failed tocompile with the Verilog models
January 2002 105 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
hlibsim-lib <Library> | -file <libList_filename>-vloptions <Verilog_model_path_filename> | -vlogmodeldir [default| <Name ofthe directory containing Verilog models>] | -sim OFF[-vlogudpdir <Name fo direcotry containing Verilog udps>][-libdir <Concept-HDL_lib_path>][-cell <cell 1> <cell 2> .....][-clean][-mapview <Names of the map view> | -wrapperview <Names of the wrapper view>]-product <Name of the product>
Usage Explanation
-lib <Library> Use this option to provide the name of theConcept-HDL library that is to be tested. Itslocation is passed through -libdir option.
-file <libList_filename> This option invokes testing in multiple librarymode. A file should contain one library per line.If this option is used, then the -lib option is notrequired.
-vloptions<Verilog_model_path_filename>
This option must be used to specify the filenamethat contains the path of respective librariescontaining the Verilog models. This option ismutually exclusive with the -sim OFF option.
-vlogmodeldir [default| <Nameof the directory containingVerilog models>
This option must be used to specify the path tothe Verilog model libraries. This option ismutually exclusive with the -sim OFF option. Ifyou do not specify the path to the directory thenhlibsim looks for a fie calledvlog_model_path.txt under the librarydirectory. This file should contain the path to theVerilog models.
-sim OFF Use this option to turn off the simulation for theselected library. This option is mutuallyexclusive with the -vloptions and -vlogmodeldir options.
If you use this switch, hlibsim proceeds onlyupto the netlisting and Verilog is not called.
Use this option to specify the path to thedirectory containing the Verilog UDPs.
January 2002 106 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
After you run hlibsim, a consolidated report is generated as hlibsim_summary.rep anda file called final_status.rep is generated stating the status of the run on the librarydirectory.
Error-Handling
If any problem is found with the name of library or the path passed to hlibsim, it exitsimmediately, stating the problem. The problem is reported as Error. The errors found duringthe test process are directed to a log file. Also, all the inputs are be verified for their existence.
Under each library, cells are added to the report for the following cases:
■ Parts ignored (No chips view): These are reported by hlibgenxmpl.
■ No <>_map view/ No <>_wrapper view: Cells for which the specified mapview orwrapper view does not exist.
■ Simulation failed: The cells for which Verilog simulation fails.
-libdir <Concpet HDL_lib_path> Use this option to specify the directory whereConcept-HDL library (supplied through -liboption) that is to be tested is stored.
If -libdir option is used and the cds.lib fileexists in the working directory, then cds.libtakes precedence and the library directory pathshall be taken from the cds.lib file. This filemust contain the correct mapping for thelibraries to be tested.
-cell <cell1> <cell2> .... : (Optional) Use this option to specify the cells oflibrary selectively that will be tested by the utility.If -cell option is not passed, then all the cellsof the library <Library> will be tested.
-clean Use this option to clean the run directory andremove all the intermediate files.
-mapview This option should have the name of the mapview, such as swift_map and vlog_map. Bydefault, it is vlog_map.
-product This option should be used to specify theproduct name e.g. Concept-HDL.
January 2002 107 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
■ Syntax Error in Mapfile: These are the cells for which errors are reported bynewgenasym.
■ Wrapperfile Errors: These are the cells for which the errors are reported bynewgenasym.
■ Crossview Errors: These cells have crossview errors reported by newgenasym.
■ Others: These are the cells for which newgenasym did not report any errors butnetassembler did.
■ Can not test these: These are cells for which the model names are incorrect or thewrapper has errors.
Example
The hlibsim utility is run on the ls00 component of the lsttl library with the Concept-HDLproduct.
See detailed log under:map_error_log - for any syntax or crossview errors inmapfiles.wrapper_error_log - for any syntax or crossview errors inwrapperfiles.sim_error_log - for any problems in simulation of parts with verilog models.
Library: lsttl---------------
Simulation Failed : ( )Mapfile Errors : ( )Parts Ignored (No Chips View) : ( )Mapview not found : ( )No mapfile found in view : ( )
January 2002 108 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
hlibftb
Overview
The hlibftb utility goes a step beyond the hlibgenxmpl utility and packages thegenerated design sheet(s).
The hlibftb utility invokes the hlibgenxmpl utility to instantiate cells of a Concept-HDLlibrary on a design sheet using Concept-HDL. The hlibgenxmpl utility creates one designsheet for each package type. All the cells supporting a particular package type areinstantiated on the sheet of that package type. For each such created design sheet,hlibgenxmpl makes a .cpm file, which it saves in the working directory.
After running hlibgenxmpl, hlibftb invokes Packager XL to package each of the designscreated by hlibgenxmpl. Then, hlibftb performs the following steps:
■ Checks the hdldir.log, pxl.log and edbconfig.log files for errors.
■ Checks whether the schematic view has non-zero verilog.v and .sir files.
■ Checks whether the packaged view has non-zero .dat files.
■ If hlibftb is used with the -netrev option, then it invokes Allegro to create an emptyboard and netrev. hlibftb then uprevs the board with the netlist, and creates a physicalview. After creating a physical view, hlibftb checks the presence of the netrev.lstand .brd files in the physical view. Then hlibftb reports the result in the ftb.repfile.
■ Reports the result of the test on the library in a report file called ftb.rep. The report fileis created in the current working directory.
■ Declares the test library as passed, if the Concept-HDL and the PXL run are successful.
■ Reports the nature of a failure in the ftb.rep file, if any errors occur in the Concept-HDL run or at the PXL run.
The hlibftb utility loads all the .ptf files specified in the ptfdirective file, and scans themfor rows corresponding to the part concerned. If the rows have the given PACK_TYPEproperty as the key property, then all the other key properties get added to the part. Thehlibftb utility checks the properties being added to ensure that the properties are notduplicated in the corresponding symbol.css file.
hlibftb then packages the design, and checks the o/ps. If the o/ps are successful, thedesign is netreved from the created .pst file.
January 2002 109 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
hlibftb also performs the following tasks:
■ It checks whether pack_type is present in ptf files, but not in the chips.prt file.
■ It ensures that if the pack_type property on it is conflicting, then the symbol is notinstantiated for a particular pack type. In other words, it skips the parts if the pack_typeproperty on it is in conflict.
■ It checks if pack type is a part of the primitive name in the chips.prt file.
Improvements in the PSD 14.0 Release
There are a number of enhancements in the PSD 14.0 release of hlibftb. They are:
■ Ability to handle technology-independent parts.
■ Ability to handle underscores in pack types. Previously, for a cell named as240 with aprimitive entry ‘74AS240_DIP_PWR’, hlibftb used to take PWR as the packtype.
■ Ability to handle hyphenated names in packtypes.
■ Ability to handle large pin count parts.
■ Ability to handle large parts.
■ Ability to handle partial names in pack primitives. Some chips have partial names in theirpack primitives, for example
-lib <library> Use this option to specify the name of the Concept-HDL library that is to be tested. This option is mutuallyexclusive with the -file option.
-file<liblist_file_path>
Use this option to specify the path to the file thatcontains the list of the libraries that are to be tested.This option is mutually exclusive with the -lib option.
Note: The specified file should contain one library perline.
Example:
lsttl
ttl
The cds.lib file must be present in the workingdirectory with mappings of libraries to be tested. Theonly exception when the cds.lib file need not bepresent in the working directory is when the -libdiroption is used in Single Library Mode.
-libdir <lib_dirname> (Optional) Use this option to specify the path to thelibrary. If you do not specify the path, hlibftb looksfor the cds.lib file in the working directory.
January 2002 111 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
Example
Following is an example of the hlibftb being run on the ls00 component of the lsttl libraryusing the Concept-HDL product.
-cell <cell1> <cell2>... (Optional) Use this option to specify the cells that needto be tested. If the cells to be tested are not specified,hlibftb tests all the cells in the specified library.
Note: This option cannot be used with the -fileoption.
-pack<dip|soic|...|all|default>
(Optional) Use this option to specify the pack types tobe tested. The default value for this option is “default”.
Note: This option cannot be used with the -fileoption.
-ptfdirectivefile (Optional) Use this option to specify the path to theptfdirective file.
-advopt (Optional) Use this option to specify the path to theoptions file.
-PSMPATH <‘path1‘><‘path2‘>...
(Optional) Use this option to specify the path to theAllegro symbols.
- PADPATH <‘path1‘><‘path2‘>...
(Optional) Use this option to specify the path to theAllegro pads.
-product <suitename> (Optional) Use this option to specify the product name,such as Concept-HDL.
-netrev (Optional) Use this option to invoke Allegro and takethe design up to the netrev stage.
-iconoff (Optional) Use this option to toggle display between theicon mode and the full screen mode of the tools as theyare executed while running hlibftb.
-clean (Optional) Use this option to clean up the designs thathave been tested.
January 2002 112 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
The output will look as shown below:
hlibchk
Overview
The hlibchk utility checks the presence of all parts in the .cat file, checks the existence ofall views in the parts of a library, checks the syntax of view files, and verifies that the Allegrolibraries contain the JEDEC_TYPE mentioned in the chips view. Apart from these functions,hlibchk also performs a check for "HDL"/ "Comment Body" properties for non-physicalparts.
Verify that all views exist and have the required files
Verify chips for JEDEC_TYPE and its existence in theAllegro library
Presence of HDL property in parts without chips
Report
January 2002 114 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
Usage Explanation
-lib <Library> Use this option to specify the name of the 5Xlibrary to be tested. The location of the 5X libraryis passed either through the cds.lib filemapping or through the -libdir option. If the-libdir option is not used, the cds.lib file isused for library mapping. This option is mutuallyexclusive with the -file option.
-file <Liblist_file_path> Use this option to specify the path to the filecontaining the list of the libraries that are to betested. This option is mutually exclusive with the-lib option.
Note: The specified file should contain onelibrary per line.
Example
lsttl
ttl
The cds.lib file must be present in theworking directory with mappings of libraries tobe tested. The only exception to this is when the-libdir option is used in Single Library Mode.
-libdir <Concept-HDL_Lib_path> (Optional) Use this option to specify the path tothe library. The path you specify is used toinclude a mapping definition of the library in thecds.lib file present in the working directory.
-cell <cell1> <cell2> ...... (Optional) Use this option to specify the cells ofthe library <Library> to be tested. If the -celloption is not used, then all the cells of the library<Library> will be tested.
-PSMPATH <Allegro_lib_path> (Optional) Use this option to specify the pathwhere the local Allegro footprints are stored.
-simswitch (Optional) Use this option to check the existenceof simulation views. The -simswitch option isoptional.
January 2002 115 Product Version 14.2
Concept HDL Libraries ReferenceTesting Libraries
Example
Following is an example of the hlibchk being run on the ls00 component of the lsttl libraryusing the Concept-HDL product.
The HDL solution provided by Cadence imposes certain restrictions due to its architectureand use model. They are as follows:
■ In SCALD, it was possible to create technology independent libraries by having differentlogical parts mapped to one physical directory (mapping in .lib file). There is no similarmechanism in HDL.
■ In 5X representation of libraries as lib->cell->view (directories), the number of directorieshave increased substantially causing problems of disk crash on NT FAT system andexceeding inode limit even on UNIX.
■ Redundancy of data across electrically equivalent parts differing in technologies, i.e. thesymbols for parts representing different technologies do not need to be different.
To address such issues, Cadence now provides you with technology independent libraries.The solution aims at making the use model better for Component selection for Packaging orFTB flow. FTB flow means making a design using Concepthdl editor by instantiating cells ofa 5X library and packaging the design thus created using PXL.
Technology Independent Library Structure
Library Names
In the PSD14.0 release, Cadence is providing a subset of ttl technology independent libraryin the traditional and IEEE formats. This technology library is a merge of libraries as follows:
The technology independent library tidttl is stored in the same location as the other libraries,i.,e in <your_install_dir>/share/library
The parts of technology independent library are named as
<technology_bundle_name>_<generic_part_name>
Example: ttl_00
The <library>.cat FIle
Similar to technology dependent libraries, this file contains the classification of the libraryparts by functional categories. However, the category file shall have functional categorizationindependent of technology with the names of the cells valid in Concept namespace (nmpmapping of physical cell directories to Concept namespace).
Technology independent parts can be accessed through the component browser. In Concept,choose Component > Add to get the list of libraries. The technology independent tidttlappears along with the other libraries.
Note: Do not use components from tidttl and other ttl libraries in the mix.
Note: The hlibsim library testing utility will not work with the technology-independentlibraries.
Technology Independent Libraries in the FTB (PXL) Flow
Property Annotation for PXL
On selection of the primitive, the corresponding rows in ppt are shown if the ppt exists. Onselection of the ppt row for chosen primitive, the key properties should be annotated along
with the PART_NAME. In the absence of ppt information, only the PART_NAME value shouldget annotated.
chips View
The example below shows how physical parts are created when the chips file contains twoPART_NAME properties with different values (in this case representative of two differenttechnologies)
The file defines two logical parts, in this case 74LS00 and 54LS00. Three primitive entrieswhose name begin with 74LS00 cause three physical parts to be created for the logical part74LS00: 74LS00, 74LS00_DIP, 74LS00_SOIC. Two primitive entries whose name begin with54LS00 cause two physical parts to be created for logical part 54LS00: 54LS00_DIP.
In absence of the PART_NAME property, PXL takes the shortest primitive which in abovecase would be 74LS00 and 54LS00 and the two would be treated as logical parts. Otherprimitives in the corresponding same sections are compared with these logical names to findthe common base and they become the physical parts.
In this case 74LS00_DIP is physical part with logical name 74LS00, but 74LS00_SOIC wouldnot be the physical part of 74LS00 as it does not lie in the same primitive section.
This makes it mandatory for PART_NAME to exist in each of the primitives which are PACKderivatives of one logical(technology) part.
PPT View
In a PPT, if a part whose name matches the logical part name for the schematic instanceexists, then it is used with the schematic instance. Only in absence of such table, the searchis done by physical name (logical name with an underscore PACK_TYPE suffix) providedPACK_TYPE exists on the instance.
The PPT for a technology independent part shall need to have sections corresponding toeach technology (logical) part as follows:
The example below shows how a map file is organized for mapping of body pins to verilogmodel ports for all technology primitives (in this case two parts).
The “standard library” contains parts that have no logic function or physical meaning. Theseparts are used either to convey design information to the Compiler, Simulator, and Packager-XL, or to make the schematic more concisely represent the design. Each part in this libraryis a body that can be added to a drawing of any type. The following parts (bodies) are in thestandard library:
A SIZE PAGE, B SIZE PAGE, C SIZE PAGE, D SIZE PAGE, E SIZE PAGE andF SIZE PAGE
A SIZE PAGE, B SIZE PAGE, C SIZE PAGE, D SIZE PAGE, E SIZE PAGE, and F SIZE PAGEare borders placed around a drawing. These borders provide a space for the engineer’sname, the date, and notes, but do not have any other significance and are not mandatory ina schematic, unless you use the CRefer, in which case a page border is required.
CADENCE A SIZE PAGE and CADENCE B SIZE PAGE
CADENCE A SIZE PAGE and CADENCE B SIZE PAGE are also borders that can be placedaround drawings. These borders include the Cadence logo and copyright statement, but donot have any other significance and are not mandatory in a schematic, unless you use theCRefer, in which case a page border is required. You can use the CADENCE A SIZE or BSIZE page borders for Cadence-supplied models and drawings.
CONN_BRK and CONN_GEN
You can use the conn_brk and conn_gen library bodies to create connectors in the schematic.Load the sizable pin (one pin sizable connector) as many times as the number of pinsrequired and assign the pin_number to the $PN property of each connector pin.
You use DEFINE to define text macros that are specified as properties of this body. Theproperty name is the text macro name with the value as its definition.
DRAWING
You use DRAWING to attach properties to the entire drawing. Examples of bodies attachedto DRAWING are “TITLE=xxx” and “ABBREV=xxx.”
FLAG
You can add FLAG symbols to interface signals to indicate the physical pins of a design. Flagsymbols are usually not required. However, they are required as Packager-XL output by somephysical design systems.
GND_EARTH
This is a chassis or frame ground. This is normally provided as protective GND for any circuitfault. This is also called protective earth.
GND_SIGNAL
For all the signal connections on a PCB, this provides the point of reference. This is keptseparate for POWER ground as the switching activity on this can copuple into other ground.In a single point grounding scheme, this is connected to POWER ground at a single point.
GROUND
In absence of a specific mention by the designer, this is used in a general design. It does notdistinguish between different types of grounds.
GND_FIELD
This is used with any circuit which generates radiated fields, such as RF transmitters.
You use MERGE symbols to combine a number of separate signals into a signal vectoredsignal, or to separate a vectored signal into a number of signals. This allows you to draw thevectored signal (the bus) as a single wire in parts of the drawing, and to draw it as severalsignals in other parts of the drawing. For example, an address bus called ABUS<15..0> canbe made up of ABUS<8..0> connected to a memory device, and ABUS<10..9>,ABUS<12..11>, and ABUS <15..13> connected to decoders and other control devices.
You can use a 4 MERGE merge symbol to draw each of the four signals separately on onepart of the drawing, and then merge them into a bus in another part of the design. This mergefunction is performed by synonyming the single signal name with the concatenation of theother signal names. Each merge symbol has four versions-two for merges and two fordemerges. Versions 1 and 2 have inputs on 0.2-inch centers and versions 3 and 4 have inputson 0.1-inch centers. Each merge symbol accepts different number of input signals to beconcatenated together.
You can also define other merge symbols. The HDL_CONCAT property attached to the originof the symbol classifies the given symbol as MERGE.
The versions of the 2, 4, 6, 8, and 10 merge symbols having inputs on 0.1-inch centers haveoutputs off the grid. To connect a wire to these points, use the right button on the mouse.Using versions 2, 4, 6, 8, or 10 is not advisable if you are using a tool that assumes that pinsare on the grid.
MSB TAP, LSB TAP, BIT TAP, and TAP
The TAP symbols are used to extract, or break out, a single bit from a vectored signal. Thefour TAP bodies are:
■ MSB TAP, which extracts the most significant bit from the signal.
■ LSB TAP, which extracts the least significant bit from the signal.
■ BIT TAP, which uses a relative bit number to extract a single bit from a bus.
■ TAP, which uses an actual bit number to extract a single bit from a bus.
For MSB TAP and LSB TAP, the SIZE property specifies the width of the signal to extract.
For BIT TAP, you must change the body property BIT to select any single bit from bit number0 to bit number <bus size>-1.
For TAP, you must change the body property BN to select any single bit of a bus.
The HDL_TAP property attached to the origin of the symbol classifies the given symbol asTAP.
The TAP symbol is the easiest to use tap body. The <standard> TAP symbols have the sameversions/rotations as the <tscr>TAP. The <standard>BIT TAP has the BN property attachedto the body, and only has four versions that are graphically different than the <tscr>BIT TAP.The <tscr>BIT TAP has eight versions with the BN property attached to the PIN.
It is recommended that users should primarily use the TAP body.
NOT
The NOT symbol supports the bubble checker features of the compiler. The NOT body is seenonly by the bubble checker. It does not change the assertion of a signal. If the bubble checkeris turned off, the signals on either side of the NOT symbol are synonymed together and theNOT symbol is otherwise ignored.
The NOT symbol is used to convert a signal from one assertion to the other for the BubbleChecker without a logical inversion taking place.
The HDL_NOT property attached to the origin of symbol classifies the given symbol as NOT.
ORIGIN
Concept-HDL automatically uses this symbol to indicate the origin of any symbol. You do notadd the ORIGIN symbol manually to a drawing. When you edit a .SYMBOL drawing, an originsymbol (a small X) appears at the center of the screen.
PIN NAMES
You use the PIN NAMES symbol for hierarchical design and library development. The signalnames can be moved and reattached to the hierarchical symbol and the PIN NAMES symbolcan then be deleted. The use of the PIN NAMES symbol eliminates the need to retype thesignal names or omit the local scope (\) signal property.
REPLICATE
You use the REPLICATE symbol when making models for sizeable parts. Library developersusually add this symbol to .SIM drawings. The HDL_REPLICATE property attached to theorigin of the symbol classifies the given symbol as REPLICATE.
You use the SIGN EXTEND symbol to extend an n-bit signal to a SIZE-bit signal by replicatingthe sign bit. The SIZE property is attached to the symbol. The MSB (the most significant bit)of the signal is always extended.
SIM_DIRECTIVES
You use the SIM_DIRECTIVES symbol to pass directives to the Simulator. Propertiesattached to this symbol are Simulator directives. This symbol is used infrequently.
SLASH
You can add a SLASH symbol to a vectored signal to provide a visible note of the signal width.You also use it to check the width of the parent signal. When you attach a SLASH symbol,you change the value of the SIZE property attached to the symbol to the correct value. Thecompiler checks that the value of the SIZE property for the SLASH symbol matches the widthof the signal. If the two do not match, an error is generated. The HDL_SLASH propertyattached to the origin of the symbol classifies the given symbol as SLASH.
SYNONYM
The SYNONYM symbol is a symbol with two pins of the same name. Add the synonymsymbol in a corner of the drawing and use the SIGNAME command to attach the two signalnames to be synonymed to the two pins of the synonym symbol. The assertions of the twosignals must match and the signals must have the same width. The default propertyTERMINAL=TRUE in the synonym.logic drawing tells the Compiler that this is a terminaldrawing and does not have to be expanded.
When signals are synonymed together, they become aliases for each other. Both names referto the same physical signal (net). When a signal has a very long name, it is convenient to giveit a shorter name with a SYNONYM symbol.
Two signals are synonymed when the signal names are each connected to a pin of theSYNONYM symbol, or when the signal names are connected to the same pin of any symbol.The latter condition should be avoided. Bus-through pins are also implemented by theCompiler synonym function. Two distinct pins on the symbol are given the same name andthe signals connected to them are therefore synonymed together.
This is a general power connection and is used for graphical notation. It can be any powerconnection such as power plane, a power track or any such power reference.
VCC_BAR
This is same as VCC_ARROW except for a different graphical representation.
VCC
This is a generic SUPPLY voltage indication and is used as a default by the designer.
VCC_CIRCLE
This is another variation of the basic VCC notation that used circle as the indication.
VCC_WAVE
This is a notation for applying a waveform in addition to a voltage source so that the compositewaveform is not a DC voltage.
Element Library
Overview
This library primarily contains the basic building blocks that are not part of other digitallibraries.
The type of cells can be classified into the following:
■ Resistor/Capacitor/Inductor/Transformer
■ Transistor (BJT, MOS), Diode
■ Generic Opamp, Opto-coupler
■ Voltage/current sources and other miscellaneous functions
Some of the parts in this library are taken from the bodies library. The chips.prt file is createdwherever needed.
Creating Ports
When creating an HDL Direct schematic, you must place port symbols on the page to indicatethe ports on the entity. Use the following symbols from the HDL Direct library:
■ INPORT
■ IOPORT
■ BUFPORT
■ OUTPORT
■ LNKPORT
■ AOUTPORT
After you place a port symbol, attach a wire to the pin on the port and then name the signal.This signal name is the port declaration in the VHDL and Verilog text. \I on a signal nameindicates that it is a port.
If the VHDL port type is not the same as the default type specified on your VHDL_DECSsymbol, you can attach one of the following properties to the wire:
■ VHDL_SCALAR_TYPE = scalar_typename
■ VHDL_VECTOR_TYPE = vector_typename
If the port is vectored, use the VHDL_VECTOR_TYPE property, otherwise use theVHDL_SCALAR_TYPE property.
If you plan to use custom port symbols instead of those supplied in the HDL Direct library,make sure to copy all the visible and invisible properties on the HDL Direct port symbols.
If a customized port symbol has additional properties attached to the pin, they are also copiedto the net attached to the port symbol when HDL Direct creates the SCALD connectivity file.
A VHDL and Verilog restriction prohibits you from wiring different ports of an entity together.HDL Direct gives a warning if different ports of an entity are wired together in your schematics.
The VHDL language has strict rules concerning the port associations allowed between portsof component instances within an architecture and the ports of the entity declaration.
Verilog port association rules are not as strict as VHDL. If you use the VHDL_USER=NOproperty on your VERILOG_DECS symbol, you do not need to follow the rules describedbelow.
A formal port is defined to be the port on an instance. An actual port is the port in the entitydescription.
For example, if a formal port is an INOUT port and that port is connected to ports higher upin the design hierarchy, the other ports must also be declared as INOUT ports. Likewise, if aBUFFER port is connected to ports higher up in the design hierarchy, the other ports mustalso be declared as BUFFER ports.
A common problem occurs when you want to read (within an architecture) the value of a portdeclared as an OUT. A port declared as an OUT can only be connected to ports on instancesthat are also declared as OUT. Therefore the value of the OUT port cannot be read by an INor INOUT port on an instance.
This restriction is made because an OUT port might have other drivers attached to it outsideof the architecture that affect the resolved signal value. By declaring an OUT port, theresolved signal value outside of the architecture cannot have any effect inside thearchitecture.
One way to read the value of an OUT port inside an architecture is by declaring the port asINOUT. Alternatively, you can use the HDL Direct AOUTPORT port to read the value of theOUT port.
Generating Entity Declarations from Symbols
Generating an Entity Declaration from Symbols
If the parts you are using do not have an entity declaration in the design library and you wantto use HDL Direct to generate entity declarations automatically, you can add properties toensure that an accurate entity declaration is generated. Typically, you make these propertiesinvisible in your symbol drawings. The properties can be set for:
These properties are not mandatory. However, if the properties are missing, and the entitydeclaration is not present, HDL Direct might generate an inaccurate entity declaration.
Declaring VHDL or Verilog Generic Parameters
To define VHDL or Verilog generic parameters
Attach the following property to the origin of the symbol.
GENERICxx=name:type
Where:
xx is a unique number, name is the name of the generic parameter, and type is the genericparameter type.
Declaring Port Modes
By default, every port in a symbol drawing is assumed to be an input. For every port in yoursymbol that is not an input, place one of the following properties on one of the pins on the port.
MODE=OUT
MODE=INOUT
MODE=BUF
MODE=LINKAGE
If you have 32 pins that are part of the same port (for example, A(31), A(30), …A(0)) you needto put only one of the above properties on one of the pins of the port.
Attach one of the following properties to a pin on the port.
VHDL_SCALAR_TYPE = type
VHDL_VECTOR_TYPE = type
If the port is vectored, use the VHDL_VECTOR_TYPE property; otherwise use theVHDL_SCALAR_TYPE property.
To set the default VHDL logic type of all ports for a symbol
Attach one or both of the above properties to the origin of the symbol.
You might need to include both properties if the symbol has vectored and nonvectored ports.Ports that have their own VHDL_SCALAR_TYPE or VHDL_VECTOR_TYPE properties takeprecedence over the origin properties.
If no VHDL_SCALAR_TYPE or VHDL_VECTOR_TYPE properties are attached to the originof the symbol or to one of its pins, HDL Direct uses the following defaults:
VHDL_SCALAR_TYPE = STD_LOGIC
VHDL_VECTOR_TYPE = STD_LOGIC_VECTOR
Declaring Verilog type of ports
To declare the Verilog logic type of a port
Attach the VLOG_NET_TYPE property to a pin on the port. Legal values of theVLOG_NET_TYPE property include WAND and WAR.
To set the default Verilog logic type of all ports for a symbol
Attach the VLOG_NET_TYPE property to the origin of the symbol. Legal values of theVLOG_NET_TYPE property include WAND and WAR.
HDL Direct examines all the pins that make up a port to determine the range of the port. Forexample, if pins SEL(1) and SEL(0) exist, HDL Direct declares a port SEL(1 down to 0). Youmight need to define the range of a port when there is insufficient information in the pinnames. For example, if SEL is a "sizeable" port and is declared as SEL (size - 1:0), but the symbolyou are creating is a "fixed size" version that has only the pins SEL(1) and SEL(0) in it, attachthe following property to one of the SEL pins.
RANGE = size - 1:0
This specifies the correct range for the port.
Declaring Libraries
To generate library clauses from a Concept-HDL body symbol drawing
Attach the following property to the origin of the symbol:
LIBRARYxx=libname
xx is a unique number and libname is the name of the library.
Declaring Use Clauses
To generate use clauses from a Concept-HDL body symbol drawing
Attach the following property to the origin of the symbol:
USExx=libname
xx is a unique number and libname is the name of the library.
For example, to ensure that the entity can access all names declared within theIEEE.std_logic_a1164 package in the library IEEE, give the property
USE LIBRARY = IEEE.std_logic_1164.ALL
This ensures that the following two entries are added to the entity declaration of the part:
The following libraries and their parts do not have the log_map, swift_map, hw_map views.
100e Series Devices
List of Parts
100kh Series Devices
List of Parts
10e Series Devices
List of Parts
100e136 100e445
100h644 100h646
10e136 10e197 10e445
January 2002 205 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
10k Series Devices
List of Parts
54asttl Series Devices
List of Parts
54fast Series Devices
List of Parts
54sttl Series Devices
List of Parts
54tiac Series Devices
List of Parts
10171 10172
54as8838 54as888
54f841
54s201 54s225
54ac11112
January 2002 206 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
54ttl Series Devices
List of Parts
a100e Series Devices
List of Parts
a100kh Series Devices
List of Parts
a10e Series Devices
List of Parts
a54asttl Series Devices
List of Parts
54112 54113 54114 5481
100e136 100e445
100h644 100h646
10e136 10e197 10e445
54as8838 54as888
January 2002 207 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
a54fast Series Devices
List of Parts
a54sttl Series Devices
List of Parts
a54tiac Series Devices
List of Parts
a54ttl Series Devices
List of Parts
a74asttl Series Devices
List of Parts
54f652 54f841
54s201 54s225
54ac11112
54112 54113 54114 5481
as8838 as888
January 2002 208 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
a74fact Series Devices
List of Parts
a74fast Series Devices
List of Parts
a74sttl Series Devices
List of Parts
a74ttl Series Devices
List of Parts
acmos Series Devices
List of Parts
act190 act192 act8836 act8837
f552
s471
81
4000b 4007b 4009b 4010b
January 2002 209 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
agaas Series Devices
List of Parts
ainterface Series Devices
List of Parts
amemory Series Devices
List of Parts
asttl Series Devices
List of Parts
vs8002
am7820 mt8952 scanpsc100f spt7814
27c512 am29f010 cy7c265#2d40 cy8c166#2d25
cy8c185#2d35 hm6716#2d2 hm6716#2d3 m5m23168
smj61cd16 smj61cd256l smj61cd256s smj61cd64
smj64c16 smj68ce16 tmm2089c tmm2089p#2d45
tms4461 tms44c257 upd488170
as8838 as888
January 2002 210 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
atidttl Series Devices
List of Parts
cmos Series Devices
List of Parts
fact Series Devices
List of Parts
fast Series Devices
List of Parts
ttl_552 ttl_81 ttl_8838 ttl_888
4000b 4007b 4009b 4010b 4552b
act190 act192 act8836 act8837
f552
January 2002 211 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
gaas Series Devices
List of Parts
interface Series Devices
List of Parts
memory Series Devices
List of Parts
vs8002
am7820 mt8952 scanpsc100f spt7814
am2169 am27ls191 am27ps191 am29705
b2210 b3210 bct2160 bct2163
bct2164 bct2165 bct2166 cy7c265#2d15
cy7c265#2d40 cy7c457 cy8c166#2d25 cy8c185#2d35
hm6716#2d2 hm6716#2d3 idt72215 idt72225
m5m23168 smj61cd16 smj61cd256l smj61cd256s
smj61cd64 smj64c16 smj68ce16 tms4461
tms44c257 upd488170
January 2002 212 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
pld Series Devices
List of Parts
rcamos Series Devices
List of Parts
sttl Series Devices
List of Parts
tidttl Series Devices
List of Parts
epf81188#2d232 epf81188#2d240 epf8452#2d160pga
epf8452#2d160pqfp epf8452#2d84 epm7096#2d100
epm7096#2d68 epm7128#2d100 epm7128#2d160
ac352 ac353 ac377 ac378 ac379
act352 act353 act377 act378 act379
s471
ttl_552 ttl_81
ttl_8838 ttl_888
January 2002 213 Product Version 14.2
Concept HDL Libraries ReferenceParts Without Map Views
ttl Series Devices
List of Parts
vlsi Series Devices
List of Parts
81
70108h 70116h adsp1401 adsp1410 adsp3211
adsp3220 adsp3221 adsp8018 b2011 b3011
b3018 b3110 b3120 d21064 i82188
i82351 i82359 i8289 idt7381 intc300
mc68331 mc68440p mpg68030 nc53c80 ns32008
ns32016 ns32032 ns32081 ns32082 ns32201
ns32202 ns32332 ns32382 ns32532 ns32c016
ns32c032 ns32c201 tact1010 tact8818 tact8832
tact8841 tact8847 tdc1010 thct1010 tial6302
tias8840 tlc34058 upd70108 upd70116 wtl1164
wtl1165 wtl3332
January 2002 214 Product Version 14.2
Concept HDL Libraries Reference
CPin Types
Pin Type Function Property Value
ANALOG An analog pin is a passive pin. It istypically connected to a passivedevice. A passive device does nothave a source of energy. Forexample, a resistor lead is apassive pin.
PIN_TYPE=ANALOG
NO_LOAD_CHECK=BOTH
NO_IO_CHECK=BOTH
ALLOW_CONNECT=TRUE
BIDIR A BIDIR pin is a input/output pin. INPUT_LOAD=(-0.01, 0.01)
OUTPUT_LOAD=(1.0, -1.0)
BIDIRECTIONAL=TRUE
INPUT An input pin is one to which youapply a signal. For example, pins 1and 2 on the 74LS00 NAND gateare input pins.
INPUT_LOAD=(-0.01,0.01)
OUTPUT An output pin is one to which thepart applies a signal. For example,pin 3 on the 74LS00 NAND gate isan output.
OUTPUT_LOAD=(1.0, -1.0)
TS A tri-state pin has three possiblestates: low, high, and highimpedance. When it is in its highimpedance state, a tri-state pinlooks like an open circuit. Forexample, the 74LS373 latch has 3-state pins.
INPUT_LOAD=(-0.01, 0.01)
OUTPUT_LOAD=(1.0, -1.0)
OUTPUT_TYPE=(TS, TS)
January 2002 215 Product Version 14.2
Concept HDL Libraries ReferencePin Types
TS_BIDIR A tri-state bi-directional pin. Abidirectional pin is either an inputor an output. For example, pin 2on the 74LS245 bus transceiver isa bi-directional pin. The value atpin 1 (an input) determines theactive type of pin 2, as well asothers.
INPUT_LOAD=(-0.01, 0.01)
OUTPUT_LOAD=(1.0, -1.0)
BIDIRECTIONAL=TRUE
OUTPUT_TYPE=(TS, TS)
OC An open collector gate omits thecollector pull-up. Use an opencollector to make "wired-OR"connections between thecollectors of several gates and toconnect with a single pull-upresistor. For example, pin 1 on the74LS01 NAND gate is an opencollector gate.
OUTPUT_LOAD=(1.0, *)
OUTPUT_TYPE=(OC, AND)
OC_BIDIR An open collector bi-directionalpin.
INPUT_LOAD=(-0.01, 0.01)
OUTPUT_LOAD=(1.0, *)
BIDIRECTIONAL=TRUE
OUTPUT_TYPE=(OC, AND)
OE An open emitter gate omits theemitter pull-down. The appropriateresistance is added externally.ECL logic uses an open emittergate and is analogous to an opencollector gate. For example, theMC10100 has an open emittergate.
OUTPUT_LOAD=(1.0,*)
OUTPUT_TYPE=(OE, OR)
OE_BIDIR An open emitter bi-directional pin. INPUT_LOAD=(-0.01, 0.01)
OUTPUT_LOAD=(1.0, *)
BIDIRECTIONAL=TRUE
OUTPUT_TYPE=(OE, OR)
January 2002 216 Product Version 14.2
Concept HDL Libraries ReferencePin Types
POWER A power pin expects either asupply voltage or ground. Forexample, on the 74LS00 NANDgate, pin 14 is VCC and pin 7 isGND.
PIN_TYPE=POWER
NO_LOAD_CHECK=BOTH
NO_IO_CHECK=BOTH
ALLOW_CONNECT=TRUENot listed on POWER_PINSline of the chips.prt file.
NC A no-connect, pin-on-body pin. PIN_TYPE=NC
NO_LOAD_CHECK=BOTH
NO_IO_CHECK=BOTH
ALLOW_CONNECT=TRUENot listed on NC_PINS lineof chips.prt file
ANALOG An analog pin.
UNSPEC A pin with no specific function.This pin type is often used forconnectors.
NO_LOAD_CHECK =‘BOTH’
NO_IO_CHECK = ‘BOTH’
ALLOW_CONNECT =‘TRUE’
GROUND A ground pin. If the pin is in the bodysection
POWER_PINS =(GND:<pin number>);
GROUND_NETS = ‘<pinname>’;
If the pin is in the pin section
‘<pin name>’:
PIN_NUMBER =‘(<pin_number>)’
PINUSE = ‘GROUND’;
January 2002 217 Product Version 14.2
Concept HDL Libraries ReferencePin Types
January 2002 218 Product Version 14.2
Concept HDL Libraries Reference
Index
Symbols[ ] in syntax 18
Aasymmetrical parts 85
BBody Section Properties 65brackets in syntax 18Bussed Pins 42
CCase Sensitivity 99
pin names and port names 73, 86Category Files (.cat files) 32cds.lib File 28
Commands 29chips.prt File 43
none defined 70, 83Sections 43
conventionsfor user-defined arguments 18
Creating Ports 133
DDeclaring Libraries 137Declaring Use Clauses 137DeMorgan Views 25
EElement Library 132
An Introduction 132Entity Declaration from Symbols 134