Computer System Overview

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Computer System Overview

Let’s figure out what’s inside

this thing...

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Computer Systems

Registers Interrupts Caching Input/Output Protection Summary

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CPURegisters

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Processor Registers User-visible registers

May be referenced by machine language Available to all programs - application programs and system

programs Data Registers – can be changed by user Address Registers – could be separate from data register Stack Registers – user / supervisor stacks Condition Codes – results of operations

Control and status registers May or may not be visible

Program Counter (PC) – address of next instruction Instruction Register (IR) – most recently fetched instruction MAR/MBR – memory reference registers Program Status Word (PSW) – condition codes, interrupts,

mode

Registers

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Instruction Execution

Processor executes instructions in a program Instructions are fetched from memory on at a time

STARTSTART HALTHALTFetch NextInstruction

Fetch NextInstruction

ExecuteInstruction

ExecuteInstruction

Fetch Cycle Execute Cycle

Registers

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Lots of Registers…

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Computer Systems

Registers

Interrupts Caching Input/Output Protection Summary

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Interrupts The interrupt was the principle tool available to

system programmers in developing multi-tasking systems!

Improves processing efficiency by allowing the processor to execute other instructions while an I/O operation is in progress

A suspension of a process caused by an event external to that process and performed in such a way that the process can be resumed

Interrupts

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Processing of Interrupts Classes of Interrupts

Program arithmetic overflow division by zero execute illegal instruction reference outside user’s memory space

Timer I/O Hardware failure

An interrupt handler determines nature of the interrupt and performs whatever actions are needed Control is transferred to this program Generally part of the operating system

Interrupts

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Interrupt Cycle Processor checks for interrupts If no interrupts fetch the next instruction for the

current program If an interrupt is pending, suspend execution of the

current program, and execute the interrupt handler

Interrupts

HALT

Fetch NextInstruction

Fetch NextInstruction

ExecuteInstruction

ExecuteInstruction

Check forInterrupt:

Process Interrupt

Check forInterrupt:

Process Interrupt

Fetch Cycle Execute Cycle Interrupt Cycle

InterruptsDisabled

InterruptsEnabled

START

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Simple Interrupt ProcessingDevice controller or

other system hardwareissues an interrupt

Processor finishesexecution of current

instruction

Processor signalsacknowledgment

of interrupt

Processor pushes PSWand PC onto control

stack

Processor loads newPC value based on

interrupt

Save remainder ofprocess stateinformation

Process interrupt

Restore process stateinformation

Restore old PSWand PC

Interrupts

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Multiple Interrupts

2 Choices Disable Interrupts

Disable upon entering an interrupt handler

Enable upon exiting

Allow Interrupts Allow an interrupt

handler to be interrupted Priorities?

Interrupts

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Multiple Interrupts - Sequential Order

Disable interrupts so processor can complete task

Interrupts remain pending until the processor enables interrupts

After interrupt handler routine completes, the processor checks for additional interrupts

What happens to the interrupts that occur when disabled?

Interrupts

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Multiple Interrupts - Priorities

Higher priority interrupts cause lower-priority interrupts to wait

Causes a lower-priority interrupt handler to be interrupted

Example when input arrives from communication line, it needs to be absorbed quickly to make room for more input

How does this change interrupt handlers?

Interrupts

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Computer Systems

Registers Interrupts

Caching Input/Output Protection Summary

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Storage-Device Hierarchy

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Memory Hierarchy

Registers

Cache

Main Memory

Disk Cache

Magnetic Disk

Magnetic Tape Optical Disk

More ExpensiveFaster & Smaller

BiggerSlower

Caching

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Comparative access timings

Processor registers: 5 nanoseconds SRAM memory: 15 nanoseconds DRAM memory: 60 nanoseconds Magnetic disk: 10 milliseconds Optical disk: (even slower)

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System design decisions

How much memory? How fast? How expensive? Tradeoffs and compromises Modern systems employ a ‘hybrid’ design in

which small, fast, expensive SRAM is supplemented by larger, slower, cheaper DRAM

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Memory hierarchy

CPU

CACHE MEMORY

MAIN MEMORY

‘word’ transfers

‘burst’ transfers

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Memory Cache Given:

Processor speed is faster than memory speed Execution/data localizes

Cache: Contains a portion of main memory Invisible to operating system Used similar to virtual memory Increases the speed of memory

Processor first checks cache If not found in cache, the block of memory

containing the needed information is moved to the cache

Caching

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Cache Design Cache size

small caches have a significant impact on performance

Block size the unit of data exchanged between cache and main

memory hit means the information was found in the cache larger block size more hits until probability of using

newly fetched data becomes less than the probability of reusing data that has been moved out of cache

Caching

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Cache Design Mapping function

Determines which cache location the block will occupy

Replacement algorithm Determines which block to replace Least-Recently-Used (LRU) algorithm

Write policy write a block of cache back to main memory main memory must be current for direct memory

access by I/O modules and multiple processors

Caching

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Disk Cache

A portion of main memory used as a buffer to temporarily to hold data for the disk

Disk writes are clustered Some data written out may be referenced

again. The data are retrieved rapidly from the software cache instead of slowly from disk

Caching

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Computer Systems

Registers Interrupts Caching

Input/Output Protection Summary

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Programmed I/O

I/O module performs the action, not the processor

Sets appropriate bits in the I/O status register

No interrupts occur Processor is kept busy

checking status

Input/Output

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Interrupt-Driven I/O

Processor is interrupted when I/O module ready to exchange data

Processor is free to do other work

No needless waiting Consumes a lot of processor

time because every word read or written passes through the processor

Input/Output

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Direct Memory Access

Transfers a block of data directly to or from memory

An interrupt is sent when the task is complete

The processor is only involved at the beginning and end of the transfer

What does this mean with respect to a paged system?

Input/Output

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Important example: Hard Disks

Our classrooms and labs have PCs that use IDE fixed-disks for storage of files

IDE means ‘Intelligent Drive Electronics’ The programming interface for IDE drives

conforms to an official documented ANSI standard (American National Standards Institute)

We present enough details for an example

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‘IDENTIFY DRIVE’

There exist about 40 different commands (e.e., read, write, seek, format, sleep, etc)

Some are ‘mandatory’, others ‘optional’ An example: the ‘Identify Drive’ command It provides information on disk’s geometry

and some other operational characteristics It identifies the disk’s manufacturer and it

provides a unique disk serial-number

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IDE Command Protocol

IDE Commands typically have 3 phases: COMMAND PHASE: CPU issues a command DATA PHASE: data moves to/from IDE buffer RESULT PHASE: CPU reads status/errors

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The IDE Controller

IDE Controller

CPU

system bus

Slave Drive(Drive 1)

Master Drive(Drive 0)

optional

Memory

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COMMAND PHASE

Wait until the IDE controller is ‘not busy’ Disable interrupts (to prevent preemption) Confirm ‘drive ready’ status Issue the ‘IDENTIFY DRIVE’ command

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DATA-TRANSFER PHASE

Continuously poll the Status Register until the DRQ (Data-Transfer Requested) bit is set, indicating that the data has been transferred into the controller’s internal ‘sector-buffer’ (size is 256 words)

Read the IDE Data-Register 256-times, saving the values into a memory area

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RESULT PHASE

Verify that the DRQ status-bit is now clear, indicating Data-Transfer Phase is finished

Check the ERR status-bit, to see if errors occurred, and if so, read the Error Register to obtain details about what went wrong

Re-enable interrupts (so multitasking can resume)

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Computer Systems

Registers Interrupts Caching Input/Output

Protection Summary

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Hardware Protection Why protect hardware? From what?

Shared hardware resources – memory, disk, … Errant programs

How? CPU provides 2 modes of operation

User Mode (non-privileged)Supervisor mode (privileged)

Privileged instructions can only be executed in monitor modeAll I/O instructions are privileged

Protection

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Dual-Mode Operation (Cont.) Mode bit added to computer hardware to indicate

the current mode: monitor (0) or user (1). When an interrupt or fault occurs hardware

switches to monitor mode.

Privileged instructions can be issued only in monitor mode.

monitor user

Interrupt/fault

set user mode

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Memory Protection We must not allow a program

access to memory outside of its space.

How? Add two registers Base Limit

Use the registers to check every reference

Protection

OS

Job 1

Job 2

Job 4

Job 3

0

256000

300040

420940

880000

1024000

300040

120900

Base

Limit

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Hardware Address Protection

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CPU Protection

What is there to protect? Configuration CPU as a resource

Timer Task Switching uses the timer

When process is loaded timer is setTimer is decremented each cycleWhen time is zero, an interrupt is generatedProcess is switched

Load-timer is a privileged instruction

Protection

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I/O Protection

All I/O instructions are privileged instructions.

Must ensure that a user program could never gain control of the computer in monitor mode (I.e., a user program that, as part of its execution, stores a new address

in the interrupt vector).

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Protect at all cost? If all I/O instructions are protected, how do

you perform input or output? System calls

Often the call is a trap to a ISR (Interrupt Service Routine)

Control is passed to the ISR which sets the mode bit to monitor mode

ISR verifies that parameters are correct ISR executes request, resets mode Control is returned to user program

Protection