University of Pune S.E. I.T. Subject code: 214442 Part 45 RISC and CISC Computer Organization UNIT VI Tushar B. Kute, Department of Information Technology, Sandip Institute of Technology & Research Centre, Nashik. http://tusharkute.com History of RISC/CISC 1950s IBM instituted a research program 1964 Release of System/360 Mid-1970s improved measurement tools demonstrated on CISC 1979 32-bit RISC microprocessor (801) developed led by Joel Birnbaum 1984 MIPS developed at Stanford, as well as projects done at Berkeley 1988 RISC processors had taken over high-end of the workstation market Performance Optimization With Enhanced RISC) architecture introduced w/ the RISC System/6k AIM (Apple, IBM, Motorola) alliance formed, resulting in PowerPC
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Uni
vers
ity o
f Pun
e S.
E. I.
T.
Subj
ect c
ode:
214
442
Part
45
RIS
C an
d CI
SC
Com
pute
r Org
aniz
atio
n
UN
IT
VI
Tush
ar B
. Kut
e,
Dep
artm
ent o
f Inf
orm
atio
n Te
chno
logy
, Sa
ndip
Inst
itute
of T
echn
olog
y &
Res
earc
h Ce
ntre
, Nas
hik.
ht
tp:/
/tus
hark
ute.
com
Hist
ory
of R
ISC/
CISC
19
50s I
BM in
stitu
ted
a re
sear
ch p
rogr
am
1964
Rel
ease
of S
yste
m/3
60
Mid
-197
0s im
prov
ed m
easu
rem
ent t
ools
dem
onst
rate
d on
CIS
C
1979
32-
bit R
ISC
mic
ropr
oces
sor (
801)
dev
elop
ed le
d by
Joel
Bi
rnba
um
1984
MIP
S de
velo
ped
at S
tanf
ord,
as w
ell a
s pro
ject
s don
e at
Be
rkel
ey
1988
RIS
C pr
oces
sors
had
take
n ov
er h
igh-
end
of th
e w
orks
tatio
n m
arke
t Pe
rfor
man
ce O
ptim
izatio
n W
ith
Enha
nced
RIS
C) a
rchi
tect
ure
intr
oduc
ed w
/ the
RIS
C Sy
stem
/6k
AIM
(App
le, I
BM, M
otor
ola)
alli
ance
form
ed, r
esul
ting
in
Pow
erPC
Wha
t is C
ISC?
CI
SC is
an
acro
nym
for C
ompl
ex In
stru
ctio
n Se
t Com
pute
r and
are
chi
ps
that
are
eas
y to
pro
gram
and
whi
ch m
ake
effic
ient
use
of m
emor
y. Si
nce
the
earli
est m
achi
nes w
ere
prog
ram
med
in a
ssem
bly
lang
uage
and
m
emor
y w
as sl
ow a
nd e
xpen
sive,
the
CISC
phi
loso
phy
mad
e se
nse,
and
w
as co
mm
only
impl
emen
ted
in su
ch la
rge
com
pute
rs a
s the
PDP
-11
and
the
DECs
yste
m 1
0 an
d 20
mac
hine
s.
Mos
t com
mon
mic
ropr
oces
sor d
esig
ns su
ch a
s the
Inte
l 80x
86 a
nd
Mot
orol
a 68
K se
ries
follo
wed
the
CISC
phi
loso
phy.
Bu
t rec
ent c
hang
es in
softw
are
and
hard
war
e te
chno
logy
hav
e fo
rced
a re
-ex
amin
atio
n of
CIS
C an
d m
any
mod
ern
CISC
pro
cess
ors a
re h
ybrid
s, im
plem
entin
g m
any
RISC
prin
cipl
es.
CISC
was
dev
elop
ed to
mak
e co
mpi
ler d
evel
opm
ent s
impl
er. I
t shi
fts m
ost
of th
e bu
rden
of g
ener
atin
g m
achi
ne in
stru
ctio
ns to
the
proc
esso
r. Fo
r ex
ampl
e, in
stea
d of
hav
ing
to m
ake
a co
mpi
ler w
rite
long
mac
hine
in
stru
ctio
ns to
cal
cula
te a
squa
re-r
oot,
a CI
SC p
roce
ssor
wou
ld h
ave
a bu
ilt-in
abi
lity
to d
o th
is.
CISC
Att
ribut
es
The
desig
n co
nstr
aint
s tha
t led
to th
e de
velo
pmen
t of C
ISC
(sm
all a
mou
nts o
f slo
w m
emor
y an
d fa
ct th
at m
ost e
arly
m
achi
nes w
ere
prog
ram
med
in a
ssem
bly
lang
uage
) giv
e CI
SC
inst
ruct
ions
sets
som
e co
mm
on c
hara
cter
istic
s:
A 2-
oper
and
form
at, w
here
inst
ruct
ions
hav
e a
sour
ce a
nd a
de
stin
atio
n. R
egist
er to
regi
ster
, reg
ister
to m
emor
y, a
nd
mem
ory
to re
gist
er c
omm
ands
. Mul
tiple
add
ress
ing
mod
es
for m
emor
y, in
clud
ing
spec
ializ
ed m
odes
for i
ndex
ing
thro
ugh
arra
ys
Varia
ble
leng
th in
stru
ctio
ns w
here
the
leng
th o
ften
var
ies
acco
rdin
g to
the
addr
essin
g m
ode
In
stru
ctio
ns w
hich
requ
ire m
ultip
le c
lock
cyc
les t
o ex
ecut
e.
E.
g. P
entiu
m is
con
sider
ed a
mod
ern
CISC
pro
cess
or
Mos
t CIS
C ha
rdw
are
arch
itect
ures
hav
e se
vera
l cha
ract
erist
ics i
n co
mm
on:
Com
plex
inst
ruct
ion-
deco
ding
logi
c, d
riven
by
the
need
for a
sin
gle
inst
ruct
ion
to su
ppor
t mul
tiple
add
ress
ing
mod
es.
A sm
all n
umbe
r of g
ener
al p
urpo
se re
gist
ers.
Thi
s is t
he d
irect
re
sult
of h
avin
g in
stru
ctio
ns w
hich
can
ope
rate
dire
ctly
on
mem
ory
and
the
limite
d am
ount
of c
hip
spac
e no
t ded
icat
ed
to in
stru
ctio
n de
codi
ng, e
xecu
tion,
and
mic
roco
de st
orag
e.
Seve
ral s
peci
al p
urpo
se re
gist
ers.
Man
y CT
SC d
esig
ns se
t asi
de
spec
ial r
egist
ers f
or th
e st
ack
poin
ter,
inte
rrup
t han
dlin
g, a
nd
so o
n. T
his c
an si
mpl
ify th
e ha
rdw
are
desig
n so
mew
hat,
at th
e ex
pens
e of
mak
ing
the
inst
ruct
ion
set m
ore
com
plex
. A
'Con
ditio
n co
de" r
egist
er w
hich
is se
t as a
side
-effe
ct o
f m
ost i
nstr
uctio
ns. T
his r
egist
er re
flect
s whe
ther
the
resu
lt of
th
e la
st o
pera
tion
is le
ss th
an, e
qual
to, o
r gre
ater
than
zero
an
d re
cord
s if c
erta
in e
rror
con
ditio
ns o
ccur
.
At th
e tim
e of
thei
r ini
tial d
evel
opm
ent,
CISC
mac
hine
s use
d av
aila
ble
tech
nolo
gies
to o
ptim
ize co
mpu
ter p
erfo
rman
ce.
Mic
ropr
ogra
mm
ing
is as
eas
y as
ass
embl
y la
ngua
ge to
im
plem
ent,
and
muc
h le
ss e
xpen
sive
than
har
dwiri
ng a
co
ntro
l uni
t.
The
ease
of m
icro
codi
ng n
ew in
stru
ctio
ns a
llow
ed d
esig
ners
to
mak
e CI
SC m
achi
nes u
pwar
dly
com
patib
le: a
new
com
pute
r co
uld
run
the
sam
e pr
ogra
ms a
s ear
lier c
ompu
ters
bec
ause
th
e ne
w c
ompu
ter w
ould
con
tain
a su
pers
et o
f the
in
stru
ctio
ns o
f the
ear
lier c
ompu
ters
. As
eac
h in
stru
ctio
n be
cam
e m
ore
capa
ble,
few
er in
stru
ctio
ns
coul
d be
use
d to
impl
emen
t a g
iven
task
. Thi
s mad
e m
ore
effic
ient
use
of t
he re
lativ
ely
slow
mai
n m
emor
y.
Beca
use
mic
ropr
ogra
m in
stru
ctio
n se
ts ca
n be
writ
ten
to
mat
ch th
e co
nstr
ucts
of h
igh-
leve
l lan
guag
es, t
he co
mpi
ler
does
not
hav
e to
be
as co
mpl
icat
ed.
CISC
Disa
dvan
tage
s De
signe
rs s
oon
real
ised
that
the
CISC
phi
loso
phy
had
its o
wn
prob
lem
s, in
clud
ing:
Ea
rlier
gen
erat
ions
of a
pro
cess
or fa
mily
gen
eral
ly w
ere
cont
aine
d as
a
subs
et in
eve
ry n
ew v
ersio
n - s
o in
stru
ctio
n se
t & c
hip
hard
war
e be
com
e m
ore
com
plex
with
eac
h ge
nera
tion
of co
mpu
ters
. So
that
as m
any
inst
ruct
ions
as p
ossib
le c
ould
be
stor
ed in
mem
ory
with
th
e le
ast p
ossib
le w
aste
d sp
ace,
indi
vidu
al in
stru
ctio
ns c
ould
be
of a
lmos
t an
y le
ngth
- th
is m
eans
that
diff
eren
t ins
truc
tions
will
take
diff
eren
t am
ount
s of c
lock
tim
e to
exe
cute
, slo
win
g do
wn
the
over
all p
erfo
rman
ce
of th
e m
achi
ne.
Man
y sp
ecia
lized
inst
ruct
ions
are
n't u
sed
frequ
ently
eno
ugh
to ju
stify
th
eir e
xist
ence
-app
roxi
mat
ely
20%
of t
he a
vaila
ble
inst
ruct
ions
are
use
d in
a ty
pica
l pro
gram
. CI
SC in
stru
ctio
ns ty
pica
lly se
t the
cond
ition
code
s as a
side
effe
ct o
f the
in
stru
ctio
n. N
ot o
nly
does
sett
ing
the
cond
ition
code
s tak
e tim
e, b
ut
prog
ram
mer
s ha
ve to
rem
embe
r to
exam
ine
the
cond
ition
cod
e bi
ts
befo
re a
subs
eque
nt in
stru
ctio
n ch
ange
s th
em.
Wha
t is R
ISC?
RISC
? RI
SC, o
r Red
uced
Inst
ruct
ion
Set C
ompu
ter.
is a
type
of m
icro
proc
esso
r ar
chite
ctur
e th
at u
tilize
s a
smal
l, hi
ghly
-opt
imize
d se
t of i
nstr
uctio
ns,
rath
er th
an a
mor
e sp
ecia
lized
set
of i
nstr
uctio
ns o
ften
foun
d in
oth
er
type
s of a
rchi
tect
ures
. History
The
first
RIS
C pr
ojec
ts c
ame
from
IBM
, Sta
nfor
d, a
nd U
C-Be
rkel
ey in
the
late
70s
and
ear
ly 8
0s. T
he IB
M 8
01, S
tanf
ord
MIP
S, a
nd B
erke
ley
RISC
1
and
2 w
ere
all d
esig
ned
with
a si
mila
r phi
loso
phy
whi
ch h
as b
ecom
e kn
own
as R
ISC.
Cer
tain
des
ign
feat
ures
hav
e be
en c
hara
cter
istic
of m
ost
RISC
pro
cess
ors:
on
e cy
cle
exec
utio
n tim
e: R
ISC
proc
esso
rs h
ave
a CP
I (cl
ock
per i
nstr
uctio
n) o
f on
e cy
cle.
Thi
s is d
ue to
the
optim
izatio
n of
eac
h in
stru
ctio
n on
the
CPU
and
a
tech
niqu
e ca
lled
PIPE
LINI
NG
pi
pelin
ing:
a te
chiq
ue th
at a
llow
s for
sim
ulta
neou
s ex
ecut
ion
of p
arts
, or
stag
es, o
f ins
truc
tions
to m
ore
effic
ient
ly p
roce
ss in
stru
ctio
ns;
larg
e nu
mbe
r of r
egist
ers:
the
RISC
des
ign
philo
soph
y ge
nera
lly in
corp
orat
es a
la
rger
num
ber o
f reg
ister
s to
pre
vent
in la
rge
amou
nts o
f int
erac
tions
with
m
emor
y
RISC
Att
ribut
es
The
mai
n ch
arac
teris
tics o
f CIS
C m
icro
proc
esso
rs a
re:
Exte
nsiv
e in
stru
ctio
ns.
Com
plex
and
effi
cien
t mac
hine
inst
ruct
ions
. M
icro
enco
ding
of t
he m
achi
ne in
stru
ctio
ns.
Exte
nsiv
e ad
dres
sing
capa
bilit
ies f
or m
emor
y op
erat
ions
. Re
lativ
ely
few
regi
ster
s.
In c
ompa
rison
, RIS
C pr
oces
sors
are
mor
e or
less
the
oppo
site
of th
e ab
ove:
Re
duce
d in
stru
ctio
n se
t.
Less
com
plex
, sim
ple
inst
ruct
ions
. Ha
rdw
ired
cont
rol u
nit a
nd m
achi
ne in
stru
ctio
ns.
Few
add
ress
ing
sche
mes
for m
emor
y op
eran
ds w
ith o
nly
two
basic
in
stru
ctio
ns, L
OAD
and
ST
ORE
M
any
sym
met
ric re
gist
ers w
hich
are
org
anise
d in
to a
regi
ster
file
.
Pipe
linin
g RI
SC P
ipel
ines
A
RISC
pro
cess
or p
ipel
ine
oper
ates
in m
uch
the
sam
e w
ay, a
lthou
gh th
e st
ages
in th
e pi
pelin
e ar
e di
ffere
nt. W
hile
diff
eren
t pro
cess
ors h
ave
diffe
rent
num
bers
of s
teps
, the
y ar
e ba
sical
ly v
aria
tions
of t
hese
five
, us
ed in
the
MIP
S R3
000
proc
esso
r:
- fet
ch in
stru
ctio
ns fr
om m
emor
y
- rea
d re
gist
ers
and
deco
de th
e in
stru
ctio
n
- exe
cute
the
inst
ruct
ion
or ca
lcul
ate
an a
ddre
ss
- acc
ess a
n op
eran
d in
dat
a m
emor
y
- writ
e th
e re
sult
into
a re
gist
er
RISC
Disa
dvan
tage
s Th
ere
is st
ill co
nsid
erab
le c
ontr
over
sy a
mon
g ex
pert
s ab
out t
he u
ltim
ate
valu
e of
RIS
C ar
chite
ctur
es. I
ts
prop
onen
ts a
rgue
that
RIS
C m
achi
nes a
re b
oth
chea
per a
nd fa
ster
, and
are
ther
efor
e th
e m
achi
nes
of th
e fu
ture
. Ho
wev
er, b
y m
akin
g th
e ha
rdw
are
simpl
er, R
ISC
arch
itect
ures
put
a g
reat
er b
urde
n on
the
soft
war
e.
Is th
is w
orth
the
trou
ble
beca
use
conv
entio
nal
mic
ropr
oces
sors
are
bec
omin
g in
crea
singl
y fa
st a
nd
chea
p an
yway
? CISC
ver
sus R
ISC
CISC
RISC
Emph
asis
on
hard
war
e
Emph
asis
on
soft
war
e
Incl
udes
mul
ti-c
lock
co
mpl
ex in
stru
ctio
ns
Sin
gle-
cloc
k,
redu
ced
inst
ruct
ion
only
Mem
ory-
to-m
emor
y:
"LO
AD
" an
d "S
TORE"
in
corp
orat
ed in
inst
ruct
ions
Regi
ster
to
regi
ster
: "L
OAD
" an
d "S
TORE"
ar
e in
depe
nden
t in
stru
ctio
ns
Sm
all c
ode
size
s,
high
cyc
les
per
seco
nd
Low
cyc
les
per
seco
nd,
larg
e co
de s
izes
Tran
sist
ors
used
for
sto
ring
co
mpl
ex in
stru
ctio
ns
Spe
nds
mor
e tr
ansi
stor
s on
mem
ory
regi
ster
s
Desig
ns
Refe
renc
es
Com
pute
r Arc
hite
ctur
e an
d O
rgan
izatio
n
By A
. P. G
odse
(fro
m b
ooks
.goo
gle.
com
)
Com
pute
r Org
aniza
tion
By
Ham
ache
r and
Zak
y
Com
pute
r Org
aniza
tion
and
Arch
itect
ure
By
Will
iam
Sta
lling
s
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