Computer Organization and Design Transistors & Logic - II

Computer Organization and Computer Organization and DesignDesign

Transistors & Logic - IITransistors & Logic - II

Montek SinghMontek Singh

Mon, Mar 14, 2011Mon, Mar 14, 2011

Lecture 9Lecture 9

OutlineOutline

A

B

Comp 411 Box-o-Tricks

F = A xor B

From What Do We Make Digital From What Do We Make Digital Devices?Devices? Recall our common Recall our common

thread from Lecture thread from Lecture 2…2…A controllable switch A controllable switch

is a common link of is a common link of all computing all computing technologiestechnologies

How do you control How do you control voltages with a voltages with a switch?switch?By creating and By creating and

opening paths opening paths between higher and between higher and lower potentials lower potentials (voltages) (voltages)

Load

This symbol indicates a “low” or ground potential or 0V.

This symbol indicates a “high” potential, or the voltage of the power supply (e.g., 2V, 5V etc.)

N-Channel Field-Effect Transistors N-Channel Field-Effect Transistors (NFETs)(NFETs)

D

G

S

D

G

S

+

+

- -VGS

VDS 0

Operating regions:

cut-off: VGS < VTH

linear: VGS VTH

VDS < VDsat

saturation: VGS VTH

VDS VDsat

S D

VGS - VTH

0.5V

S D

S D“ “

IDS

VDS

VGS

linear saturation

When the gate voltage is high, the switch connects. Good at pulling things “low”.

P-Channel Field-Effect Transistors P-Channel Field-Effect Transistors (PFETs)(PFETs)

S

G

D

S

G

D

+--

+

VGS

VDS 0

Operating regions:

cut-off: VGS > VTH

linear: VGS VTH

VDS > VDsat

saturation: VGS VTH

VDS VDsat

S D

VGS - VTH

–0.5V

S D

S D“ “

-IDS

-VDS

-VGS

linearsaturation

When the gate voltage is low, the switch connects. Good at pulling things “high”.

Finally… From Transistors to Finally… From Transistors to Gates!Gates! Logic Gate recipe:Logic Gate recipe:

use use complementary complementary arrangements of PFETs and arrangements of PFETs and NFETsNFETscalled CMOS (“complementary metal-oxide called CMOS (“complementary metal-oxide

semiconductor”)semiconductor”) at any time: either “pullup” active, or “pulldown”, at any time: either “pullup” active, or “pulldown”,

never both!never both!

VDD

VIN VOUT

pullup: make this connectionwhen VIN is near 0 so that VOUT = VDD

pulldown: make this connectionwhen VIN is near VDD so that VOUT = 0

We’ll usePFETs here

and, NFETshere

Gnd

CMOS InverterCMOS Inverter

Vin Vout

Vin

Vout

A Yinverter

Only a narrow range of input voltages result in “invalid” output values. (This diagram is greatly exaggerated)

Valid “1”

Valid “0”

Invalid

“1” “0”

“0” “1”

CMOS ComplementsCMOS Complements

conducts when A is high conducts when A is low

conducts when A is highand B is high: A.B

A

B

A B

conducts when A is lowor B is low: A+B = A.B

conducts when A is highor B is high: A+B

A

BA B

conducts when A is lowand B is low: A.B = A+B

A A

Series N connections:

Parallel N connections:

Parallel P connections:

Series P connections:

A Two Input Logic GateA Two Input Logic Gate

A

B

What function doesthis gate compute?

A B C

0 00 11 01 1

Here’s Another…Here’s Another…

What function doesthis gate compute?

A B C

0 00 11 01 1

A

B

CMOS Gates Like to InvertCMOS Gates Like to InvertObservation: CMOS gates Observation: CMOS gates

tend to be inverting! tend to be inverting!

One or more “0” inputs are One or more “0” inputs are necessary to generate a necessary to generate a “1” output“1” output

One or more “1” inputs are One or more “1” inputs are necessary to generate a necessary to generate a “0” output“0” output

Why?Why?

A

B

General CMOS Gate RecipeGeneral CMOS Gate Recipe

Step 1. Figure out pulldown network that does what you want (i.e the set of conditions where the output is ‘0’)

e.g., F = A*(B+C)

A

B C

Step 2. Walk the hierarchy replacing nfets with pfets, series subnets with parallel subnets, and parallel subnets with series subnets

AB

C

Step 3. Combine pfet pullup network from Step 2 with nfet pulldownnetwork from Step 1 to form fully-complementary CMOS gate.

AB

C

A

B C

One Last ExerciseOne Last Exercise Lets construct a gate to Lets construct a gate to

compute:compute: F = A+BC = NOT(OR(A,AND(B,C)))F = A+BC = NOT(OR(A,AND(B,C)))

Step 1: Draw the pull-down Step 1: Draw the pull-down networknetwork

Step 2: The complementary pull-Step 2: The complementary pull-up networkup network

FA B

C

VddA

B C

One Last ExerciseOne Last Exercise Lets construct a gate to Lets construct a gate to

compute:compute: F = A+BC = NOT(OR(A,AND(B,C)))F = A+BC = NOT(OR(A,AND(B,C)))

Step 1: Draw the pull-down Step 1: Draw the pull-down networknetwork

Step 2: The complementary pull-Step 2: The complementary pull-up networkup network

Step 3: Combine and VerifyStep 3: Combine and Verify

FA B

C

VddA

B C

A B C F

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

11100000

Now We’re Ready to Design Stuff!Now We’re Ready to Design Stuff! We need to start somewhereWe need to start somewhere

usually it’s the functional specificationusually it’s the functional specification

A

B YIf C is 1 thencopy B to Y,

otherwise copyA to YC

If you are like most engineers you’d rather see a table, or formula than parse a logic puzzle. The fact is, any combinational function can be expressed as a table.

These “truth tables” are a concise description of the combinational system’s function. Conversely, any computation performed by a combinational system can expressed as a truth table.

Argh… I’m tired of word games

C B A Y

0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Truth Table

A Slight DiversionA Slight Diversion Are we sure we have all the gates we need?Are we sure we have all the gates we need?

How many two-input gates are there?How many two-input gates are there?

All of these have 2-inputs (no surprise)All of these have 2-inputs (no surprise)… … 2 inputs have 4 possible values2 inputs have 4 possible values

How many possible patterns for 4 outputs are there? How many possible patterns for 4 outputs are there? ______Generalizing, for N inputs, there are 2Generalizing, for N inputs, there are 2(2^N)(2^N) gates gates

AB Y

00 001 010 011 1

ANDAB Y

00 001 110 111 1

ORAB Y

00 101 110 111 0

NANDAB Y

00 101 010 011 0

NOR

SU

RG

E

24

There Are Only So Many GatesThere Are Only So Many Gates There are only 16 possible 2-input gatesThere are only 16 possible 2-input gates

… … some we know already, others are just sillysome we know already, others are just silly

Do we need all of these gates?Do we need all of these gates? Nope. We describe them all using AND, OR, and NOT.Nope. We describe them all using AND, OR, and NOT.

I N P U T AB

Z E R O

A N D

A>B

A

B>A

B

X O R

O R

N O R

X N O R

N O T ‘B’

A<=B

N O T ‘A’

B<=A

N A N D

O N E

00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 01 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

How many of these gates can actually be implemented using a single CMOS gate?

We Can Make Most Gates Out of We Can Make Most Gates Out of OthersOthers

How many different gates do we really need?How many different gates do we really need?

AB Y

00 001 110 011 0

B>A

AB

y

AB Y

00 0 01 1 10 1 11 0

XOR

AB

Y

AB

Y

One Will Do!One Will Do! NANDs and NORs are universalNANDs and NORs are universal

Ah!, but what if we want more than 2-inputsAh!, but what if we want more than 2-inputs

=

=

=

=

=

=

Gate TreesGate Trees

Suppose we have some 2-input XOR gates:

And we want an N-input XOR:

A1

A3 A4 AN

A2

A

BC

A0011

B0101

C0110

tpd = 1

tpd = O( ___ ) -- WORST CASE.

output = 1 iff number of 1s input is ODD (“ODD PARITY”)

Can we compute N-input XOR faster?

N

Gate TreesGate Trees

A1

A2

A4

A3

AN

N-input TREE has O( ______ ) levels...

Signal propagation takes O( _______ ) gate delays.

log N

log N

21222

log2N

Here’s a Design ApproachHere’s a Design ApproachThree steps:Three steps:

1.1. Write functional spec as a Write functional spec as a truth truth tabletable

2.2. Write down a Boolean expression Write down a Boolean expression for every ‘1’ in the outputfor every ‘1’ in the output

3.3. Wire up the gates!Wire up the gates!

This approach will always give This approach will always give us logic expressions in a us logic expressions in a particular form: particular form:

SUM-OF-PRODUCTSSUM-OF-PRODUCTS

C B A Y

0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Truth Table

CBAACBBACABCY

Straightforward SynthesisStraightforward Synthesis We can implement SUM-OF-PRODUCTS…We can implement SUM-OF-PRODUCTS…

……with just three levels of logicwith just three levels of logic

INVERTERS/AND/ORINVERTERS/AND/ORABC

ABC

ABC

ABC

Y

AB=A+B

Useful Gate StructuresUseful Gate Structures NAND-NANDNAND-NAND

NOR-NORNOR-NOR

C

A

B

Y

C

A

BY

C

A

B

Y

zyxxyz

C

A

BY

yxyx

C

A

B

Y

C

A

BY

AB=A+B “Pushing Bubbles”

DeMorgan’s Laws

An Interesting 3-Input GateAn Interesting 3-Input Gate Based on C, select the A or B input to be Based on C, select the A or B input to be

copied to the output Y.copied to the output Y.

C B A Y

0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Truth Table

A

BY

C

If C is 1 thencopy B to Y,

otherwise copyA to Y

2-input Multiplexer

B

C

A

Y

schematic

A

B

C

0

1

Gatesymbol

MUX ShortcutsMUX Shortcuts

0101S

0101S

0101S

I0I1

I2I3

Y

S0 S1

A 4-input Mux(implemented as a

tree)

0101S

0101S

A2

B2

A3

B3

Y0

S

0101S

0101S

A0

B0

A1

B1

Y1

Y2

Y3

A 4-bit wide Mux

ABCDS

0123

YA0-3

B0-3

S

Y0-3

Mux Logic SynthesisMux Logic Synthesis

Consider implementation of some arbitrary Boolean function, F(A,B)

... using a MULTIPLEXERas the only circuit element:

A B Cin Cout

0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

Full-AdderCarry Out Logic

01234567

A,B,Cin

Cout

00010111