Computer Architecture Lecture 3: Logical circuits, computer arithmetics Piotr Bilski
Dec 27, 2015
Computer Architecture
Lecture 3: Logical circuits,
computer arithmetics
Piotr Bilski
Arithmetic-Logical Unit (ALU)
• Performs arithmetic-logical operations
• Calculations are performed on the binary system numbers (Boole’s algebra)
ALU
CU
registers
state pointers
(flags)
registers
Number representations
• Integer numbers:
• Real numbers:
6110 = 0 0 1 1 1 1 0 12
27 26 25 24 23 22 21 20
1,632812510 = 1, 1 0 1 0 0 0 1 02
LSBMSB
Integer numbers (fixed point representation)
• Representation of the unsigned number A:
• Sign-magnitude representation:
• Two’s complement (U2):
2
0
2n
ii
i asA
2
01
1 22n
ii
in
n aaA
Examples (sign-magnitude)
2110 = 000101012
-2110 = 100101012
010 = 000000002
010 = 100000002
• double zero representation
• addition and subtraction requires analysis of signs and magnitudes
Integer systems characteristics
Adding the opposite number
Additional algorithm
Subtraction
When signs of the operands are equal and result's opposite
Sign and magnitude analysis
Overflow
Additional bits filled with a sign
Additional bits = 0
MSB sign
Increase bits number
Two’s complementChange MSBNegation
OneTwoZero representations
-2n-1 to 2n-1-1-2n-1+1 to 2n-1-1 Range
Two’s complementSign-magnitudeCharacteristics
Arithmetic operations on integers (1)
Negation:
Sign-magnitude
00010101 (21)
+10000000
10010101 (-21)
Two’s complement
00010101 (21) 11101010 NEG(21)
+00000001
11101011 (-21)
Arithmetic operations on integers (2)
Conversion between lengths:Sign-magnitude 00010101 (21) 8b 00000000 00010101 (21) 16b 10010101 (-21) 10000000 00010101 (-21) 16bTwo’s complements 00010101 (21) 8b 00000000 00010101 (21) 16b 11101011 (-21) 8b 11111111 11101011 (-21) 16b
Arithmetic operations on integers (3)
Addition:Sign-magnitude
00011001 (25)
+00001101 (13)
00100110 (38)
10011001 (-25)
+10001101 (-13)
10100110 (-38)
10011001 (-25) x0011001+00001101 (13) x1110010 NEG(13)
10001100 (-12) 0001011
+0000001
10001100 (-12)
10001101 (-13) x0001101+00011001 (25) x1100110 NEG(25)
00001100 (12) 1110011 R 00001100 NEG(R)
Arithmetic operations on integers (4)
Addition:Two’s complements
00011001 (25)
+00001101 (13)
00100110 (38)
11100111 (-25)
+11110011 (-13)
11011010 (-38)
11100111 (-25)
+00001101 (13)
11110100 (-12)
11110011 (-13)
+00011001 (25)
00001100
Arithmetic operations on integers (5)
• MultiplicationUnsigned integers:
0111 (7) 4b 0101 (5) 4b
00000111000000000001110000000000
00100011 (35) 8b !!
Increasing effectiveness of the multiplication
• Every partial result can be summed at once (fewer registers!)
• Multiplying by zero is only bit shifting!
Hardware realization of the unsigned integers multiplication
Carry (C)Accumulator (A)
Example of the hardware algorithm’s work
C A Q M 0 0000 0101 0111 starting values0 0111 0101 0111 add0 0011 1010 0111 shift right
0 0001 1101 0111 move
0 1000 1101 0111 add0 0100 0110 0111 shift
0 0010 0011 0111 move
0 0010 0011 0111 result
Multiplication in Two’s complement representation
• Signed integers:1001 (-7) multiplier0011 (3) multiplicand
11111001 11110010
11101011 (-21)
Different interpretation of the binary shiftingNegative number must be represented in the two’s
complement code
Realization of the multiplication in the Two’s complement code –Booth’s algorithm
A 0, Q-1 0, LOAD(M, Q)
Bit counter = n
Right shifting A, Q, Q-1
Bit counter = bit counter - 1
A A - M A A + M
START
Q0, Q-1
STOP
Bit count.=0
YES
=01=10
=11 =00NO
Example of the Two’s complement code multiplication (7 x 3 operation)
A Q Q-1 M 0000 0011 0 0111 starting values1001 0011 0 0111 subtract1100 1001 1 0111 shift arithmetically
1110 0100 1 0111 shift arithmetically
0101 0100 1 0111 add0010 1010 0 0111 shift arithmetically
0001 0101 0 0111 shift arithmetically
0001 0101 0 0111 result
Division of unsigned integers
A 0, LOAD(M, Q)
Bit counter = n
Bit counter = bit counter - 1
Q0 1 Q0 0
A A + M
START
A < 0?
STOP
Bit count.=0
YES
YESNO
NO
Move A,Q left
A A - M
Division of integers in Two’s complement representationLOAD(A, M, Q)
Bit counter = n
Bit counter = bit counter - 1
Q0 0Q0 1
START
Oper. successful?
STOP
Bit count.=0
YES
YES
NO
NO
Move A,Q left
A A - M
signs A, M identical?
A A + M
NO YES
restore A
Example of the Two’s complement representation
division (–7/3 operation) A Q M 1111 1001 0011 starting values1111 0010 0011 shift left0010 add1111 0010 0011 restore1110 0100 0011 shift left0001 add1110 0100 0011 restore1100 1000 0011 shift left1111 add
1111 1001 0011 set Q0 = 11111 0010 0011 shift left0010 add1111 0010 0011 restore1111 0010 0011 result
Floating point representation
• Used to represent very small and very large numbers
• Form the following number:
where:m – mantissac – exponentb - base
cbmA
Examples
1.24 x 107 (1.24e7)
5.82 x 10-21
0.010110 x 2110101
0.001001 x 16101
Format of the 32-bit floating point number:
8 bits 23 bitssign
exponent mantissa
Representation of the floating point binary number
1,6328125 x 220 = 1.1010001 x 210100
10,6328125 x 2 1,265625 0,265625
00,265625 x 2 0,53125 0,53125
10,53125 x 2 1,0625 0,0625
00,0625 x 2 0,125 0,125
00,125 x 2 0,25 0,25
00,25 x 2 0,5 0,5
10,5 x 2 1,0 0
Representation of the binary floating-point number
1,6328125 x 220 = 1.1010001 x 210100
10010011 101000100000000000000000
• Exponent is a displaced number at 127, so 20 = 127 + 20 = 147 (as above)
Normalization of the floating-point number
• Exponent is changed, so the first mantissa’s digit before the comma was non-zero
• Because the non-zero number is 1, it does not have to be stored
Range and accuracy of the floating-point numbers
For the 32-bit number:
• Exponent is 8-bit, so range is +-2256
• Mantissa is 23-bit, so accuracy is 2-23 = 1.2 x 10-7
We make a compromise between the accuracy and range
Density of the floating point numbers
-n 0 n 2n 4n
negative overflow
positive overflow
zero
negative underflow
positive underflow
Standard IEEE 754
• Apllied standard of storing floating point numbers
• Refers to the 32- i 64-bit numbers
• Exponent of length, respectively, 8 i 11 bits
• Default base is 2
• Predefined formats for the indirect calculations
Special values in IEEE 754
• c = 0, m = 0 – positive or negative zero
• c = 11111111, m = 0 – positive or negative infinity
• c = 0, m 0 - denormalized number (bit on the left from the comma is zero!)
• c = 11111111, m 0 - NaN
Floating point arithmetics
Basic operations:
ba cb
ca bmBbmA ;
ba
ba
bba
bba
cc
b
a
ccba
cb
cca
cb
cca
bm
m
B
A
bmmBA
bmbmBA
bmbmBA
,)(
,)(
,)(
Addition and subtraction
1. Checking for zeros2. Equalization of mantissas3. Adding or subtracting of mantissas4. Result normalization
Example:
(123 x 100)+(456 x 10-2)=(123 x 100)+(4,56 x 100) == 127,56 x 100
Multiplying and dividing
1. Checking zeros
2. Adding exponents and subtracting shifted values from the sum
3. Checking for exponent overflow and underflow
4. Multiplication of the mantissas considering signs (sign-magnitude representation!)
5. Rounding and normalization of the multiplication result
Logical structures (1)Basic gates:
A
BY
Y = A AND B
A
BY
A Y
Y = A OR B
A = NOT Y
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
A Y
1 0
0 1
Logical structures (2)Additional gates:
A
BY
Y = A NAND B
A
BY
Y = A NOR B
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
B
Y = A XOR B
Y
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Logical structures (3)
Half-adder
A
BS
C
A B S C
0 0 0 0
0 1 1 0
1 0 - -
1 1 - -
A S
B C
Logical structures (4)Adder
A S
B C
A S
B C
Ci
A
B
S
Co
A B Ci S Co
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1
Logical structures (5)
4-bit adder
A0 B0 A1 B1 A2 B2 A3 B3
0
S0 S1 S2 S3
C1 C2 C3C4