COMPUTER-AIDED MODELING AND SIMULATION OF SWITCHING REGULATORS by SEONG JOONG KIM THESIS submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in ELECTRICAL ENGINEERING APPROVED: F. C. Lee, Chairman V. Vorperian June, 1986 Blacksburg, Virginia D. Y. Chen B. H. Cho
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COMPUTER-AIDED MODELING AND SIMULATION OF SWITCHING
REGULATORS
by
SEONG JOONG KIM
THESIS submitted to the Faculty of the
Virginia Polytechnic Institute and State University
in partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE
in
ELECTRICAL ENGINEERING
APPROVED:
F. C. Lee, Chairman
V. Vorperian
June, 1986
Blacksburg, Virginia
D. Y. Chen
B. H. Cho
COMPUTER-AIDED MODELING AND SIMULATION OF SWITCHING REGU-
LATORS
by
SEONG JOONG KIM
F. C. Lee, Chairman
ELECTRICAL ENGINEERING
(ABSTRACT)
Switching regulators are modeled as an unterminated two-
port circuit to provide flexibility in system model building.
Each functional block of switching regulators is modeled as
an independent module so that an arbitrary regulator can be
configured.
Unified models for large-signal and small-signal analysis
are developed in user friendly manner. Analysis capabilities
of switching regulator model are demonstrated using EASYS
software program.
ACKNOWLEDGEMENTS
I wish to express my gratitude to Dr. Fred C. Lee for pro-
viding the opportunity to investigate and research the topic
discussed in this thesis. The encouragement and suggestions
Dr. Lee has provided is greatly appreciated.
I wish to express my appreciation to my committee members,
Dr. D. Y. Chen and Dr. V. Vorperian for their support.
A special thanks to Dr. B. H. Cho for providing many use-
ful advices and guidance throughout the research.
With much love and gratitude, I thank my parents for their
cc , .... - --------------7 I ul 1 I l I I l I I l I I I 1 z I I I l J ~1 - VI + I V I R I w I I ·- - ---- - --- _J
(b) CIC --Figure 3.3 Current-feedback module
V 0
--
34
As illustrated in Fig.3.3(a), the op-amp and capacitor Cl are
common to both the current loop and the voltage loop. Thus, )
the control voltage (vc) represents the total error voltage
derived from both the current loop and the voltage loop.
• [CC] --- Current-injected control module(C.I.C)[ 7 l
In CIC, as shown in Fig.3.3(b), the switch current is
sensed through a current trans£ ormer. The voltage drop
across the current-sensing resistor (R) is proportional to w the switch current as described in following equations.
i. = i /n 1 S
= i. R l. w
n
(3.9)
Thus, the control voltage after summing the output voltages
of both the current-loop and the voltage-loop becomes
= - V - V E I (3.10)
Chapter 4
DIGITAL SIGNAL PROCESSOR MODELING
4.1 Introduction
The digital signal processor (DSP) converts the control sig-
nal ve from the analog feedback controller into discrete-time
pulses to control the ON-OFF of the power switch. The DSP
includes the threshold detector (comparator), the ramp func-
tion and the latch circuit.
The threshold detector compares the control signal, ve,
and the reference signal (either de or a ramp) to generate
the trigger signal for the switch command. For the multiple
loop control, the control signal, ve, is the sum of the out-
puts f~om all feedback loops. In this case, the ve waveform
already includes a ramp function (proportional to the
inductor current or the switch current). The external ramp
function is optional, it is needed to stabilize the system
operating at a constant frequency and a duty ratio greater
than fifty percent. Figure 4.1 illustrates the PWM model for
a constant-frequency control. For each different duty-
ratio-control law, such as constant frequency, constant TON
and const~nt TOFF' the PWM model is different. These dif-
f erent ,JR'odules are stored in the component module library,
as in the case of power stage models.
35
PROTECTION
dU:l CSP
·o· LIMIT
36
COMPARATOR
-.
Figure 4.1 Pulse-width-modulator (PWM)
37
4.2 EASY5 Model For Digital Signal Processor
The digital signal processor is modeled according to its
control law such as constant-frequency control--[WM], con-
stant on-time control-- [NN], and constant off-time
control--[FF].
The protection functions are also included in the model,
such as the peak-current limiter for power components and the
converter shut-down in the event of sensed abnormalities such
as over-voltage, under-voltage, or over-current beyond a
predetermined level. Nonlinearities, such as op-amp satu-
ration and duty-cycle limiter, are also included in this
module.
For the small-signal model, the transfer function from the
control signal, vc, to the duty cycle modulation, d, becomes
the simple gain , FM, which is determined according to its
control law[ 6 ].
d = FM Ve
38
4.2. 1 Constant-frequency control [WM]
For a single-loop control model, as shown Fig.4.2(a), an ex-
ternal ramp is used to implement the duty-cycle signal. The
frequency of the external ramp function is identical to the
switching frequency. For two-loop control, as shown in
Figs.4.2(b) and (c), the inductor-current or switch-current
information determines the point at which the control voltage
(vc) intersects the reference voltage (vR). The reference
voltage (vR) is a fixed threshold voltage (vTH) when an ex-
ternal ramp is not used. If an external ramp is used to
overcome the instability problem, which occurred when the
duty ratio exceeds fifty percent[ 6 l, the. reference voltage
becomes the sum of the threshold voltage and ramp voltage.
The FORTRAN implementation of this module is shown in the
flow diagram, Fig.4.3. It consists of four basic elements:
the ramp-function generator, selection of the control method,
comparator and protection. To generate the ramp function, a
normalized time (TN) is defined by using the EASYS internal
variable TIME.
where T is the switching period. s By subtracting integer N
which is generated by the library function IDINT(TN) from TN,
the normalized ramp function(TN - N) is produced.
39
r Ts---Jj
d ( t)
I I l I TON TOFF
(a) single-loop control
·-..... --
(b) SCM
(c) CIC
Figure 4.2 Constant-frequency control
40
TN = (TIHE + T )/T s s N NP N = IDINT( TN)
VR = vp(TN - N)
two loo
single loop
no VR = VR + V th V = VE ,:.
yes
VR = vth VR = VR + vth V = VE - V V = VE -VI C C
no
no
SW= OFF no
no
SW= OFF
- SW = OFF
es
RETURN SW= ON
E'Iqure 4. 3 Flow-chart for constant-frequency control
41
Then the ramp function (V ) is generated by multiplying ramp the desired amplitude. These waveforms are shown in Fig.4.4.
Since this module can handle the single-loop control and
multi-loop control (with or without external ramp function),
one of these options is selected and the appropriate refer-
ence voltage(vR) and control voltage(vc) are assigned. The
reference voltage and the control voltage are compared to
determine the status of the switch according to the switching
logic illustrated in Fig.4.2. Whenever one switching period
ends, the switch is reset to the ON position and the process
is repeated for the next cycle. Duty-cycle limiter and
overcurrent-protection logic are included in this module.
If any aforementioned abnormalities are sensed, the shut-down
command will turn off the switch. The switch status (ON or
OFF) determined in these processes, d(t), is transferred to .
the power stage to execute the corresponding state equations.
T 3 N
2
3 N
2
T s
la-------
T -N N 1
T s
T s
T s
Figure 4. 4
42
2T s
2T s
2T s
2T s
3T s
3T s
3T s
3T s
Ramp function generation
43
4.2.2 Constant-OFF-time control [FF]
In the constant-OFF-time control, regulation is achieved by
controlling ON-time interval T0N. When the two-loop control
is implemented, as shown in Fig.4.S(b), the intersection of
the descending control voltage (vc) with the threshold level
determines the end of the ON-time interval. For the single-
loop control, however, additional elements are required be-
cause the control voltage has only the output voltage
information. One possible implementation is illustrated in
Fig.4.S(a). An external ramp function is initiated at the
end of the constant-off-time interval. The intersection of
the control voltage with the ramp function determines the end
of the ON-time interval.
In the EASYS model, as shown in Fig. 4. 6, the control
voltag~, vc, and the reference voltage, vR, are determined
according to the choice of the control technique, single-loop
or two-loop control. If the switch is ON, those two volt-
ages, vc and vR, are compared to determine the instant of
turn off (Tc). Once the switch is tur~ed OFF, it will remain
for a pre-determined OFF-tirqe interval (TOFF). At the end
of the TOFF' the switch is turned ON and the on-time instant
(TR) is reset.
d(t)
d(t)
variable ON time
constant OFF time
variable TOFF ON time constant
I I variable ON time
OFF time
't
constant
44
(a) single loop control
(b) SCM
OFF time ( c) CIC
Figure 4.5 Constant OFF-time control
I
[
[
T = R SW=
45
FF --- CONSTANT OFF TIME CONTROL
two loop
slope = 0
V = V - VI C E
no
yes
TIME ON
yes
V = C
SW= OFF
RETURN
- VE
T = OFF time C
T = R ON time
yes
no SW OFF
T = TIME C
Figure 4. 6 Flow-chart for constant OFF-time control
instant
instant
46
4.3 Constant-ON-time control [NN]
In constant-ON-time control, the output regulation is
achieved by controlling the OFF-time interval. For two-loop
control, as shown Fig. 4. 7 (b), the intersection of the as-
cending control voltage with the threshold level marks the
end of OFF-time interval TOFF' For single-loop control, as
shown in Fig. 4. 7 (a), the intersection between the control
voltage and descending ramp signal decides the turn-on in-
stance. Figure 4.8 shows the flow chart of constant ON-time
control module. In this module, control logic is basically
the reverse of the constant-OFF-time control. Comparison
between vc and vR occurs during OFF-time interval, and after
a predetermined ON-time interval, the switch is turned off
and the OFF-time instant (TR) is reset.
d (t)
47
TON variable TON OFF time constant
ON time
(a) single loop control
----- - - - - ·--
[
-- -- .. -
TON variable TON OFF time constant
ON time (b) SCM
Figure 4.7 Constant ON-time control
48
NN --- CONSTANT ON TIME CONTROL
SINGLE LOOP
SLOPE = 0 Ve= - VE- VI
no yes
yes no SW= ON T = TIME R
SW= OFF T = TIME C
yes
no SW= OFF
RETURN
Figure 4.8 Flow-chart for constant ON-time control
Chapter 5
MODELING AND SIMULATION EXAMPLES
5. 1 Large-Signal Simulation Examples
Since a switching regulator is modeled as an unterminated
component to give the maximum flexibility to configure a
system, it is necessary to connect a load for the simulation.
A simple LCR load model [LO] is developed, as shown in
Fig.5.1.
The state equations are
• iL = (vl - V ) / L C
• VC = (iL - vc/R) I C
iL --+
+ L
+ vl R
VC C
Figure 5. 1 LCR load
49
50
As described in Chapter 1, a complete converter circuit
can be configured by arbitrarily choosing a power stage, a
analog feedback controller and a digital signal processor.
To demonstrate the versatility of this modeling scheme, the
following two examples are given:
• Example 1 : Buck regulator employing SCM feedback and a
constant-OFF-time duty-cycle control
Following modules are selected to model a switching regulator
system as shown in Fig.5.2.
[BC] --- buck power stage (large-signal)
[MP] --- compensator (two-pole one-zero)
[SM] --- SCM (current loop)
[FF] --- PWM (constant-OFF-time control)
[LO] --- load
The EASYS Model Description Data [BUCKCF.MOD] is shown in
Fig.5.3(a). It includes the calling of each module from the
Macro-Module Library and the interconnections between the
component modules. This is accomplished by matching the
port quantities between the input port and the output port.
-. D S P
Figure 5. 2
-=-v .I_ TH
R p
51
R C
IC I I I
I. - - -
Buck regulator employing SCM
Load
I
--, I
R
I
- - - _.J
2
52
****•***~********•·~····~•**•**•~********. *** BUCK LARGE SIGNAL<MODULAR APPROACH> ****~************************************ ** REVISED 2/4/86 MACRO FILE NAME=MACROS •LIST MACRO COMPONENTS=BC,LO,FF,SM,MP MODEL DESCRIPTION LOCATION=12,BC, INPUTS=LO<IL=I2>,FF(G=IG) LOCATION=17,LO, INPUTS=BC(V2=V1> LOCATION=34,SM, INPUTS=BC(VL=VL> LOCATION=36,MP, lNPUTS=BC(V2=VO> LOCATION=43,FF, INPUTS=SM<VI=VI>,MP(VE=VE),BC<IL=IL> END OF MODEL PRINT
Figure 5.3 (a) User input model description data
[BUCKCF.MOD]
3 4 5 6 7
********** ********** * * V2 BC ,,v1 * * * BC * * LO * * 12 •<=-=-=========================,•====================,•===:::-+ 17 * * *======>============>=========================) * * ********** IL LOI =12 I l **********
A I I l l Q FF =I I I I I I I I I I l I
21 123 124 25 126 27 I I l l I lVL BC =VL l V2 BC =VO I l l V V 1 l ********** ********** l I * * * * I I * SM * * MP * 3 I I 33 * 34 * 35 * 36 * 37 I I * * * * IL BC =IL I ********** ********** I V I I I ********** VI SM =VI I I * * VE MPI =VE l <=======* FF +•.===============· =================
42 * 43 * 44 45 46 47 * * **********
52 54 55
Figure 5.3 (b) EASYS generated model configuration [BUCKCF.MGL]
56 57
LO
FF
COMPONENT
BC
LD
PARAM~lLR NAME (AND DIMENSION DATA FOR VECTOR AND MATRIX PARAMEfFRS)
(a) load resistance R (b) output voltage v 2 (c) inductor current iL
58
• Example 2: Buckjboost (Flyback) regulator employing CIC
and a constant-frequency control
Following modules are selected to model the circuit shown in
Fig.5.8.
[FB] --- buck/boost power stage (large signal)
[MP] --- compensator (two-pole one zero)
[CC] --- CIC (current-feedback loop)
[WM] --- PWM (constant-frequency control)
[LO] --- load
The EASYS Model description data and the EASYS generated
system configuration are shown in Fig.S.9(a) and (b), re-
spectively.
Fig.5.10.
list.
The input data requirement list is shown in
Figure 5.11 is the user input Analysis Program
Figures 5.12(a)-(c) show the simulation results at steady
state. Transient responses when load resistance is decreased
ten percent at lms are shown in Figs.5.13(a)-(b)
59
Load
I L ____________ J
d
J_
'-------1 D S P
..I. /Vv1
Figure 5. 8 Flyback converter employing CIC
60
*************************************** ** FLVBACK LARGE SIGNAL(MODULAR APPROACH) ******************~~******************* ** REVISED 12/8/85 MACRO FILE NAME=MACROS *LIST MACRO COMPONENTS=FB,LO,CC,SM,MP,WM MODEL DESCRIPTION . LOCATION=12,FB, INPUTS=LO<IL=I2),WM(IG=GG> LOCATION=17,LO, INPUTS=FBCV2=V1) LOCATION=34,CC, INPUTS=FB(PHI=IL> LOCATION=36,MP, INPUTS=FB(V2=VO) LOCATION=43,WM, INPUTs~cccvI=VI),MP(VE=VE) END OF MODEL PRINT
Figure 5.9 (a) [FLYBCK.MOD]
1
11
21
31
41
51
2 3 4 5 6 7
********** ********** * * V2 FB ::Vt * * * FB * * LO * * 12 *<============================: =====================: ====>* 1 7 * * *=====::;:=============::>========== =======-=-====-====) * * ********** IL LO =12 I I ********** A I I I IQ WM =GG I I I I I I I I
21 23 124 25 126 27 I I I I PHIFB =IL I V2 FB =VO I I V V I ********** ********** I * * * * I * CC * * MP *
31 33 * 34 * 35 * 36 * 37 I * * * * I ********** ********** I I I I ********** VI CC =VI I I * * VE MPI =VE I <=======* WM *<================================
The EASYS Model description data and the EASYS generated
system configuration are shown in Fig. 5. 15 (a) and ( b), re-
spectively. The input data requirement list is shown in
Fig. 5 .16. Figure 3 .17 is the user input Analysis Program
list.
Gain characteristic~ of audiosuceptibility and output
impedance of converter is displayed in Fig.5.18.
To obtain the loop-gain characteristics the system path
is disconnected in the PWM small-signal module and a signal
is injected at the disconnected point. Transfer function
between disconnected points becomes loop-gain. The voltage-
loop and current-loop loop-gains are achieved by freezing the
current-loop module and voltage-loop module respectively.
The loop-gains of the voltage-loop, current-loop, and total
loop are shown in Fig.5.19, Fig.5.20 and Fig.5.21.
68
,. u
2 X 1
____ _.2x2
... .... I y ... ,. ,. u d U=O ____ _.2x2 ____ _.2x1
+
A
X
+ ,. I ,...
d .... ,. d U=O
2 X 1
Hdx
FM
___ ,..1x2 ___ _., X 2
Figure 5. 14 Small signal transfer function model of switching regulator
69
***~*****~*****~•************************ *-1:•i;o BUCK SMALL-SiGNr!>.L.'.MOnlJLAR • (CONST. OFF-TIME CONTROL, SCMI ***************************************** ** REVISED 5/4/36 MACRO FILE NAME=MACROS LIST MACRO COMPONENTS=UK,LO,MP,SM,PW MODEL DESCRIPTION LOCATION= 12, UK, I NPUTS=LO I IL= I 2), rw <DH=D I LOCATION=17, LO, INPUTS=UK I V2=\J 1 l LOCATION=36,MP, INPUTS=UKIV2=VOl LOCATION=34,SM, INPUTS=UKIIL=ILl LOCP.T I ON=43, PW, INPUTS=~1P I VE=VE >, SM I VI=VI I END OF MODEL PRJNT
Figure 5.lS(a) User Input Model Description [BUCKS.MOD]
~••******* ********** * * _V2 UK =V 1 * • • UK * * LO • * 12 •<================================================-==-=>• 17 * * •===================>=========================> * * ********** IL LO =12 I I ********** A I I
I DH PW =D I I I I I I I I
21 23 124 25 126 27 I I I 1 IL UK =IL I V2 UK =VO I I V I)
I ********** ********** I * * * * I * SM * * MP •
3 I 3::3 * 34 * 35 * 36 * 37 I * * * * I ********** ********** I I I l ********** VI SM =VI I I <:- * VE ~1P I =VE I <=======• PW *<================================
4;? * 43 * 44 45 46 '17
Figure 5.lS(b) System Configuration Diagram [BUCKS.MGL]
PR It•Jl,-ER PL.!:tl-S DNLINE PLOTt3 SS Pl\F~Ar'!El.E.R;:::f.)f-1 ss START~o.ss ~;~1 POII\JTS=5; :3·r1:./;I)"Y s~r/\"TE 1·t;:· r-1;1;\11\.},;'iL. ~::;r: l'-1L.L:
r-:· F{ E>3 ;¥! i r~l:.: 6 . 2 _ r=·r~ t::,~ i'1A X:::=:J. E ~:.1 ·}f· I j\fT CfJi\rrF!CJL.S::· ~IL LG=O,VC l.O=O -ri.:.: Ii\J;=itJ-r~··\.J ·1 l)!-\1 -:·:~ O{Jl"l~lJ .. r:::::\i2 !Jt-<~ TRANSFER FUNCllON TF INPUT=IL LO,lF OUTPUT=V2 UK rR t~h1s:-:;·r-:.R r,:t._1~.:c 1·• J cJr.,-1 !_ I f\JEl\F~ t::,p~f~~L. ~l:3 I~~: PARAMETER VALUfS ;\IN Pl,J::.-c(), MM P~•J::-. ·J C I p I.or~=(.) . 7·•r::-I f .. ;p(J i ==\; .... .) r•t--;~ -~.!~ 11i . .11·F1 l . .i·1· _:.}-•!D f-4 t~J TRANSFER FUNCTlOM PARAMETER VALUES C\/ P\,J:c:c(}. , CJ r,~.J~. J. -rr-~.L\f·.ISt=EF~ FtJNCT J CJ~-! ;":, _,:.\ r~ /':., 1-/!F:-r t'.::.· f~ \/ r"-1 L 1,..1r·_ rj .--. \.' p !;..,J::-.: .• t . 'T ?f\t,1sr:c:~ ;:1Jhtc.~·1 :; C}t·:
Figure 5.17 Analysis Input Program [BUCKS.ANC]
, ... ' ..
;""""T"l ....,.I "'T""I '""!"'Tl '"T""'l'l I i~--:--r-l l'"T""! i 1-:""'!'i ! 1-----;--rl-,-i T""""I I i"T'T'li i -----;I """Tl-Ii":', i~! ! !----;-;I-,-! -:-:-11 r-r,! ! ! I i i il!ii iii il I I ii I I I !ii' i ii 11!1
j" ·1 · 'ill! ,; I .i.-+--r-t-H-M' +-0 -.!.I I I! !I !:11i,, i I 11liii
I :!, I . I: ! 8 I ! I !I -~-i---+--W-l-W+L--+-~~++--+-++~-4--+-~~,+-~TiT:Til,~J
! I Iii - 8 z . -~~-+-++~++---+-+++Hi-tt--t--+-++mH+--+--t-t-+r+Hrr-t--HTitm f§ I
8 _____,.......,.........11,.......,.i I i .--I......--.--.~, .,..,..,.,.1 __ .,....._..,..,.i I ......... ! 1 ---1 ......... 1 i-l 1 __,........,.........,....._..
8 1 ! I I ! Ii I I I I! Ii o+--~~...;....;..:....;____....:....__:.__;___.;._~-;.__.,.....___:__:__;__;__:_.:.;_____;_~L..;....;....;._;__:_;__~__:__:_~
ID i I' ' I I I Ii i I : ':I' I I I lj
n;.,...__..__,...-1 1 I : 8 .... ~--+-+--+-+++-+++--+-+--+-+-H-,-µ-~+4--!-~-----+---+-H--H~-+-~~
11 I I I !i I I I I I I Ii I I! I I I I Ii I I Ii I ! I I I I
' I I• I II : ; : ; ''.I ' ' ! I I 1 1, ' I Ii I ,
l" I I 1.E+2 1.E•3 1.E+4 1,E+S
FREQ CHZ)
111 ! II I ! T 111' 'i I II 11 11., I, 111 I I 1, II 11,,
111111 ,I 11~-~ll.i! i!ll!II ii Ii ID t=t:•~,~i II ===rtli i ~,I•~;,, ~I j8\)-f,-: Ii ~,, ~i I!~,. +-I ~i~I ! : I
,_ I I I \Ii Ii i i i Iii I Iii i 8~-t-,_-+-,H1!~:!~i!t--+,-+-++l4i 1~,-1-+1 +!~1~41~ll-+-W,1l4:.w:!4[!!~~1-U-~!!~il I i iii ilii I I ii 1i1i i i Iii t+ , ! : 1 i !:i: ! 1 1 I 1 Ii!
This thesis introduces the modular approach for the mod-
eling of the switching regulator using EASYS software pro-
gram. The switching regulator is divided into the power
stage, analog feedback controller, and digital signal
processor according to its function. Each functional block
is modeled as a independent module and a regulator is con-
figured by collecting appropriated pre-defined modules which
are stored in macro library.
The converter power stage was modeled with unterminated
two-port model using hybrid-g parameters. The large-signal
model of power stage has three sets of matrices coefficients
and appropriate sets of matrices are selected according to
the status of duty cycle which is determined by the digital
signal processor module.
state equations are used.
For small-signal model, averaged
Four power circuit topologies,
buck, boost, buck-boost(flyback) and forward converter, are
modeled.
The analog feedback controller was modeled with two
seperated modules, voltage feedback compensator module and
current feedback module. Transfer function model was chosen
so that it can be used for both the small-signal and large-
76
77
signal model. For the voltage feedback compensator, three
commonly used compensators were modeled. For the current
feedback module, SCM and CIC schemes were modeled.
Three different control law, constant frequency control,
constant ON-time control and constant OFF-time control were
modeled for the digital signal processor block.
Switching regulator large-signal model performed time-
domain simulations for the cases of steady-state and step-
load transients. It was demonstrated that EASYS small-signal
model can be used for the transfer function analysis of
switching regulator such as audiosuceptibility and input
output impedance. Frequency response of system loop-gain was
also presented for stability analysis. Other analyses are
possible using the EASYS Analysis capabilities such as Root-
locus, Steady-state analysis, Linear model generation, opti-
mal controller synthesis, and etc.
Possible future work includes the improvement of numerical
integration method. In this time-domain simulation, ineffi-
cient fixed step integrator and very small step sizes are
used because switching waveform has very steep rate at the
switching instant.
APPENDIX I
Macro Component Descriptions
This section describes a set of EASYS macro components
developed in this study. Major equations, a circuit model
and a program listing are provided for each macro component.
The macro components are listed in the following table.
Macro Component Name
BC
BT
FB
FW
UK
ST
BB
WD
TABLE OF MACRO COMPONENTS
Description
- 'CONVERTER POWER STAGE LARGE-SIGNAL MODELS -
Buck Converter Power Stage
Boost Converter Power Stage
Buck/Boost Converter Power Stage
Foward Converter Power Stage
- CONVERTER POWER STAGE SMALL-SIGNAL MODELS -
Buck Converter Power Stage
Boost Converter Power Stage
Buck/Boost Converter Power Stage
Foward Converter Power Stage
78
Macro Component Name
DG
MP
PZ
SM
cc
WM
FF
NN
PW
LO
PT
79
Description
- COMPENSATOR MODELS -
Lead-lag Compensator
Two-pole One-zero Compensator
Two-pole Two-zero Compensator
- CURRENT-FEEDBACK LOOP -
SCM Current Loop
CIC Current Loop
- PWM MODELS LARGE-SIGNAL -
PWM (Constant Frequency Control)
PWM (Constant Off-Time Control)
PWM {Constant On-Time Control)
- PWM MODELS SMALL-SIGNAL -
PWM
- LOAD MODELS -
LCR Load
Constant Power Load
V
I
IQ
Vl
12
IQ
C
L
RC
RL
V2
Il
IL
vc
IS
VL
80
BC BUCK CONVERTER POWER STAGE
(LARGE-SIGNAL)
INPUT
variable
variable
variable
parameter
parameter
parameter
parameter
OUTPUT
variable
variable
state variable
state variable
variable
variable
R C
C
input
input
V
I
voltage
current from
switching function
load
(if switch is on, IQ=l) (if switch is off, IQ=O)
capacitance
inductance
capacitor effective resistance
inductor effective resistance
output voltage
output current to source
inductor current
capacitor voltage
switch current
inductor voltage
Volts
Amps
Farads
Henries
Ohms
Ohms
Volts
Amps
Amps
Volts
Amps
Volts
EQUATIONS
For IQ= 1:
[ -(RL+RC)/L
1/C
RC
1
For IQ= 0, IL> 0:
• [ I: 1 = r-(RL+RC)/L
VC 1/C
RC
0
For IQ= O, IL= 0
81
-RC/L] [ Vl ] -1/C 12
-1/C
82
***************•R**R~~R*****~•**~* ** LARGE SIGN~L MODEL OF BUCK(W/0 LOAD> POWER STAG~ ONLY
**************************************** ** REVISED 1?./3/85 MACRO FILE NAME~MACROS DEF I NE M1\CRO=:ftC MACRO INPUTS:,
C L RL RC IG Vl 12 * IG SWITCHING FUNCTION * IQ=l (SWITCH;ON) * IQ=O <SWITCH;OrF)
* V1 INPUT VOLTAGE * 12; INPUT CURkENT<r-ROM LOAD) MACRO OUTPUTS:: IS IL ILL VL VC V2 11
* IL; INDUCTOR CURRENT<STATE> * VC; CAPACITOR VOLTAGE<STATE> IS; SWITCH CURRENT * ILL; INDUClOR CURRENT(DUMMY> * VL TRANSF-ORMER VOLTAGE * V2 OUTPUT VOLTAGE * 11; OUTPUT CURRENT<TO SOURCE)
MACRO CODE MACRO STOP SORT *i:--1:·*
IF(DABS(IG BC--). LT. 1. E-10)THEN IF ( IL BC--. L.E. 0. ) THEN
MACRO ILLBC --= 0.
DERIVATIVE, IL BC--=O.
****
*
GOTO H· .. 77 ~LSE=.
TOFF ***** A11=-CRL BC--+RC BC--)/L BC--A12=-l/L iiC·• · A21=1/C BC--A2~!==0. Bl 1=0 B 12=RC BC:··-/L BC --B21=0. B22=-1/C BC--C11=RC IiC·--C12=1 C21=0 C22=0 DlJ=O D12=-RC BC--D21=0 D22=0 IS BC--::.00
END IF ELSE
TON*** All=-<Rl. A12:::-1/L A21=1/C
HC·-·-+RC BC--> /l i!C ---
HC ·•·-
BC--
A;!;'= 0 B 1 l = t / l Ji(: ···· B 12=HC I<C - · /I I•C: ·-82 J :=O 822=-1 /C -C11=RC HC --C12=1 C21=-1 C22=0 D11=O D12=-RC BC-·-D21=O D22=0 IS BC--= 0 JL BC--END IF
MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION= 22, BC END OF MODEL
Vl 12
84
BT BOOST CONVERTER POWER STAGE
(LARGE-SIGNAL)
v2
Vl Il R
C
12 IL CI IQ VL 0 0
INPUT
Vl variable input voltage Volts
I2 variable input current from load Amps
IQ variable switching function (if switch is on, IQ=l) (if switch is off, IQ=O)
C parameter capacitance Farads
L parameter inductance Henries
RC parameter capacitor effective resistance Ohms
RL parameter inductor effective resistance Ohms
OUTPUT
V2 variable output voltage Volts
Il variable output current to source Amps
IL state variable inductor current Amps
vc state variable capacitor voltage Volts
IS variable switch current Amps
VL variable inductor voltage Volts
EQUATIONS
For IQ= 1 :
RL/L
0
0
1
For IQ= 0, IL> 0:
-(RL+RC)/L
1/C
RC
0
For IQ= 0, IL= 0
85
1
0
+
+
1/L
-1/C
1/L
86 *·**********~****•*************~~« i. * LAt•u.,;E SI GNl'.L l'lrlDEL OF DIJOST ( W/Cl UJf'\IJ) * POWER S I l\Gl:. ONI. Y * REVISED 11/19/8~ ******************************************* MACHO FILE NAM~=MACROS DEFINE M/'>.CRO= HT MACRO INPUTS=-
INDUCTOR CURRENT<FROM POWER STAGE> (FLUX IF BUCK/BOOST> CURRENT TRANSFORMER TURNS RATIO IF FLYBACK: POWER STAGE PRIMARY# OF TURNS OTHERWISE NP=1 IF FLYBACK; POWER TRANSFORMER PRIMARY INDUCTANCE OTHERWISE LP=1
OUTPUTS==VI * VI; CIC OUTPUT CONTROL VOLTAGE * MACRO CODE MACRO STOP SORT * VI CC--=NP CC- /LP CC--*
& IL CC--•RW CC--/NI CC--* MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION=22,CC END OF MODEL
VE
VI
TI
VP
VQ
ER
VR
vc IQ
106 WM PWM(CONSTANT FREQUENCY CONTROL)
(LARGE-SIGNAL)
::~~---_-_- _.-M~.,_ __ WM __ :--IQ-•
INPUT
variable voltage-loop error voltage
variable current--loop error voltage
parameter switching period
parameter amplitude of external ramp
parameter thershold voltage
parameter reference voltage of op.amp.
OUTPUT
variable reference voltage
variable total control voltage
variable switching function
EQUATIONS
VR =VP* {TN - N) + VQ
VC = - VE - VI
IF VR > VC, IQ= 0
Volts
Volts
Seconds
Volts
Volts
Volts
Volts
Volts
107 ********************•****~~******~ *• PW. M <CONSIANT F~EOUENCY)*~• ***~***************•*•**~•~~*****~** MACRO FILE Nl'.MF= M(\,CHOS r>fT I NE MACHO=- \.-JM MACRO I NPUTS 0
* * * * * * * * * * * * *
TI VP VO ~R CIC SCl-1 VE VI EPS vex VCN IL X DMN DMX VE ; VI ; CIC; SCM;
TI VP VG ER
AMPLIFIED ERROR VTG(FROM COMPENSATOR> INPUT VOLTAGE FROM CURRENT FEEDBACK MODULE IF ClC, CIC:::1 OTHERWISE CIC::.:O IF SCM, SCM=l OTHERWISE SCM=O SWICIUNG INTERVAL AMPLITUDE OF EXTERNAL RAMP ( IF EXT. RA,1P NOT USED, VP::.:O) THRESHOLD VOLTAGE REFERNCE VOLTAGE OF OP.AMP
MACRO OUTPUTS=-
* * * * I}
* i:·
VR VC TN vs VR vc IO
EXTERNAL RAMP VOLTAGE TO'I AL CONTROL VOLT AGE SWITCHING FUNCTION ( Ir- SWITCH=ON, IG=1) CIF SWITCH=OFF, IG::.:O)
IFCG FF--.LT.EPSFF-->THEN IF<<TIME-TC>.GE.TOFFF-->THEN Tf~:-T l Mt-Ci r-r-- -:-1
ENn lF ELSE VR FF--=SLPFF--*(TIME-TR)+VTHFF--
IF(VR FF--.GE.VC FF-->THEN G FF ---=-0 TC=-TlME l:-NJ> Jr·
END IF +++22 CONTINUt:.
IF<IL FF·•-. GE. ILMFF--)0 FF--~o MACRO RESUME sorn END OF MACRO MODEL DESCRIPTION LOC.-.\TION= 22, r-F END OF MOf>EL. *
110
PWM(CONSTANT ON-TIME CONTROL) (LARGE-SIGNAL)
NN .,
VI NN --
INPUT
VE variable
VI variable
TOF parameter
SLP parameter
VTH parameter
ER parameter
OUTPUT
Q variable
VR variable
vc variable
EQUATIONS
vc = - VE - VI
VR = V(RAMP) + VTH
IF VR < VC, Q = 1
Q -
voltage loop error voltage
current loop error voltage
constant off-time interval
slope of external ramp
threshold voltage
refernce voltage of op.amp.
switching function
reference voltage
total control voltage
Volts
Volts
Seconds
Volts/sec
Volts
Volts
Volts
Volts
111 *********•******************~****•****~ * p l,J M ( CONST fo.Nl OM l 1 ME CClN"I nm ) ***************~~********************** MACRO FILE NAM[•: M1~CROS DE.-I NE NN MACRO I NPu·r S=·
VE VJ TON FPS
ER CIC *
Il VTli SCl'l
l l M
* * * * * * * * * * * *
VE ;AMPLIFIED ERROR VTG(FROM COMPENSATOR> VI ; INPUT VTG FROM CURRENT FEEDBACK MODULE
CIC; IF CIC, CIC==l OTHERWIS~ CIC:.;Q
SCM; IF SCM, SCM=l OTHERWISE SCM=O
.TON ; CONSTANT ON TIME INTERVAL SLP; SLOP OF EXTERNAL RAMP
( IF EXT.RAMP NOT USED,SLP=O> VTH; THRESHOLD VOLTAGE ER; REFERNCE VOLTAGE OF OP.AMP
MACRO OUTPUTS:: VR VC G
* * VR; EXTERNAL RAMP VOLT~GE PLUS THRESHOLD VTG * VC; TOTAL CONTROL VOLTAGE * G; SWITCHING FUNCTION * <IF SWITCH=ON, 0=1) * (IF SWITCH=ONN,G=O) * TC; ON TIME INSTANT * TR; OFF TIME INSTANT MACRO CODE MACRO STOP SQRT **~·* * **** VC NN--= -VE NN---CICNN--*VI NN---
& SCMNN--t!-VI NN --****""* IF<TIME.GT.EPSJGOTO +-~+11
~:-\) ; I t--~ P l) T \} 7 ·-r:;: r=-F0! l] fVj C O i'1f r~ E !'.IS l'i "i C1l1 }'•·;[)I) t.J L. f"? ):~\) I j I f\!f1 t}l"" '-iT(;: i~:-r{[!}"''t c:.t}F:RE:J\}7 .. ··--L..OCtP r·t[}l)(_.J{ __ f:~ ~::-r: 1~ .. , : P t•Jt-·! (~r\ I j\J r-t.)._) j 1r·J\Jr:c·r1c1i\J l./CJL ·rt\~;r: r·I)~-f ; l)t}·ry· f-~c~'-f} Cl t:-i -:J) _\ 'f)i,)-r ~{ R l-\-f IO< I}t)rltl:-·{''{) 1\11\(:f-::CJ C:tJ-i)E i'-1/\CRlJ s-rOf 1 '.J[lf{"T fZ·
HD FH-··J:'.·(C\' pt,i-···tc\/E:. Fi/J-•-·+ :~,: C: J P !rJ----~-:~) I F1 !1J ~ .... )
DH PW--=NN PW--*HD PW--~MM PW--~V~ PW--************************ MACRO RESUME SORT END OF i'-1,\CRCJ MODEL DESCRIPTION LOCATION= 22, rw ;::ND DF MOD!.:.L
I
R-L-C LOAD
L
V
C
INPUT
Vl variable
RA parameter
RB parameter
L parameter
C parameter
TC parameter
OUTPUT
IL state variable
vc state variable
R variable
EQUATIONS
For TIME< TC
For TIME TC
R = RA
R = RB
• IL= ( Vl - VC) / L •
114
R
input bus voltage
resistance
resistance
inductance
capacitance
time for step change
inductor current
capacitor voltage
resistance
VC = ( IL - VC / R) / C
LO
I
Volts
Ohms
Ohms
Henries
Farads
seconds
Amps
Volts
Ohms
115
****************************~*** ******** LOAD MODE· L **-f.·******* ***************************** MACRO FILE NAME~MACROS DEFINE MACRO=,L.O MACRO INPUTS= V1 RA RB
* * Vt * RA * RB * TC * MACRO MACRO MACRO *
L C TC
INPUT VOLT~GECFROM POWER STAGE) RESISTOR VALUE DEFORE STEP CHANGE RESISTOR VALUE AFT~R STEP CHANGE TIME FOR SlEP CHANGE
OUTPUTS= IL VC R CODE STOP SORT R LO--: RA LO--· IFCTIME.GT.TC LO-->R LO--~RB LO--
*STATE EQUATION MACRO DERIVATIVE, IL LO--=(Vl LO-- - VC LO--)/L LO--MACRO DERIVATIVE,VC LO--~<IL LO-- - VC LO--/R LO--)/C LO--* MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION=25, LO END OF MODEL
116
CONSTANT POWER LOAD PT
... __ P_T __ : __ I_L_>
INPUT
VL variable input bus voltage Volts
PW1,PW2 parameters constant power values Watts PWO
PC parameter if PC=l, const. power if PC=O, time varying power if PC=2, time varying power
VR parameter minimum voltage to Volts maintain const.power
SW parameter slope of time varying power Watts/sec
OUTPUT
IL variable load current Amps
PW variable load power Watts
EQUATIONS
For PC = 1 : For PC = 2 :
PW = PWl ( IF TIME < TC ) PW = PWl ( SW* TIME ) PW = PW2 ( IF TIME>- TC ) PW = PW2 ( IF PW~ PW2 )
For PC = 0 :
PW = SW* TIME+ PWO
117
MACRO FILE Nf\t•ff· == MACr-.<OS ********************************~************************ T>EF INE MACRO :· fJ"I * LOAD MODl-: L * INrUT IS BUS VOLTAGE <VL) AND POWER <PW) OUTPUT IS !(LOAD> * **** FOR SlEP POWER CHANGE I PC PT= 1. **** FOR RAMP CHANGE OF POWER I PC PT ==O. OR 2. * PC PT= 0: PW= SW* TIME+- PWO * PC PT= 2: PW= PW1 - <SW* TIME) MACRO INPUTS= VL
vr~ MACRO OUTPUTS~ IL MACRO CODE MACRO STOP SORT
PO TC PW
Pl-ll SW SL
PW2
IF < PC PT -- . EG. 1. ) GO TO +H-23 IF ( PC PT--. EG. 2. >GOTO +++43 PW PT--= SW PT--*TIME PWOPl--IL PT-·· ::,;. PW Pl-- / VL p·1 -·-GOTO ++-:33
* STEP CHANGE OF POWER AT TIME= TC PT -i-++23 CONTINUE
* DUMMY STATEMENT +-++53 PW PT --- =- PW Pl -·-MACRO RESUME SO:<l E.ND OF MACRO ************·~*************'**************************** MODEL DESCRIPTION LOCATION=42, Pl END OF MODEL Pf<lNT
APPENDIX II
Procedure of EASY5 Programming
In this section, one example of a switching regulator
system is modeled and simulated to show users how to apply
the macro component models. In addition, the general proce-
dures of system-level modeling and simulation are briefly
explained. The EASYS commands used in this example are the
commands used in an interactive mode.
Step 1. Write Model Description Statements
Once required component models and their interconnections
are identified, appropriate macro components and/or standard
components are collected from the macro component model li-
brary and the EASYS standard component library.
As shown in Fig.A.l, the EASYS system model[BUCKCF.MOD]
can be described with simple mnemonic statements. The LO-
CATION command phrase indicates the start of a new component
in the system model. This command must be followed by a nu-
meric value phrase that specifies the location of the compo-
nent on the model schematic. In the example of Fig.A.l, the
location number of the Buck power stage [BC] is 12 and the
load [LO] is 17, etc. The location number phrase is followed
by the name of the component at that location. A LOCATION
statement must be given only once for each statement.
118
119
*** BUCK LARGE SIGNAL(MODULAR APPROACH) ***************************************** ** REVISED 2/4/86 MACRO FILE NAME=MACHOS . ·*LI ST M,qCRD COl"IPONENTS=c 0 BC, LO, FF, SM, MP MODEL DESCRIPTION -LOCATION=12,BC, LClC,-\TJON:::: 1 7, LO, I NPUTS=BC ( V2" 0-V 1) LOCAfION=34,SM, INPUTS=BC<VL=VL) LOCATION=36,MP, INPUTS=BC(V2=VO) LOCATION=43,rF, INPUTS=SM(VI~VIl,MPCVE~VEl,BCCIL=IL> END OF MODEL PRINT
Figure A.l Model Description [BUCKCF.MOD]
120
This means that once a LOCATION statement is started for a
component, the complete description of that component must
be given. The location of each component model should be
arranged so that the interconnections among the components
can be clearly visualized in the EASYS Model Generation pro-
gram generated schematic diagram. Each component model is
described with an 'INPUTS' phrase. The input component name
must be supplemented by the name of the particular output
quantity that is to provide the input. As an example, con-
sider the load component [LO] in Fig. A. 1 Since the output
voltage (V2) of the buck-converter power stage [BC] is to be
the input voltage (Vl) to the load component, the following
statement indicates to the program that the output of [BC],
V2, is to be used as the input to the ·load component, [LO]:
LOCATION=lO, LO, INPUTS=BC(V2=Vl)
The input and output connections between the component models
are made by using the port variables shown with the right and
left side arrow of the box in the input-output list of each
component model. In model connection an 'implicit loop'
should always be avoided. The 'implicit loop' is formed
whenever the blocks are connected with all non-state vari-
ables and the connection comprises a loop. If a system con-
sists of an implicit loop, the Model Generation program will
not generate a model, instead, it will give the error message
showing where in the system an implicit loop occurs.
121
Step 2. Run the EASY5 Model Generation Program
Whenever a new macro component model is developed, the
macro model should be compiled and linked by the EASYS model
generation program using the command as follows:
EASYS BC BC.MOD
Once the macro component model is compiled and linked, the
executable file for the model is stored in the user's perma-
nent file 'MACROS. DAT' for subsequent use. After all the
component models are compiled and linked, the system model
[BUCKCF.MOD] should be also compiled and linked by the EASYS
Model Generation program. With the file 'BUCKCF. MOD' , the
EASYS Model Generation program will make all the connections
between the component blocks according to the Model De-
script~on data. The command for the EASYS Model Generation
program is as follows:
EASYS BUCKCF BUCKCF.MOD
With the above command, the EASYS program creates a new file,
'BUCKCF.MGL', which contains a FORTRAN listing of component
model programs, a schematic diagram (Fig.A.2) and input data
requirements list (Fig.A.3).
2
·k ·!c· tH-'.· * l"i-·I<· IHH~ -1:c -,-:
4 7
·IH(--1<··~ -~:-l:,•-JH-Hi-E· 1-:· t:-
li· HC +~ 1:- LO l~ 12 *<===:====·======== ·====================~==============>« 17 * *===r==>=-==========>====~===-~~==~~~==========> *
**~******* IL LOI =12 I I *******k** A l I I J G FF 11 I I J I I I l 1 l I
~? 1 I ;;i~-l I ;!4 ;:-'.~; I ;;?t-:, ;;_tJ I I I I 1 IVL BC :0 VL. :t V~? BC ::c.lJO I I I V V I I ********** ********** l I ·fr 11- -1:; , . .-l J . •t:- f;M 1~ {t· i'"iP -le
1 l H C ::-o; l L J •f.d~ tt"«--~, 1i· *·lHHf -J(·*-!-HHHHHH,·* I V l I I ********** VJ SM =VI I I j:'" ~:- vr-:: MP 1 :.: \IL:. I ~====~==* ~F *<==~=======================~=====
The printed data of various variables and parameter values
at a specified time interval are found in BUCKCF.APL. The
plotting data for a line printer is in BUCKCF. PPT, and
BUCKCF.RPD contains a plotting data for a graphics terminal.
The simulation result are drawn from the data in BUCKCF.RPD.
REFERENCES
1. F. C. Lee, Yuan Yu, "Computer-Aided Analysis and Simu-lation of Switched DC-DC Converters," IEEE Trans. on In-dustry Appliction Vol.IA-15 No.5 Sep./0ct. 1979
2. B. H. Cho, F. C. Lee, "Modeling and Analysis of Spacecraft Power Systems," IEEE PESC Record, June 1985
3. Boeing Computer Services, 11EASY5 Dynamics Analysis System User's Guide," 1983
4. B. H. Cho, "Modeling and Analysis of Spacecraft Power Systems," Ph.D. Dissertation, 1985, VPI & SU
5. R. D. Middlebrook, S. Cuk, "A General Modified Approach to Modeli~g Switching Regulator Power Stages," IEEE PESC Record, J~•~e 1976
6. F. C. Lee, Yuan Yu, "Application Handbook for Standard-ized Control Module for . DC to DC Converters," NASA Re-port, NASA CR-165172, Vol. I, Apr. 1980
7. F. C. Lee, et al. "Modeling and Analysis of Power Proc-essing Systems," NASA Report, NASA CR-165538, Vol. I, Dec. 1980
8. S. Kim, J. Lee, B. Cho and F. C. Lee, "Computer-Aided Modeling and Analysis of Power Processing Systems," NASA Report, NAG5-518, Vol. I, May 1986
9. S. Kirn, J. Lee, B. Cho and F. C. Lee, "Computer-Aided Modeling and Analysis of Power Processing Systems," NASA Report, NAG5-519, Vol. II (User's Handbook), May 1986
127
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