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Computer Aided Design of Electronics
[Datorstödd Elektronikkonstruktion]
Computer Aided Design of Electronics
[Datorstödd Elektronikkonstruktion]
Zebo Peng, Petru Eles, and Nima AghaeeEmbedded Systems Laboratory
IDA, Linköping University
www.ida.liu.se/~TDTS01
Zebo Peng, Petru Eles, and Nima AghaeeEmbedded Systems Laboratory
IDA, Linköping University
www.ida.liu.se/~TDTS01
22Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Electronic Systems
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33Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Objectives
Basic principles of computer-aided design for electronic systems (Electronic Design Automation).
Electronic system design at high levels of abstraction.
Synthesis and optimization algorithms.
Test and design for testability techniques.
The hardware description language VHDL and its use in the design/synthesis process.
44Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Course Organization 10 Lectures (Petru and Zebo): Introduction and basic terminology.
VHDL: overview and simulation semantics.
Behavioral and structural modeling with VHDL.
High-level synthesis of digital systems.
Heuristics and optimization algorithms.
Testing and design for testability.
Invited industrial lecture (Björn Fjellborg, Ericsson)
Laboratory part (Nima): Three seminars on assignments and CAD systems.
Lab assignments, for groups of two students.
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55Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Recommended Literature
G. de Micheli: “Synthesis and Optimization of Digital Systems.”
Z. Navabi: “VHDL Analysis and Modeling of Digital Systems.” Other VHDL books can also be used.
A VHDL Cookbook is available at the course website.
Articles to be distributed, including: High-level synthesis of digital circuits.
Optimization heuristics.
Design for test and built-in self-test.
Lecture notes (www.ida.liu.se/~TDTS01).
66Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Lecture I
The test problems
The design challenges
Trend in microelectronics
Different design paradigms
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77Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Moore’s Law
Similar improvement in:Clock Frequency (every 2 years)PerformanceMemory capacity
Number of transistors per chipwould double every 1.5 years.1000 M
25 M
50 M
750 M
# of trans.
0080 85 90 9575
year
05 10
88Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Moore’s Law in Action
Source: Prof. K Yelick, U.C. Berkeley
Lo
gar
ith
mic
scal
e
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99Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Intel Microprocessor Evolution
9 Images courtesy of Intel Corporation
Intel 40042.3 Thousands transistors
10000 nm
Intel 8‐core Xeon2.3 Billion Transistor
45nm
1010Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
System on Chip (SoC)
Source: S3
Source: Stratus Computers
Hardware Software
Embeddedmemory
DSP
Network
High-speed electronicsSensor
Analogcircuit
Digital ASIC
Microprocessor
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1111Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
System of Systems (SoS)
1212Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Lecture I
The test problems
The design challenges
Trend in microelectronics
Different design paradigms
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1313Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Many Design Tasks
System specification (functionality and requirements)
Hardware/software trade-offs
Architecture selection and exploration
Synthesis and optimization
Implementation
Testing and design for testability
Analysis and simulation
Verification and validation
Design management: storage of design data, cooperation between tools, design flow, etc.
1414Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Design Objectives Unit cost: the cost of manufacturing each copy of the system,
excluding NRE cost.
NRE cost (Non-Recurring Engineering cost): The one-time cost of designing the system.
Size: the physical space required by the system.
Performance: the execution time or throughput .
Power: the amount of power consumed by the system.
Testability: the easiness of testing the system to make sure that it works correctly.
Flexibility: the ability to change the functionality of the system without incurring heavy NRE cost.
Correctness, safety, etc.
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1515Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
1616Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Mixed Technologies for Electronics
Embed in a single chip: Logic, Analog, DRAM blocks
Other advanced technology blocks on a chip:
FPGA, Flash memory, RF/Microwave
FPGA
DRAM
SRAM
LOGIC
FLASH
RF
Analog
Logic
Beyond Electronic
MEMS (Micro Electro Mechanical Systems)
Optical elements
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1717Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
The Main Challenges
System complexity Increasing functionality and diversity
Increasing performance
Stringent design requirements Low cost and low power
Dependability: reliability, safety and security
Testability and flexibility
Technology challenges for cost-efficient implementation Deep submicron effects (e.g., cross talk and soft errors)
Issues related to process variation
1818Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Possible Solutions
Powerful design methodology and CAD tools.
Advanced architecture (modularity).
Extensive design reuse.
Design Paradigm Shift
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1919Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Lecture I
The test problems
The design challenges
Trend in microelectronics
Different design paradigms
2020Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Capture and Simulate
The detailed design is captured in a model.
The model is simulated.
The results are used to guide the improvement of the design.
All design decisions are made by the designers.
abc
d
o
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2121Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Abstraction Hierarchy
Layout/silicon level The physical layout of the integrated circuits is described.
abc
d
o
in o u t
Circuit level The detailed circuits of transistors, resistors, and capacitors are described.
Logic (gate) level The design is given as gates and their interconnections.
2222Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Abstraction Hierarchy (Cont’d)
Register-transfer level (RTL) Operations are described as transfers of values between registers.
Algorithmic level A system is described as a set of usually concurrent algorithms.
System level A system is described as a set of processors and communication channels.
clk
p R1 O
R2
For I=0 To 2 LoopWait until clk’event and clk = ´1´;If (rgb[I] < 248) Then
P = rgb[I] mod 8;Q = filter(x, y) * 8;
End If;
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2323Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Gajski’s Y-ChartSystem level
RT - level
Logic level
Circuit level
CPU, Memory, Bus
ALU, Reg., MUX
Gate, Flip-Flop
Transistor
Algorithms, processes
Register-Transfer Spec.
Boolean Eqn.
Transistor functions.
Transistor layouts
Standard-Cell/Subcell
Macro-Cell, chips
Board, MCMs
Behavioraldomain
Structuraldomain
Physical/geometricaldomain
2424Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
The Three Domains
Behavioral domain — A component is described by defining its input/output functional relationship.
Structural domain — A component is described in terms on an interconnection of more primitive components.
Physical/geometrical domain — A component is described in terms of its physical placement and characteristics (e.g., shape).
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2525Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
A Typical Top-Down Design ProcessSystem level
RT - leve l
Lo gic leve l
C ircui t level
C PU, Memory, Bu s
AL U, R eg., MUX
Gate , F l ip -F lop
Transistor
Algo rithm s, p rocesse s
R eg iste r- Tran sfer S pec.
B oolean Eq n.
Tra nsisto r func t ions.
Tra nsistor layou ts
S ta nda rd -Ce ll/S ubce ll
Ma cro-C ell , chips
B oard, MC Ms
Structural Dom ain
Behavioral D om ain
Physical D om ain
1
InformalSpecification
2626Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Describe and Synthesize Paradigm
Description of a design in terms of behavioral specification.
Refinement of the design towards an implementation by adding structural details.
Evaluation of the design in terms of a cost function and the design is optimized w.r.t. the cost function.
o1 = (a + b) c + d c;o2 = (d +f) c;o3 = (a + b) d + d f;...
abc
d
o
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2727Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
High-Level Describe and Synthesize
Description of a design in terms of behavioral specification.
Refinement of the design towards an implementation by adding structural details.
Evaluation of the design in terms of a cost function and the design is optimized for the cost function.
For I=0 To 2 LoopWait until clk’eventand clk=´1´;If (rgb[I] < 248) Then
P=rgb[I] mod 8;...
clk
p
R
enable
O
2828Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Core-based Design
DRAM CPU
ROMANALOG
SRAM
RF
UDL
DSP
FPU
Utilization of pre-designed and pre-verified cores:
Reuse of large IP blocks, such as CPU, DSP, memory modules,
communication infrastructure, and analog blocks.
Divide-and-conquer design methodology.
Flexibility based on different core description levels:
Soft: RT level (synthesizable
VHDL/Verilog).
Firm: Gate-level netlist.
Hard: Layout.
Legal issues:
IP right protection.
Liability in case of failures.
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2929Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Platform-based Design
A platform is a partial design: for a particular application area;
includes embedded processor(s);
may include embedded software;
customizable to specific requirements.
A platform captures the good solutions to the important design challenges in a given application area.
A method for design re-use at all abstraction levels based on assembling and configuring platform components in a rapid and reliable fashion. It reuses architectures.
3030Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Platform-based Design Steps
Design the platform. A highly configurable system
architecture.
Optimize for performance, power, etc.
Useful for a set of applications.
Tools to explore the different configurations.
Use the platform. Modify hardware components for a
particular customer’s needs.
Optimize the software.
HW/SW integration and test.
requirements past designs
platform
userneeds
product
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3131Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Lecture I
The test problems
The design challenges
Trend in microelectronics
Different design paradigms
3232Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Testing and its Current Practice
Testing aims at the detection of physical faults (production errors/defects and physical failures).
Different from the design task, testing is performed on each individual chip, after it is manufactured (volume sensitive).
The common approach to perform testing is to utilize an Automatic Test Equipment (ATE).
Automatic Test Equipment
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3333Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Testing of Mixed Technologies
How to test the mixed chip?
Use multiple ATEs: Logic ATE, Memory ATE, Analog ATE, etc.
Usually time consuming, due to handling time.
Employ a super ATE with combined capabilities.
Usually very expensive.
FPGA
DRAM
SRAM
LOGIC
FLASH
RF
Analog
U.D.Logic
Logic T
DRAM T
Analog T
3434Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
High Test Complexity
# of transistors increases exponentially.
# of access port remains stable.
Implication:
Test Complexity Index (# of transistors per pin) increases rapidly.
Testing Complexity Index - [#Tr. per Pin]
19920.5
20072004200119981995
1.60E+ 5
0.10.120180.250.35
1.00E+ 5
1.40E+ 5
4.00E+ 4
2.00E+ 4
0.00E+ 0
6.00E+ 4
8.00E+ 5
Implications of SIA Roadmap: Testing
F. Size [m]Year
Source: W. Maly, 1996
Source: SIA Roadmap
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3535Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Built-In Self Test (BIST)
Solution: Dedicated built-in hardware for implementing test functions.
No need for expensive ATE.
At-speed testing. Concurrent test possible. Support O&M. Support field test and
diagnosis.
External Test
Standard Digital Tester
Limited Speed/
Accuracy
Low Cost-per-Pin
Built-In Embedded Test
Pattern GenerationResult Compression
DiagnosticsPower Management
Test Control
Support forBoard-level Test
System-Level Test
Logic
Mixed-Signal
Memory
I/Os & Interconn.
Source: LogicVision
Design for the best BIST mechanism = optimization.
Testing => Design
3636Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Challenges still Remain
System specification with very high-level languages.
Modeling techniques for heterogeneous system.
Testing issue to be considered during the design process.
Design verifications -> get the whole system right the first time!
Very efficient power saving techniques.
Design techniques to address process variation.
Temperature aware design approaches.
Powerful optimization algorithms.
Parallel computers for design algorithms.
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3737Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Electronics System Designer
3838Zebo Peng, IDA, LiTHZebo Peng, IDA, LiTH TDTS01 Lecture Notes – Lecture 1TDTS01 Lecture Notes – Lecture 1
Conclusion Remarks
Much of design of digital systems is managing complexity.
What is needed: new techniques and tools to help the designers in the design process, taking into account different aspects.
We need especially design tools working at the higher levels of abstraction, in order to deal with the complexity and have good design productivity.
This is what our course will focus on!