Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.

Compiling ESTEREL circuitsinto finite states machines

BRES YannisStage de DEA d’Informatique 1998/1999

Esterel constructive semantics

Gives, for each statement p

pE

A new environment E’

E’

A completion code k (terminated, paused or trap exit level)

k,

A derivative statement p’, to be executed on next step

p’

, provided an initial environment E :

Circuit compilation

pE

E’ k,p’

Thus, each statement p of the language can be compiled into a circuit :

E are wires indicating present signals

E’ are wires indicating emitted signals

k indicates which completing code wire will be on

p’ is a another circuit activated by k wire

Generated circuits

Directed graphs :

logical gates (and, or, not, …)

registers (memory elements)

wires

Example of circuit

abort sustain Owhen I

I!O

K 1

K 0

0

1

0

Circuits vs. automata

Circuits are roughly linear while automata are exponential

No automata for big circuits

Up to medium-sized circuits :

Only input/test dependent stuff remain at run-time

Automata are faster (run-time minimal)

Ex : Motorola measures maximal application speed

Control flow computed at compile-time

Current compilation chain

strlic strlic strlic

iclc

lcsc

sscoc

.strl .strl .strlEsterel source

.ic .ic .icintermediate code

.lclinked code

.sccircuit code

.ocautomaton code

.sscsorted circuit code

scssc sccausal

Future compilation chain

strlic strlic strlic

iclc

lcsc

.strl .strl .strlEsterel source

.ic .ic .icintermediate code

.lclinked code

.sccircuit code

.ocautomaton code

sscoc

.sscsorted circuit code

scssc sccausal

scoc

SSCOC automaton generation

Circuit is seen like a set of boolean equations

To be evaluated, equations must be sorted (.ssc)

Sorting fails on several kind of cyclic circuits !

Code unmaintained...

SCOC automaton compilation

Algorithm follows electrical current

new informations (hot)propagated informations (cold)

I!O

K 1

K 0

0

1

0



Building initial statePropagating registers

1

0

I!O

K 1

K 0

0

1

0




1

0

I!O

K 1

K 0

0

1

0




1

0

0

I!O

K 1

K 0

0

1

0




1

0

0

0

I!O

K 1

K 0

0

1

0




1

0

0

0

0

I!O

K 1

K 0

0

1

0




1

0

0

0

0

I!O

K 1

K 0

0

1

0




1

0

0

0

0

I!O

K 1

K 0

0

1

0




1

0

0

0

0

I!O

K 1

K 0

0

1

0




11

0

0

0

0

I!O

K 1

K 0

0

1

0




11

0

0

0

0

I!O

K 1

K 0

0

1

0



Initial state built

11

0

0

0

0

I!O

K 1

K 0

0

1

0

!O



Initial state builtBuilding state 1

11

0

0

0

0

I!O

K 1

K 0

0

1

0

!O




Loading registers values

0

1

I!O

K 1

K 0

0

1

0

!O




Loading registers valuesPropagating registers

0

1

I!O

K 1

K 0

0

1

0

!O





0

1

I!O

K 1

K 0

0

1

0

!O





0

1

I!O

K 1

K 0

0

1

0

!O





0

1

I!O

K 1

K 0

0

1

0

!O




Loading registers valuesPropagating registersForking on input signal I

0

1

I!O

K 1

K 0

0

1

0

!O





Building branch where I is present

0

1

?I!O

K 1

K 0

0

1

0

!O






0

1

1

?I!O

K 1

K 0

0

1

0

!O






0

1

0

1

?I!O

K 1

K 0

0

1

0

!O






0

1

0

1

?I!O

K 1

K 0

0

1

0

!O






0

0

1

0

1

?I!O

K 1

K 0

0

1

0

!O






0

0

1

0

1

?I!O

K 1

K 0

0

1

0

!O






00

0

1

0

1

?I!O

K 1

K 0

0

1

0

!O






00

0

1

0

1

?I!O

K 1

K 0

0

1

0

!O





Final state reachedBuilding branch where I is present

00

0

1

0

1

?I!O

K 1

K 0

0

1

0

!O

?I





Building branch where I is presentBuilding branch where I is absent

0

1

#I!O

K 1

K 0

0

1

0

!O

?I






0

1

0

#I!O

K 1

K 0

0

1

0

!O

?I






0

1

1

0

#I!O

K 1

K 0

0

1

0

!O

?I






0

1

1

0

#I!O

K 1

K 0

0

1

0

!O

?I






0

1

1

1

0

#I!O

K 1

K 0

0

1

0

!O

?I






0

1

1

1

0

#I!O

K 1

K 0

0

1

0

!O

?I






01

1

1

1

0

#I!O

K 1

K 0

0

1

0

!O

?I






01

1

1

1

0

#I!O

K 1

K 0

0

1

0

!O

?I






State 1 reached again

01

1

1

1

0

#I!O

K 1

K 0

0

1

0

!O

?I

# I.!O

Circuit saving and restoring

To avoid saving the whole circuit at each step of automata building :

Restoration data are stored in a stack of stacks






















Signal relations processing

Stored in a directed graph

Example :3 22 11 # 4 # 5

3

21

4 5

: present absentabsent present

: present present

: absent absent



Example :3 22 11 # 4 # 5

3

21

4 5


: present present

: absent absent



Example :3 22 11 # 4 # 5

3

21

4 5


: present present

: absent absent



Example :3 22 11 # 4 # 5

3

21

4 5


: present present

: absent absent



Example :3 22 11 # 4 # 5

3

21

4 5


: present present

: absent absent



Example :3 22 11 # 4 # 5

3

21

4 5


: present present

: absent absent



Example :3 22 11 # 4 # 5

3

21

4 5


: present present

: absent absent



Example :3 22 11 # 4 # 5

3

21

4 5


: present present

: absent absent

Smart circuit evaluation

Circuit evaluation algorithm stops as soon as all required nets are stabilized :

Registers (determine next state)

K0/K1 (determine whether automaton has terminated)

Output signals

Action nets (side-effects operating on values)

Input partitionning

After registers propagation :

Inputs reachable from required nets will be processed first

Other inputs will probably not be processed at all

Depending on current state, parts of the circuit are disabled

Input sorting

Example : bus arbiter

Set of cells requesting the access to a data bus

Cells have rotating priorities

bus

Cell #1

Cell #2

Cell #3

Cell #4

Cell #5

Input sorting

Inputs are sorted upon the number of reachable registers

This turns transitions from full trees (2n-sized) to combs (n-sized):

2

?R eq1!A ck1

#R eq1

?R eq2!A ck2

?R eq3!A ck3

#R eq3

1

#R eq2

3

?R eq2!A ck2

#R eq2

?R eq3!A ck3

?R eq1!A ck1

#R eq1

#R eq3

?R eq3!A ck3

#R eq3

?R eq1!A ck1

?R eq2!A ck2

#R eq2

#R eq1

DAG sharing

present A emit A' end present

||

present B emit B' end present

Goals :

Saving memory

Emphazing semantic aspects

?A . !A ' #A

?B . !B '

#B ?B . !B '

#B

?A . !A ' #A

?B . !B ' #B

Performance comparison

Compiling ESTEREL circuits into finite states machines BRES Yannis Stage de DEA d’Informatique 1998/1999.

Documents

wire slide

oc automaton code

circuit compilation

compiletime slide

new environment e e

initial environment

statement p p e

automata circuits