Comparison of topside contact layouts for power dies embedded in PCB ESTC 2016, Grenoble Chenjiang YU 1 , Cyril BUTTAY 2 , Éric LABOURÉ 1 , Vincent BLEY 3 , Céline COMBETTES 3 , Gilles BRILLAT 3 1 GEEPS, Paris, France 2 Laboratoire Ampère, Lyon, France 3 LAPLACE, Toulouse, France 14/09/16 1 / 23
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Comparison of topside contact layouts for power dies ... · Comparison of topside contact layouts for power dies embedded in PCB ESTC 2016, Grenoble Chenjiang YU1, Cyril BUTTAY2,
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Comparison of topside contact layouts forpower dies embedded in PCB
I Start with a DBC substrateI Die attach (silver sintering)I PCB stackingI PCB laminationI Topside copper etchingI Laser ablationI Copper electroplating
8 / 23
Overview of the process
I Start with a DBC substrateI Die attach (silver sintering)I PCB stackingI PCB laminationI Topside copper etchingI Laser ablationI Copper electroplating
8 / 23
Overview of the process
I Start with a DBC substrateI Die attach (silver sintering)I PCB stackingI PCB laminationI Topside copper etchingI Laser ablationI Copper electroplating
8 / 23
Overview of the process
I Start with a DBC substrateI Die attach (silver sintering)I PCB stackingI PCB laminationI Topside copper etchingI Laser ablationI Copper electroplating
8 / 23
Overview of the process
I Start with a DBC substrateI Die attach (silver sintering)I PCB stackingI PCB laminationI Topside copper etchingI Laser ablationI Copper electroplating
8 / 23
Overview of the process
I Start with a DBC substrateI Die attach (silver sintering)I PCB stackingI PCB laminationI Topside copper etchingI Laser ablationI Copper electroplating
8 / 23
Overview of the process
I Start with a DBC substrateI Die attach (silver sintering)I PCB stackingI PCB laminationI Topside copper etchingI Laser ablationI Copper electroplating
8 / 23
Overview of the process – significant points
I Backside die attach with silver sintering:I The die does not move during assemblyI Accurate positioning
I Ablation using a CO2 laserI Very good selectivity (metal layers insensitive to laser light)I Use of the copper layer as an alignment mask
I Prototype-scale equipment usedI Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2
I Affordable, useful for process development.
9 / 23
Overview of the process – significant points
I Backside die attach with silver sintering:I The die does not move during assemblyI Accurate positioning
I Ablation using a CO2 laserI Very good selectivity (metal layers insensitive to laser light)I Use of the copper layer as an alignment mask
I Prototype-scale equipment usedI Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2
I Affordable, useful for process development.
9 / 23
Overview of the process – significant points
I Backside die attach with silver sintering:I The die does not move during assemblyI Accurate positioning
I Ablation using a CO2 laserI Very good selectivity (metal layers insensitive to laser light)I Use of the copper layer as an alignment mask
I Prototype-scale equipment usedI Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2
I Affordable, useful for process development.
9 / 23
Die Preparation — Lab-scale process
I Standard Al topside UnsuitableI Ti/Cu PVD with a shadow mask
(50/500 nm)I Simple process for singulated dies
5×5 mm2 IGBT die
10 / 23
Die Preparation — Lab-scale process
Mask
I Standard Al topside UnsuitableI Ti/Cu PVD with a shadow mask
(50/500 nm)I Simple process for singulated dies
5×5 mm2 IGBT die
10 / 23
Die Preparation — Lab-scale process
MaskDie
I Standard Al topside UnsuitableI Ti/Cu PVD with a shadow mask
(50/500 nm)I Simple process for singulated dies
5×5 mm2 IGBT die
10 / 23
Die Preparation — Lab-scale process
PVD
MaskDie
I Standard Al topside UnsuitableI Ti/Cu PVD with a shadow mask
(50/500 nm)I Simple process for singulated dies
5×5 mm2 IGBT die
10 / 23
Die Preparation — Lab-scale process
PVD
MaskDie
I Standard Al topside UnsuitableI Ti/Cu PVD with a shadow mask
(50/500 nm)I Simple process for singulated dies
5×5 mm2 IGBT die
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Cross section
I Vertical walls in epoxy layersI Good self-alignmentI No degradation of die topside
metal due to CO2 laserI Die contact not yet perfect
11 / 23
Outline
Introduction
Proposed Embedding Technique
Effect of Contact Area/Layout
Summary and Conclusion
12 / 23
Effect of Contact Area/Layout
Die
Topside copper
Wells
R
Copper foil Electroplated copper
Die
Die topside métallizationfiber-resin composite
I Thick topside copper foil (35 µm)I Thin electroplated copper (10 µm)I Many wells:
I More copper section on wallsI Large well(s):
I Thicker die contact metallizationI reduction of topside copper section
13 / 23
Effect of Contact Area/Layout
Die
Topside copper
Wells
R
Copper foil Electroplated copper
Die
Die topside métallizationfiber-resin composite
I Thick topside copper foil (35 µm)I Thin electroplated copper (10 µm)I Many wells:
I More copper section on wallsI Large well(s):
I Thicker die contact metallizationI reduction of topside copper section
13 / 23
Effect of Contact Area/Layout
Die
Topside copper
Wells
R
Copper foil Electroplated copper
Die
Die topside métallizationfiber-resin composite
I Thick topside copper foil (35 µm)I Thin electroplated copper (10 µm)I Many wells:
I More copper section on wallsI Large well(s):
I Thicker die contact metallizationI reduction of topside copper section
13 / 23
Modelling
Die
Topside copper
Wells
RRtop
Rwall
Rcont
Rdie
RAl
Raccess
Vin
I Structure divided into 100×100µm cellsI 2-D current flow assumedI Generation of a meshed circuit of resistorsI Solving using Modified Nodal Analysis.
I Resistance value extracted from I(V) characteristic of diodeI Large scattering of experimental data (±20%)I Same die in standard TO-247 package: 4.4 mΩ
18 / 23
Contact Resistance — conclusions
I Contact distribution is important, contact area not so muchI Experimental results show same trend as simulation
I Resistance 4 times higher!I Poor quality of die/electroplated copper interfaceI Model also probably too optimistic (diode modelled as a resistance)
I Resistance equivalent to that of (commercial) wirebonded dies
19 / 23
Contact Resistance — conclusions
I Contact distribution is important, contact area not so muchI Experimental results show same trend as simulation
I Resistance 4 times higher!I Poor quality of die/electroplated copper interfaceI Model also probably too optimistic (diode modelled as a resistance)
I Resistance equivalent to that of (commercial) wirebonded dies
19 / 23
Contact Resistance — conclusions
I Contact distribution is important, contact area not so muchI Experimental results show same trend as simulation
I Resistance 4 times higher!I Poor quality of die/electroplated copper interfaceI Model also probably too optimistic (diode modelled as a resistance)
I Resistance equivalent to that of (commercial) wirebonded dies
19 / 23
Contact Resistance — conclusions
I Contact distribution is important, contact area not so muchI Experimental results show same trend as simulation
I Resistance 4 times higher!I Poor quality of die/electroplated copper interfaceI Model also probably too optimistic (diode modelled as a resistance)
I Resistance equivalent to that of (commercial) wirebonded dies
19 / 23
Outline
Introduction
Proposed Embedding Technique
Effect of Contact Area/Layout
Summary and Conclusion
20 / 23
Summary and Conclusion
I Embedding of power devicesI Custom design at die levelI Attractive for fast, wide-bandgap devicesI Contact layout allows for better current
spreadingI Simple process
I Lab-scale process presentedI Low contact resistance achievedI Main issue: die topside finish
I Developments to come:I Half-bridge with gate driversI Embedding of passive componentsI Work on thermal design
21 / 23
Summary and Conclusion
I Embedding of power devicesI Custom design at die levelI Attractive for fast, wide-bandgap devicesI Contact layout allows for better current
spreadingI Simple process
I Lab-scale process presentedI Low contact resistance achievedI Main issue: die topside finish
I Developments to come:I Half-bridge with gate driversI Embedding of passive componentsI Work on thermal design
21 / 23
Summary and Conclusion
I Embedding of power devicesI Custom design at die levelI Attractive for fast, wide-bandgap devicesI Contact layout allows for better current
spreadingI Simple process
I Lab-scale process presentedI Low contact resistance achievedI Main issue: die topside finish
I Developments to come:I Half-bridge with gate driversI Embedding of passive componentsI Work on thermal design
21 / 23
Bibliography I
E. Hoene, “Ultra Low Inductance Package for SiC,” in ECPE workshop on powerboards, ECPE, 2012.
A. Ostmann, “Leistungselektronik in der Leiterplatte,” in AT&S Technologieforum,2013.
A. Ostmann, L. Boettcher, D. Manessis, S. Karaszkiewicz, and K.-D. Lang,“Power modules with embedded components,” in Microelectronics PackagingConference (EMPC) , 2013 European, pp. 1–4, Sept. 2013.