Comparison between RISC architectures: MIPS, ARM and SPARC

Insightful comparison between three of the most popular and widely used RISC processors: MIPS, ARM and SPARC

Apurv NerlekarRishabh Sreedhara

Rishikesh NagareShivakumar Soppannavar

Index

1. Introduction2. History3. Applications and market4. Architectural difference 5. Register conventions6. Operating modes7. Addressing modes8. Conditional execution9. Exception handling10 Stack implementation11.Conclusion

Introduction

1. Why do we need to study the differences?

● Every application is different, and hence each application requires different crucial factors that decide the architecture to use.

● Some may be performance dependent, some crucial with respect to reliability, some might require to reduce the cost.

2. We will discuss about how to select a specific processor for particular application along with few use cases.

3. The presentation will help you scale your application and adapt an architecture which is a best fit.

History

Reduced instruction set computing ( RISC ).

● MIPS : Microprocessor without Interlocked Pipeline Stages. - Developed since 1980.MIPS-32 and MIPS-64 with versions MIPS 1 to MIPS 5Ex: Embedded systems, Connectivity.

● ARM : Advanced RISC Machines. - Developed since 1985.Developed because of the emerging trend of low cost machines.Ex: Mobile devices, Automotive.

● SPARC : Scalable Processor Architecture. - Developed since 1987.Developed because of the concept of making it compatible for various different languages to code on and deploy softwares which can provide high performance.Ex: Network Servers, Mobile Devices.

Applications and market

1. MIPS● Unlike other architectures MIPS has many market applications.● Open source implementations available.● Simple coding syntax, easier to use.● Benefits help them to be used for educational purpose.● The cost for devices using MIPS is less.● Support for Graphics, and long term support.

Ex: Few Applications ● MM : Memory Management application .● MMU : Memory Management Unit.● Mobile Devices, Networking devices, Audio devices.

Overall : Low cost, huge functionality and high performance gives it a bigger market than the rest.

Applications and market (contd..)

2. ARM● Support for 64 bit architecture. Continuous updation.● Development over architecture depending upon the market.

Ex. ARM v8-A for high performance market like mobile devices. ARM v8-R for embedded devices like automotive, industrial control.

● Variety of units as per demand. Some include virtual platforms, code generation tools, debug solution tools.

● Every device configured with respect to consume low power.● Extension approach like java acceleration, SIMD, advanced SIMD, security (Trustzone). ● Support for Graphics, long term support.

Overall : Low cost, adaptability, variety of low power-high performance devices gives it a bigger market than the rest.

Applications and market (cont..)

3. SPARC● Used majorly by programmers and Architects. Low level programing.● Multi core functionality introduced by this architecture.● Use cases include softwares and devices where need for performance with respect to

throughput is required.● A bit higher on cost than others● Highest support of Integration with other architectures.● Multiple servers can be written with the help of Solaris OS which is the best fit.

Overall : Adaptability, Extreme high performance architecture makes it ideal for systems which are highly concerned about throughput and extreme server processing.

Architectural difference

1.MIPS● Low overhead - less time wasted● Power Efficient- less number of instructions

2.ARM with Thumb● Reduced total amount of Memory● Extra Thumb ISA● Switching between states

3.SPARC● Register file model unlike others its not flat

Register conventions

Registers referred using:

● MIPS $ ex: $R0● ARM

ex: R0● SPARC %

ex: %R0

MIPS32 bit wide 32 registers

Two special registers:Hi/Lo -> Multiply and Divide Unitsmfhi $r1mflo $r0

ARMFor ARM Cortex- M3● 32 bit wide 16 registers● 12 general purpose registers

Status registers:● CPSR

SPARC● 32 bit wide 32 Registers

● Registers are divided into four groups.1. global registers2. output registers3. local registers4. input registers

● Register file model not flat.● Overlapping register windows.

Procedure Calling Mechanism

ARM

Operating modes

User Mode Privileged Mode

System Mode Exception Mode

SVC - Supervisor Mode

UND- Undefined Mode

ABT - Abort Mode

IRQ- Interrupt Mode

FIQ- Fast Interrupt Mode

MIPS

Kernel Mode User Mode

SPARC

Supervisor Mode User Mode

MIPS

Operating Modes - MIPS and SPARC

kernel mode, (Status Bit - 0) ● Can access and change all registers.● This mode has the privilege over other modes and gets switched to in case of an

error, interruption, exception or at power upUser mode, (Status Bit - 1)

● Accessed by users and has a lower privilege than that of the kernel mode. ● It also prevents different users from interfering with one another

kernel mode, (Status Bit - 0) ● Used to access the processor state registers, such as the Window Invalid Mask (WIM), and the

input/output devices.● Full access to the memory and its system tables making it privileged in almost all architectures.

User mode, (Status Bit - 1) ● Used to write to and read from the processor state register and has a limited access to the memory

since a load or a store instruction cannot be executed in it.● Additionally, to know whether the processor is in the user mode or in the supervisor mode, the

processor status word is used to determine the current state of the processor

SPARC

Operating Modes - ARM

ARM has seven basic operating modes, starting with the processor mode which has two operating modes under it, the user mode and the privileged mode. 1. User mode

The user mode is where most applications’ contents or operating systems’ tasks run.2. Privileged mode

The privileged mode has under it two operating modes, system mode and the exception mode.

❖ System mode is the privileged mode which uses the same registers as used by the user mode❖ Exception mode has 5 operating modes

1. Supervisor mode (SVC) which is entered under two conditions, when on restore or when Software Interrupt Instruction (SWI) is executed

2. Abort (ABT) mode which is used to handle memory access violations3. Undefined (UND) mode which is used to handle undefined instructions4. Interrupt (IRQ) mode which is entered when a high priority interrupt is raised.5. Fast Interrupt (FIQ) mode which is entered when a high priority interrupt is raised

Operating Modes - ARM - Register Organization

Addressing modes

Addressing modes are the ways how architectures specify the address of an object they want to access.

MIPS

SPARC

ARM

1. Register Addressing2. Immediate 3. PC-Relative 4. Pseudo-direct 5. Base

1. Pre indexed Addressing 2. Pre indexed Addressing with write back 3. Post indexed Addressing 4. Program counter Relative Addressing

1. Register indirect with index 2. Register indirect with immediate

Addressing modes - MIPS

MIPS support five addressing modes:

1. Register Addressing: This mode is mainly used in calculating the effective address of the jump register (jr) instruction. Ex: Jump $R3; ADD $R5, $R6, $R7

2. Immediate Addressing: This mode does not access memory and thus is relatively faster than other modes. The immediate is of size equal to 16-bits. Ex: ADD $R1, $R1, 10; i.e R1= R1+100

3. PC-Relative Addressing: This mode is used to determine when the branch instruction occurs by summing the offset value with the PC. EX: BEQZ $R5, Loop;

4. Pseudo-direct Addressing: This mode is used in the jump instruction where the value of the offset is 6-bits and the target of the instruction jumped to is 26-bits. The upper four bits of the PC and the least two significant bits, which are 00, are all concatenated with the 26-bit immediate resulting in a 32-bit instruction. EX: MOVE $R1, $R2 means move value of $R2 into $R1, this is translated into actual code like Add $R1, $R1, $ZERO

5. Base Addressing: This mode is used in store word and load word instructions. It is known as the indirect addressing since the register acts as a pointer to some memory location whose address could be found in the register. EX: LW $R1, 24($R1); Address is the sum of the register and constant 24

Addressing Mode - ARM

ARM supports multiple addressing modes, including modes that allow direct bit shifting. There are four main addressing modes to calculate the effective address:

1. Pre-indexed Addressing: In this mode, the source/destination address is stored in a register offset by another value. Figure 1 (a), shows how the load operation is used to calculate the pre-indexed effective address. EX: LDR R3, [R5, R6]

2. Pre-indexed Addressing with Write Back: In this mode, it is sometimes useful to save the new address in a register. To indicate that this effective address is being written back, add an exclamation mark (!) at the end of the load instruction. Figure 1 (b) describes the operation of the write back. EX: LDR R3, [R5, R6]!

3. Post-Indexed Addressing: This mode is similar to Pre-Indexed Addressing with Write back. However, the address is modified and saved only after the load/store operation. Figure 1 (c) illustrates the effective address calculation in the post-indexed addressing mode. EX: LDR R3, [R5], R6

4. Program Counter Relative Addressing: This mode allows the ARM architecture developers to address memory relative to the Program Counter (R15). LDR R0, [R15, #24]

Addressing Mode - ARM (cont..)

Pre-indexed addressing mode

Pre-indexed addressing mode with write back

Post-indexed addressing mode

Addressing mode -SPARC

SPARC supports two addressing modes to compute the effective address:

1. The Register indirect with index: This mode computes the effective address by adding the contents of the base register to those of the index register. The effective address cannot be equal to only the base register but the index register could be made equal to zero and by that the effective address will be equal to the base register. E.g: Add %i3, %i1, %i2Typically used to access array where one register holds the base value and other holds the (scaled) index of the element

2. The Register indirect with immediate: This mode computes the effective address by sign extending the 13-bit immediate to 64 bits and then adds the contents of the base register to it. The effective address could be made equal to the base register by making the constant equal to zero.

E.g: Add %o1, 4, %o2

Stack implementation

A stack is a data structure that is used for the storage of data.

MIPS ARM SPARC

Direction of Stack growth

Stack grow downwards

Stack grow downwards and upwards

Stack grow downwards

Push and Pop instruction

Does not support push/pop instructions. Instead, it manipulates the stack pointer (register 29)

No explicit push/pop instructions but it can manipulate the stack pointer to do so

No explicit push/ pop instructions but can be implemented using the stack pointer(sp)

Stack implementation - Stack Popping

Stack popping. The stack pointer (SP) copies the data, in the address given, in a register first, and then moves the stack pointer.

Initial Stack After

adjusting SP

Empty

Data

Stack

SP SP

SP

Empty

Data

Stack

Empty

Data

Stack

000FFFFC

00100000

000FFFFC

00100000

000FFFFC

00100000

After Copying

Stack implementation - Stack Pushing

Stack pushing. The stack pointer (SP) is moved in order to place the contents of register 3 (R[3]) into the address that the stack pointer is pointing to.

Initial Stack After Copying

Empty

Stack

SP

SP SP Empty

Stack

Empty

R[3]

Stack

000FFFFC

0010000000100000

000FFFFC

00100000

After Adjusting

SP

Conditional ExecutionAdvantage of conditional statements is that, we can make certain statements to execute conditionally.

MIPSNo Conditional bitsdepends on branch instructionsExample: beq $5, $13, label1

ARMFour Conditional Flags:

● Zero (Z), Overflow(V), Carry (C), Negative (N)Data processing instructions do not affect the conditional flagspostfix the instruction with letter “s”Example:ADDS r0, r1, r2Data processing Instructions: Arithmetic operations, comparisons, logical operations, data movement between registers.

SPARCFour Conditional flags:

● Zero (Z), Overflow(V), Carry (C), Negative (N)Suffix “cc” to operationsExample:ADDc Rs1, Rs2, RdADDccc Rs1, Rs2, Rd

Exception handlingNormal execution of instructions may be interrupted when an exception occurs.Are 2 types:

● Synchronous exceptions: occurs at the same place every time a program is executed● Asynchronous exceptions: happen with no temporal relation to the program being executed

Register Number Register Name Usage

8 BadVAddr This holds Memory address where exception occurred

12 Status Masks the Interrupts, enable bits, and changes status when exception occurred

13 Cause Type of exception occurred and pending interrupt bits

14 EPC Holds Address of instruction that caused exception

MIPS

Cause Register Pending Interrupt Exception Code

Bits 15-10 Bits 5-2

Exception handling

ARM● Exception happens only in ARM mode.● Core copies CPSR and is saved in SPSR.● CPSR is updated with ARM state, CPU to exception mode, interrupts are disabled.● PC is set to interrupt vector address.

SPARC● When Exception occurs Trap Enable gets cleared● Execution state changes to supervisor mode● Current window pointer is decremented● Program counter, processor state register, NPC are saved to local registers %l0 to %l2 ● trap handling code is saved to %l3 to %l7

Conclusion

We conclude that once the detail analysis of your product is done and If the tables and flowcharts from this presentation is followed, it can help us decide which architecture to choose before even starting the prototyping of product.

This will help making the product competitive and help them keep updated in the market with high assured performance.

References

[1] A. I. Center., ARM Information Center. N.p., n.d.

[2] B. J. Catanzaro, Ed., The SPARC Technical Papers. New York, NY, USA: Springer-Verlag New York, Inc., 1991.

[3] C. Corporation, Best Practices For Improving Application Performance and Lowering Cost by Managing MIPS., 2012.

[4] R. Teodorescu, Instruction Set Architecture of MIPS Processor Presentation B. The Ohio State University, 2008.

[5] C. Lin, Understanding the Stack. Department of Computer Science, University of Maryland, 2003.

Thank you