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Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS: D.Brunel , C.Busseret, A.Poncet PISA: A.Campera, G.Fiori, G.Iannaccone POLIMI: R.Gusmeroli, C. Monzio Compagnoni, A.L.Lacaita, A.S.Spinelli TUW: M.Karner, H.Kosina, E.Langer UDINE: F.Driussi, P.Palestri , L.Selmi WUT: B.Majkusiak, J.Walczak
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Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Dec 14, 2015

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Page 1: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Comparison among modeling approaches for gate current

computation in advanced gate stacksARCES: N.Barin, C.Fiegna, E.Sangiorgi

BU: P.A.Childs

FMNT-CNRS: D.Brunel , C.Busseret, A.Poncet

PISA: A.Campera, G.Fiori, G.Iannaccone

POLIMI: R.Gusmeroli, C. Monzio Compagnoni, A.L.Lacaita, A.S.Spinelli

TUW: M.Karner, H.Kosina, E.Langer

UDINE: F.Driussi, P.Palestri, L.Selmi

WUT: B.Majkusiak, J.Walczak

Page 2: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Aim of Task 3 of SINANO Work-Package 4Study of the performance and reliability of conventional (SiO2) and

high-k thin insulator gate stacks for sub-50nm MOSFETs)

• To support the understanding of device reliability issues and potential limitations of device performance related to the gate stack architecture of future CMOS technologies.

The activities foreseen in this context are:• simulation of C/V and I/V for different gate stack and device

architectures; • investigation of the effects of high-K materials and of the related

defects, traps, charges, etc.. on the low-field mobility and carrier transport properties of the inversion channel.

Two main phases :• comparison of gate leakage currents in advanced device

architectures; • assessment of modeling requirements for ultra-thin oxide and

high-k, metal gate stacks.

Page 3: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

OUTLINE

• Modeling approaches• Template devices• Results

– C/V– I/V– Microscopic quantities

• Comparison with experiments• Conclusions

Page 4: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Simulation Framework

• Solution of the Schrödinger equation in the poly-Si/dielectric/Si stack

EyV

dy

d

m )(

2 2

22poly

Diel.

Si

• Boundary conditions ?

+Poisson Equation

Page 5: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Boundary Conditions

Closed

In principle: no current !

Define quantum boxes

=0 at both sides of a box

Ig: semiclassical approach

Page 6: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Boundary Conditions

Open: resonance peakInject plane waves and compute transmission/reflection

Ei

Page 7: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Boundary Conditions

Open: perfectly-matched-layer

Absorbing boundaries

Complex eigenvalues

Page 8: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Boundary Conditions

Periodical The Schrödinger equation is solved two times,applying Dirichlet and then Neumann conditions on both sides.

This is like simulating an infinite periodical structure, but only over one half period

T-prob. from the contact to the semiclassical turning point

Page 9: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Approaches followed by the partners

Model 1Model 2Model 3Model 4Model 5Model 6Model 7

Different definitions of the quantum boxes in closed-boundaries

Page 10: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

OUTLINE

• Modeling approaches• Template devices• Results

– C/V– I/V– Microscopic quantities

• Comparison with experiments• Conclusions

Page 11: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Template Devices

• Device A: pure SiO2 (tOX=1nm) NPOLY=1020cm-3 (n-type)

NSUB=1018cm-3 (p-type)

• Device B: pure SiO2 (tOX=3nm) NPOLY=51019cm-3 (n-type) NSUB=31017cm-3 (p-type)

• Device HK: 4nm HfO2+ 1nm ITL NPOLY=1020cm-3 (n-type) NSUB=31017cm-3 (p-type)

• Device A and B are from: C. A. Richter, IEEE EDL, vol.22, p.35, 2001.

Page 12: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Simulation Parameters

Same parameters in all modeling approaches

Page 13: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

OUTLINE

• Modeling approaches• Template devices• Results

– C/V– I/V– Microscopic quantities

• Comparison with experiments• Conclusions

Page 14: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Results: C/V curves

•Good overall agreement•Small problems in accumulation and at beginning of inversion (different models for poly-quantization)

HK

Page 15: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Internal quantities affecting C/V

Cond.Band in accumulation Subbands in inversion

Page 16: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Results: I/V

HK Errors within a factor of 10

Much larger in accumulation (not shown)

Page 17: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Internal quantities affecting IG

HK

Escape-time

Page 18: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Internal quantities affecting IG

Tunneling probability

HK

Page 19: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

OUTLINE

• Modeling approaches• Template devices• Results

– C/V– I/V– Microscopic quantities

• Comparison with experiments• Conclusions

Page 20: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Comparison with experimentsData from N.Yang et al., IEEE T-ED, vol.46, p.1464, 1999.Same physical parameters as in the template devices.

NPOLY=1020cm-3

NSUB=51017cm-3

(from C/V)

Page 21: Comparison among modeling approaches for gate current computation in advanced gate stacks ARCES: N.Barin, C.Fiegna, E.Sangiorgi BU: P.A.Childs FMNT-CNRS:

Conclusions• Unprecedented comparison effort carried out by seven

academic groups• Good agreement between results obtained using very

different models (open/closed boundaries)• Approaches based on closed boundaries, coupled with

the evaluation of the semiclassical escape-time provide a good trade-off between efficiency and precision

• Results submitted to IEEE T-ED, 2nd review step: mandatory revisions

• Comparison of Trap-Assisted-Tunneling