Comp+Arch+Wk+6 Interrupts+++FP+Pipeline Aut09

8/8/2019 Comp+Arch+Wk+6 Interrupts+++FP+Pipeline Aut09

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Computer Architecture

EXCEPTIONS AND INTERRUPTS


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Exceptions and Interrupts

Exception handling is a programming language constructor computer hardware mechanism designed to handle theoccurrence of some condition that changes the normalflow of execution. The condition is called an exception.

Alternative concepts are interrupt, signal and eventhandling.

In general, current state will be saved in a predefinedlocation and execution will switch to a predefined handler(subroutine/procedure). Depending on the situation, the

handler may later resume the execution at the originallocation, using the saved information to restore theoriginal state. For example, an exception which will usuallybe resumed is a page fault, while a division by zero usually

cannot be resolved transparently.(Wikipedia)


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Common Exceptions

I/O Device Request

Integer Arithmetic Overflow

FP Arithmetic Anomaly

Page Faults

Memory Protection Violation

Undefined Instruction

Power Failure

etc


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Characterizing Exceptions

Synchronous vs. Asynchronous

User Requested (system calls)/coerced(mouse click)

Maskable vs. Non-maskable

Within / Between Instructions

Resume-able/Terminate


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Resumable

Shut pipeline by converting all instruction

after the instruction causing exception toNOP

Save processor state

Call Handler

Resume State

Precise Exception ???


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Exception typeSynchronous vs.

asynchronous

User request vs.

coerced

User maskable

vs. nonmaskable

Within vs.

between

instructions

Resume vs.

terminate

I/O device request Asynchronous Coerced Nonmaskable Between Resume

Invoke operating

systemSynchronous User request Nonmaskable Between Resume

Tracing

instruction

execution

Synchronous User request User maskable Between Resume

Breakpoint Synchronous User request User maskable Between Resume

Integer arithmetic

overflowSynchronous Coerced User maskable Within Resume

Floating-point

arithmeticoverflow or

underflow

Synchronous Coerced User maskable Within Resume

Page fault Synchronous Coerced Nonmaskable Within Resume

Misaligned

memory accessesSynchronous Coerced User maskable Within Resume

Memory

protection

violation

Synchronous Coerced Nonmaskable Within Resume

Using undefined

instructionSynchronous Coerced Nonmaskable Within Terminate

Hardware

malfunctionAsynchronous Coerced Nonmaskable Within Terminate

Power failure Asynchronous Coerced Nonmaskable Within Terminate


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MIPS Interrupts

IF Page Fault, Mem Prot Violation

ID Undefined or Illegal Op Code

EX Arithmetic

MEM Same as IF

WB None


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MULTIPLE CYCLEPIPELINES


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Single Cycle Computer

(One Big Clock Cycle to Accommodate Longest Latency)

IF ID EXE MEM WB

Single Clock Cycle


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Multiple Cycle Computers

IF ID EX WB IF ID EX WB IF ID EX WB

All Instruction Go through the Processing One-by-One


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Classic 5-Stage Integer Pipeline

IF ID EX Mem WB

Almost 1 CPI except for LUDand Branch Hazards


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A Multiple Cycle Pipeline

EX

Mem WBF ID FP ADD

FP Multiply

Divide

RegisterFile(Integer/FP)

RegisterFile(Integer/FP)


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FP Pipeline Stages

Adder, Multiplier, Divider Steps

Unpack floating point number

Operand Shift Stage

A Mantissa Add Stage, Multiply, Divide Stage

Rounding the result

Operand shift the result


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Multiple Cycle Floating Point Pipeline

EX

Mem WBF ID A1

A2

A3

A4

M1

M2

.. M7Divide

Function Unit LatencyWithforwarding

Initiation

/Re-IssueInterval

Integer ALU 0 1

Load/Store 1 (LUD) 1 (LUD)

FP Add 3 1

FP/Int Multiply 6 1

FP/Int Divide 24 25

Note:1.Both FP ADD and SUB use the same A1, A2,-- Pipeline.2.FP Load/Store go through Integer Pipeline.


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Forwarding

EX

Mem WBF ID A1

A2

A3

A4

M1

M2

.. M7Divide

ALU/FPInstructions


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Example 1a, FP ALU to ALUExample 1

ADD.D F10, F11, F12 IF iD A1 A2 A3 A4 MEM

WB

ADD.D F0,F1,F10 IF ID ID ID ID ID ID A

1 A2

Without Forwarding

ADD.D F10,0(R2) IF iD A1 A2 A3 A4 ME

M

WB

IF

ADD.D F0,F1,F10 IF ID ID ID ID A1

With Forwarding (needs multiplexer)


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Example 1b FP Load to ALU

L.D F10,0(R2) IF ID EX

E

ME

M

WB

ADD.D F0,F1,F10 IF ID ID ID A1 A2 A3 A

4

MEM

Without Forwarding (ID stall, waiting to be written in register file)

L.D F10,0(R2) IF ID E

X

E

M

E

M

W

B

ADD.D F0,F1,F10 IF ID ID A1 A2 A3 A4 MEM

With Forwarding (to exe stage through mux)


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EXAMPLE 2, Concurrent use of

different stagesADD.D F0,F1,F2 IF ID A1 A2 A3 A4 ME WB

ADD.D F5,F6,F7 IF ID A1 A2 A3 A4 ME WB

ADD.D F0,F1,F2 IF ID A1 A2 A3 A4 MEW

B

ADD.D F5,F6,F0 IF ID ID I D ID A1 A2 A3 A4M

E

W

B

With Dependency


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EXAMPLE 3 Cannot be pipelined

DIV Unit is not Pipelined. So second instructionwaits in ID stage although it is independent.

1 2 3 4 5 6 7 26 27 28

DIV.D F0,F1,F2 IF IDD I

V

1

D I

V

2

D

I

V

3

D

I

V

4

D

I

V

5

o

o

o

D

I

V

24

M

EWB

DIV.D F5,F6,F7 IF ID IDI

D

I

D

I

D

o

o

o

ID

D

I

V

1


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Example 4 - Out Of Order Execution

L.D F10,0(R2) IF ID EXE

ME

M

WB

ADD.D F0,F1,F2 IF ID A1 A2 A3 A4 MEM

WB

ADDI R5, R5, 10 IF ID EXE

ME

M

WB

Mul.D F9,F6,F7 IF ID M1 M2 M3 M4 M4 M5 M6 M7 MEM

WB

Add R3,R9,R10 IF ID EXE

EX

E

ME

M

WB

Sub R7,R8,R10 IF ID ID EXE

ME

M

WB

Note All Instructions Independent

Out Of Order Completion (delay in 4th instruction as twoinstructions cannot be in MEM at same time.


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Example 4 - Out Of Order Execution

L.D

F10,0(R2)

IF ID E

X

E

M

E

M

W

B

ADD.D

F0,F1,F2

IF ID A1 A2 A3 A4 M

E

M

W

B

ADDI

R5, R5, 10

IF ID E

X

E

M

E

M

W

B

Mul.D

F9,F6,F7

IF ID M

1

M

2

M

3

M

4

M

5

M

6

M

7

M

E

M

W

B

Add

R3,R9,R10

IF ID E

XE

E

XE

M

EM

W

B

Sub

R7,R8,R10

IF ID ID EX

E

M

E

M

W

B

Note All Instructions Independent

Out Of Order Completion (delay in 4th instruction as twoinstructions cannot be in MEM at same time.


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Example 5 No Data Dependencies

Clock Cycle Number

1 2 3 4 5 6 7 8 9 10 11

Mul.D F0,

F1, F2

Add R1, R2,R3

SUB R5,R6,R7

Add.D F4,

F5, F6

OR R10,

R11, R12AND R20,

R21, R22

L.D F0,

0(R5)


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Example 5

Clock Cycle Number

1 2 3 4 5 6 7 8 9 10 11

Mul.D F0,

F1, F2

IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB

Add R1, R2,R3

IF ID EX MEM WB

SUB R5,R6,R7 IF ID EXE MEM WB

Add.D F4,

F5, F6

IF ID A1 A2 A3 A4 MEM WB

OR R10,

R11, R12

IF ID EXE MEM WB

AND R20,

R21, R22

IF ID EXE MEM WB

L.D F0,

0(R5)

IF ID EXE MEM WB

Structural Hazard in MEM/WB stage (solution next page)


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Example 5 solutionClock Cycle Number

1 2 3 4 5 6 7 8 9 10 11

Mul.D F0,

F1, F2

IF ID M1 M2 M3 M4 M5 M6 M7 ME

M

WB

Add R1, R2, R3 IF ID EX ME

M

WB

SUB R5, R6,R7 IF ID EX

E

ME

M

WB

Add.D F4,F5, F6

IF ID A1 A2 A3 A4 A4 MEM WB

OR R10,

R11, R12

IF ID EXE MEM WB

AND R20,

R21, R22

IF ID EXE ME

M

WB

L.D F0,

0(R5)

IF ID EX

E

EX

E

EXE ME

M

WB

Structural Hazard solution (could be by stalling in ID which is easy to implement or in the

very last state as shown but may be difficult to implement. We need a special hardware tomonitor when an instruction is going to complete to avoid structural hazard).


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Example 6 - WAW1 2 3 4 5 6 7 8 9 10 11 12 13

MUL.D F3,F1,F2

ADD.D F1,F5,F4

ADD.D F3,F9,F12


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Example 6 - WAW

1 2 3 4 5 6 7 8 9 10 11 12 13

MUL.D F3,F1,F2 IF I

D

M

1

M

2

M

3

M

4

M

5

M

6

M

7

M

E

M

W

B

ADD.D F1,F5,F4 IF ID

A1

A2

A3

A4

ME

M

WB

ADD.D F3,F9,F12 IF I

D

I

D

I

D

I

D

I

D

I

D

I

D

I

D

A

1

A

2

Reg Busy bit in Register File

A particular processor it waits in ID stage in case of WAW not in WB, Page A-54, Paragraph 2


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Example 7

L.D F4, 0(R2)

MUL.D F0,F4,F6

ADD.D F2,F0,F8

S.D F2,0(R2)


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Example 8 - EXCEPTIONS

DIV.D F0,F1,F2

ADD.D F10,F10,F8SUB.D F12,F12,F14


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Data Hazards

RAW Hazard

ADD.D F3, F1, F2

SUB.D F5, F6, F3

WAW Hazard

DIV.D F3, F1, F2SUB.D F3, F6, F5

WAR HazardDIV.D F3, F1, F2SUB.D F5, F6, F3 #(F3 may read value from ADD)

ADD.D F3, F6, F7


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Problem A-2 Done on Handouts in the

class

In doing this or similar problems:

All stalls including WB structural hazards arein ID/Last stage.

WAW stalls are also in ID stage.

Notice a lot of ID stage stalls?


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TOO MANY IDSTAGE STALLS SOLUTION?

Comp+Arch+Wk+6 Interrupts+++FP+Pipeline Aut09

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