Comparative Evaluation of a Full-and Partial-Power ...€¦ · Comparative Evaluation of a Full- and Partial-Power Processing Active Power Buffer for Ultra-Compact Single-Phase DC/AC

copy 2020 IEEE

IEEE Journal of Emerging and Selected Topics in Power Electronics (Early Access)

Comparative Evaluation of a Full- and Partial-Power Processing Active Power Buffer for Ultra-Compact Single-Phase DCAC Converter Systems

D NeumayrG KnabbenE VaresconD BortisJ W Kolar

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This article has been accepted for publication in a future issue of this journal but has not been fully edited Content may change prior to final publication Citation information DOI 101109JESTPE20202987937 IEEEJournal of Emerging and Selected Topics in Power Electronics

Comparative Evaluation of a Full- and Partial-PowerProcessing Active Power Buffer for Ultra-Compact

Single-Phase DCAC Converter SystemsDominik Neumayr Member IEEE Gustavo C Knabben Student Member IEEE Elise Varescon

Dominik Bortis Member IEEE and Johann W Kolar Fellow IEEEPower Electronic Systems Laboratory ETH Zurich Switzerland

Corresponding Author Dominik Neumayr ETL I12 Physikstrasse 3 8092 Zurich SwitzerlandE-Mail neumayrlemeeethzch Tel +41 44 633 83 58

AbstractmdashOne of the key technical challenges of the Googleamp IEEE Little Box competition an international contest to buildthe worldrsquos smallest 2 kW single-phase inverter in 2015 wasto shrink the volume of the energy storage required to copewith the twice mains-frequency (120Hz) pulsating power at theAC side and meet the stringent 25 input voltage ripple atthe DC side In this paper first a full-power processing buck-type converter active buffer approach selected by the 1st prizewinner of the Little Box Challenge (LBC) is analyzed in detailBeing relieved from strict voltage ripple requirements a largervoltage ripple is allowed across the buffer capacitor significantlyreducing the capacitance requirement Second a partial-poweractive buffer approach selected by the 2nd prize winner of theLBC where conventional passive capacitive buffering of the DC-link is combined with a series-connected auxiliary converter usedto compensate the remaining 120Hz voltage ripple across the DC-link capacitance is studied in detail In this paper both selectedconcepts are comparatively evaluated in terms of achievableefficiency power density and ripple compensation performanceunder both stationary and transient conditions Novel controlschemes and optimally designed hardware prototypes for bothconsidered buffer concepts are presented and accompanied withexperimental measurements to support the claimed efficiency andpower density and assess the performance of the implementedcontrol systems Finally by means of comparison with conven-tional passive DC-link buffering using only electrolytic capacitorsit is determined at what voltage ripple requirement it actuallybecomes beneficial in terms of volume to employ the consideredactive buffer concepts

Index TermsmdashPower Pulsation Buffer Active Power Decou-pling Series Voltage Injector Partial-Power Converter GoogleLittle Box Challenge

I INTRODUCTION

In order to achieve a cost reduction in solar power andpromote wide bandgap (WBG) power semiconductors for thenext generation of high efficiency and ultra-compact powerelectronics Google and IEEE launched the Little Box Chal-lenge (GLBC [1]) in 2015 aiming for a massive power densityenhancement of a 2 kW single-phase DCAC converter systemcompared to state-of-the-art technology advertising $1 millionprize money

One of the key technical challenges in the implementa-tion of the Google Little Box was to shrink the volume of

the energy storage required to cope with the twice mains-frequency (120 Hz) pulsating power at the AC side whilemeeting the stringent 25 (10 V pk-pk)1 input voltage rippleThe additional challenging technical requirements as listed inTab I and the attractive prize money created a remarkableinterest in the power electronics community which led to theparticipation of 2000+ teams ndash companies research institutesconsultants and universities ndash in the GLBC Finally 100+teams submitted technical descriptions of realized systemsOut of these applications 18 finalists [2] were selected topresent their technical approaches and hand over their proto-types to the National Renewable Energy Laboratory (NREL)Golden (Co) USA for final testing The team from theBelgian company CE+T Power was finally awarded the grandprize of $1 million for the most compact inverter passing alltests eg also the 100 hours testing achieving a power densityof 872 kW

dm3 (1429 Win3) and a CEC weighted efficiency of

1The specified 20 input current ripple limit (cf Tab I) is more stringentand for the stated Rs = 10 Ω input resistor implies a 25 (10 V pk-pk)limit for the maximal permissible 120 Hz input voltage ripple

TABLE IKEY INVERTER SPECIFICATIONS OF THE GOOGLE LITTLE BOX

CHALLENGE

Parameter Requirement

Input Voltage Source 450 Vdc with Rs = 10 Ω

Output Voltage amp Frequency 240 Vrms60 Hz

Maximum Apparent Output Power S 2 kVA

Power Factor 07 1 lead amp lagMaximum Load Steps 500 W

Power Density gt 3 kW

dm3 (gt 50 Win3)

CEC Efficiency ge95

Lifetime (Test Duration) gt 100 h

Max Outer Enclosure Temperature le 60 C

DC Input Voltage Ripple (120 Hz) le 25 (ie le 10 V pk-pk)DC Input Current Ripple (120 Hz) le 20 (ie le 1 A pk-pk)GroundLeakage Current le 50 mA (initially le 5 mA)Electromagnetic Compliance FCC Part 15BCISPR11 Class BAC Output VoltageCurrent THD lt5

Authorized licensed use limited to ETH BIBLIOTHEK ZURICH Downloaded on April 162020 at 115812 UTC from IEEE Xplore Restrictions apply



2

954 The 2nd and 3rd place was awarded to the team fromSchneider Electric for achieving a power density of 61 kW

dm3

(100 Win3) and to the team from Virginia Tech for achievinga power density of 43 kW

dm3 (70 Win3) with their converterprototypes respectively

One strategy followed by the majority of the GLBC finaliststo reduce the size of the energy storage conventionally real-ized with passive capacitive DC-link buffering using bulkyelectrolytic capacitors is to employ an additional converterwith dedicated buffer capacitor to enable a wide feasiblecapacitor voltage fluctuation ∆vb which according to

∆E = Cb middot Vb∆vb (1)

wherein ∆E denominates the alternately stored and releasedenergy of the buffer results in a significantly reduced buffercapacitance size Cb and thus lower overall converter volumedespite the additional power electronic components The win-

ning team from CE+T Power selected the Parallel CurrentInjector (PCI) approach as shown in Fig 1 (a) where thebuffer converter connected in parallel at the converter DCinput injects current ib to compensate the fluctuating portionof current iinu = pacVdc which results in a constant inputcurrent is and consequently in a constant voltage at theconverter input The depicted setup with Vs = 450 V DCsource and Rs = 10 Ω input resistor was specified in thetesting requirements of the GLBC [1] [2] The synchronousbuck-type implementation of the PCI converter with totem-pole bridge-leg HF filter inductor and buffer capacitor asshown in Fig 1 (c) was chosen by the team of CE+T Powerfrom several available options discussed in literature [3]ndash[9]

A different approach as depicted in Fig 1 (b) was followedby the 2nd prize winner of the GLBC [10]ndash[12] In thisapproach conventional passive capacitive buffering of the DC-link is used however the total installed capacitance value is

t

Is

ib

i =Vdc

AC

DC

AC

DC

Cdc

pac

Vdc

t

vCf

Vs

RsRsis

+minus

+ minus

idc+

minus

ib

Vs

is

+minus

iac iac

+

minusvac

+

minusvac

DC inputDC-link AC output DC input DC-link AC output

+

minus

vdc

+

minus

Vin

t

Is

idc

vCf

i =Vdc

pac

pPPB = IS vaux

pFPB = Vdc ib

vdc

t

vdc=Vin

(a)

(c) (d)

(b)

RSiS

+

minusVS

450 V

10 Ω

+ +minus minus

Cb

Cdc

idc

iinuiinu

ib

iinuiinu

+

+

minus

minusvfb Lf

Cf

vCf

+

minus

Vin

Zl

iac

iLf

iCf

iCb

+

minus

vac

DC

AC

vbvdc

+

minusvb

Cb

Cdc

RS

ZlLf

iS

iLf

iac

+

minus+

minusVS

vac450 V

450 V 450 V

DC

AC

10 Ω

10 Ω 10 Ω

+

minus

Vin=Vdc

Vin=Vdc

Fig 1 (a) Full-power processing Parallel Current Injector (PCI) active power buffer concept with characteristic waveforms (b) Partial-power processingSeries Voltage Injector (SVI) buffer concept with characteristic waveforms (c) Synchronous buck converter implementation of the PCI converter (d) H-bridgebased implementation of the SVI converter The depicted setup with Vs = 450 V DC source and Rs = 10 Ω input resistor is in accordance with the technicaltesting requirements of the Google Little Box Challenge (GLBC) [1] [2]




3

less then what would be actually needed to comply with the25 voltage ripple requirement In order to meet the specifiedinput voltage ripple an additional Series Voltage Injector(SVI) converter impresses voltage vCf which compensates the120 Hz voltage ripple still present in vdc resulting in a constantinput voltage Vin Fig 1 (d) shows the implementation of theSVI converter based on a H-bridge with LC output filter andflying buffer capacitor Cb selected by the team from SchneiderElectric

The key advantage of this concept is that the SVI convertercan be implemented with low-voltage (LV) components andonly processes a small share of the entire fluctuating powerpSVI = Is middot vCf asymp 100 W since for a defined DC-linkcapacitance size of around 400 microF - 600 microF the amplitudeof vCf required to compensate the remaining voltage rippleonly amounts to approximately 20 V and Is = 5 A in thenominal operating point (cf Tab I) For the remainder of thiswork [SVIC] denominates the combination of the partial-power SVI converter and the DC-link capacitor which jointlyperform the buffering of the 120 Hz pulsating power

On the contrary the PCI buffer concept selected by thewinning team processes the entire fluctuating portion of the ACpower pPCI = Vdc middot ib = Vdc middot Is = 2 kW resulting in a loweroverall conversion efficiency particularly at light load of theoverall converter system However only a (non-electrolytic)single buffer capacitor is required which could result in amore compact design compared to the SVI approach whereboth a DC-link capacitor and an additional buffer capacitorCb are needed It should be noted that Cdc asymp 15 microF shown inFig 1 (b) is only intended to filter HF switching noise Alsonote that unlike in case of the [SVIC] buffer there is nodistinction between the denomination ldquobufferrdquo and ldquoconverterrdquoin case of the full-power PCI approach ie ldquoPCI bufferrdquo andldquoPCI converterrdquo are synonyms for the remainder of this work

Although the use of active power buffer concepts in variousconfigurations to cope with the 120 Hz pulsating power insingle-phase system has already been studied in literature inrecent years [13]ndash[23] a direct multi-objective performancecomparison of a full-power PCI buffer and a [SVIC] bufferapproach particularly for the technical requirement of theGLBC (cf Tab I) has not been presented so far For this rea-son the main contribution of the work presented in this paperis the comparative evaluation of the PCI and [SVIC] bufferconcepts in terms of achievable efficiency η power density ρand input voltage variation compensation performance underboth stationary and transient conditions and consequently toassess whether the team from CE+T Power had a significantadvantage by choosing the PCI concept for their Google LittleBox inverter design

Due to the numerous degrees of freedom in the designof the buffer converters eg capacitance value and capaci-tor technology (aluminum electrolytic and ceramic capacitortechnology) bridge-leg control (conventional PWM or zerovoltage switching Triangular Current Mode [24]) switchingfrequency etc a design optimization is carried out and theηρ-Pareto fronts are determined for both considered conceptsin order to estimate the maximal achievable performance andallow a fair comparison In previous work of the authors [6]

the Pareto optimization and the hardware implementation ofthe PCI concept was described in detail The main findingsare summarized and complemented with latest experimentalresults in Section II-A - Section II-C of this paper Likewiseas presented in [6] for the PCI a mathematical model ofthe capacitor voltages is derived in Section III-A for the[SVIC] buffer and subsequently used in the design optimiza-tion outlined in Section III-B A control system for the SVIconverter is proposed in Section III-C and the implementedhardware demonstrator is described in detail in Section III-Dincluding experimental measurements to assess the achievedperformance under stationary and transient conditions Theobtained optimization results and the achieved ηρ-performanceof the implemented prototypes of both considered conceptsare then discussed and comparatively evaluated in Section IVMoreover a comparison between conventional passive buffer-ing with solely electrolytic DC-link capacitors and the inves-tigated optimally designed PCI and [SVIC] buffer conceptsis provided indicating at which voltage ripple limit it actuallybecomes beneficial to implement an active power bufferFurthermore a short discussion on the implementation cost ofthe investigated active power buffer concepts will be providedSection V concludes the paper and summarizes the mostimportant findings

II FULL-POWER PARALLEL CURRENT INJECTOR (PCI)POWER BUFFER

A PCI Converter Pareto Optimization

Despite the reduced capacitance requirement the buffercapacitor still comprises a large portion of the active buffersrsquooverall volume Thus the selected capacitor technology de-fines to a large extend the resulting power density and playsa critical role in the optimal design of the PCI converter Inprinciple the design of the PCI converter is independent ofthe implemented inverter topology however the reactive powerconsumption of the installed EMI filter on the AC-side also hasto be considered The PCI is controlled to fully compensate thefluctuating power resulting from the load and the EMI filter ofthe inverter stage As a consequence only a constant power Psmust be provided by the power supply Vs and vdc is relievedfrom the twice mains-frequency voltage ripple Accordinglythe PCI must be dimensioned to cope with the apparent power

Sb =radicP 2

ac + (Qac +Qfilt)2 (2)

wherein Qfilt is the reactive power of the main DCAC con-verterrsquos EMI filter (not shown in Fig 1 (c)) The instantaneouspower provided by the PCI buffer can be calculated accordingto

pb = vb middot iLf + vLb middot iLf = vb middot iLf + Lf middotd

dtiLf middot iLf asymp vb middot iLf (3)

Neglecting the power contribution of the PCI inductor isreasonable because when a mean buffer capacitor voltageof Vb = 300 V and a reasonable inductor value of 20 microH isconsidered then the peak power in the inductor only amountsto

pLf = ωLf i2Lf = ωLf

(2 kW

300 V

)2

= 335 mW




4

Vol

tage

(V)

0

100

200

300

400

0

vb(t) Cbmin

vb(t) 2 ∙ Cbmin

vb(t) approx 2 ∙ Cbmin

Fig 2 Full-power Parallel Current Injector (PCI) converter buffer capacitorvoltage for different capacitance values

The fluctuating power is fully compensated if

vb(t) middot iLf(t) = poutac(t) = Sb cos(2ωtminus φ) (4)

where φ = arctan ((Qac+Qfilt)Pac) Inserting the volt-agecurrent relationship of the buffer capacitor yields thedifferential equation

vb middot Cbdvbdt

= Sb cos(2ωtminus φ) (5)

with the analytical solution

vb(t) =

radicV 2

b0 minusSb sin(2ωtminus φ)

ωCb (6)

wherein Vb0 is the RMS value of vb(t) and also correspondsto the initial buffer capacitor voltage at t = φ

2ω (cf t = 0 inFig 2) Now if the capacitance is chosen much larger thanthe minimum requirement

Cb gtgt Cbmin =2SbωV 2

dc

= 663 microF (7)

(6) can be approximated by means of

vb(t) asymp Vb0 minus1

2

Sb sin(2ωtminus φ)

ωCbVb0 (8)

as shown in Fig 2 for Cb = 2 middot Cbmin asymp 130 microF and Vb0 asymp280 V

On the one hand the large feasible amplitude of the voltageripple enables the use of thin-film and ceramic capacitorsbecause of the much smaller needed capacitance values com-pared to conventional passive capacitive DC-link bufferingOn the other hand the large voltage ripple and the DC biasmakes the design of the buffer capacitor more challengingespecially in case of ceramic capacitor technology with non-linear capacitance-voltage relationship

Identified as the two most promising ceramic capacitorsfor large voltage swing buffer applications a comprehensiveperformance analysis of TDKrsquos 22 microF450 V class IIX6Scapacitor [25] [26] and EPCOSTDKrsquos 2 microF500 V 2nd gener-ation CeraLink [27] was carried out In particular as depictedin Fig 3 the capacitance ( microF

cm3 ) and loss density ( Wcm3 ) at 60 C

1000 200 300 4000

100

200

300

400

4681012141618202224

1000 200 300 4000

100

200

300

400

4681012141618202224

0 100 200 300 4000

100

200

300

400

0 100 200 300 4000

100

200

300

400

500

V C

eraL

ink

Capacitance Density (microF cm3) Loss Density (Watt cm3)

450

V

X6S

MLC

C

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vacpp (V)

Vacpp (V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vacpp (V)

Vacpp (V)

Fig 3 Contour plot of capacitance density and loss density of a 500 VCeraLink and 450 V class IIX6S capacitor technology with respect to DCbias Vdc and 120 Hz AC excitation Vacpp at 60 C operating temperature

TABLE IISYSTEM PARAMETERS amp SEARCH LOCUS OF THE PCI CONVERTER

PARETO OPTIMIZATION

Feature RangeOption

Capacitor Technology450 V class IIX6S500 V 2nd generation CeraLink

Cb [110 microF 350 microF]

Vb0 12Cb middot V 2b0 isin

[E0min E0max

]Em 5 - 30

Inductor Technology N87 MnZn ferrite HF litz wireLf [10 microH 60 microH]

ModulationTCM fs from 200 kHz to 1 MHz

PWM fs = 140 kHz

Heat sink CSPI = 257 W

Kdm3

operating temperature as a function of applied DC bias andlarge-signal 120 Hz AC ripple was experimentally measuredIn a characteristic PCI buffer operating point ie a buffercapacitor voltage with 300 V DC bias and a 130 Vpp super-imposed AC voltage the X6S MLCC features a capacitancedensity of 84 microF

cm3 as opposed to the slightly higher 95 microF

cm3

of the CeraLink However the loss density of the X6S MLCCamounts to just 56 mW

cm3 By contrast the CeraLink dissipatesroughly 1 W

cm3 in the very same operating pointAccording to (8) and a particular value of Cb and Vb0 from

the considered design space listed in Tab II the operatingpoint of the buffer capacitor can be calculated Given thisoperating point and a ceramic material from the design spacethe prevailing large-signal capacitance density is extractedfrom the empirical dataset (cf Fig 3) This allows to accu-rately calculate the number of single capacitor chips mountedin parallel to meet the requested large-signal capacitancevalue Cb despite the non-linear behavior of the consideredceramic materials Likewise the power losses occurring in




5

the capacitor assembly caused by continuously storing andreleasing

∆E =Sbω

= 531 J (9)

is extracted from the experimental measurements (cf Fig 3)Additional losses due to the high frequency current ripple iniLf is negligible since the ESR of the buffer capacitor assem-bly is vanishingly low at the considered switching frequenciesMoreover Vb0 the RMS value of the buffer capacitor voltageor the mean buffer voltage according to (8) can be adjustedby the employed control system as proposed in Section II-Band is considered a further degree of freedom in the designDepending on the large-signal ripple and bias properties of therespective capacitor technology different bias voltages mightlead to the optimal design However in order to have enoughenergy margin to cope with load transients the bias voltagemust be kept within certain bounds Specifically given Cb thenVb0 must be chosen such that

12Cb middot V 2b0 isin [E0min E0max] (10)

where the interval boundaries of the mean energy E0 are givenby

E0min = Em +∆E

2 E0max = Emax minus Em minus

∆E

2

with the maximal energy

Emax = 12CbV2dc

and an empirically chosen energy margin in the range of

Em = (5 minus 30 of ∆E)

Besides the buffer capacitor a compact implementation of thePCI half-bridge and the HF filter inductor is also vital In[28] [29] GaN was identified as the key power semiconductortechnology for the implementation of ultra-compact converterdesigns for the Google Little Box Challenge For the imple-mentation of the half-bridge 600 V 70 mΩ CoolGaN devicesform Infineon in combination with a novel high-performancegate drive circuit [28] are considered The bridge-leg is op-erated with a Triangular Current Mode (TCM) modulationscheme [24] where the onoff intervals of the power transistorsare adjusted such that a triangular current is impressed in thebridge-leg filter inductor and Zero Voltage Switching (ZVS)is achieved in all operating points Due to reduced switchinglosses and accordingly reduced heat sink volume a higherefficiency and higher power density is expected when TCMis applied Moreover a rather high switching frequency inthe range of 200kHz-1MHz results in a significantly reducedvolume of the inductor However as outlined in [28] therequired large HF current ripple leads to increased conductionlosses which reduces the gain of soft-switching resulting fromTCM Therefore also conventional PWM is considered for thebridge-leg since the large turn-on switching losses associatedwith PWM can be reduced when a relatively high currentripple is allowed (ZVS around the current zero crossings) In[30] advanced models for winding and core loss calculationand thermal models for HF inductor design are presented

Adopting these models to a large variety of available coregeometries N87 MnZn ferrite material and available HF-litzwires an optimal inductor in terms of volume can be identifiedfor a given inductance value and current waveform Thegenerated power losses are extracted by means of an optimizedforced-air cooled heat sink with a experimentally verifiedCooling System Performance Index (CSPI) of 257 W dm3

K asdescribed in more detail in [29]

Given the design space as summarized in Tab II andelaborate loss and volume models of the utilized componentsthe performance of several PCI converter configurations wascalculated Fig II-A (a) displays the performance of thecalculated designs in the ηρ-performance space In particularPCI converter designs with class II and CeraLink capacitorsboth either with TCM or conventional PWM operation aredistinguished by color As reference the ηρ-performance of aconventional DC-link assembly which will be introduced laterin Section IV is also shown Clearly noticeable designs withclass IIX6S ceramic outperform those with CeraLink capaci-tors The highest power density of 413 kW

dm3 (6771 Win3)and an efficiency of 994 (P2) is achieved with TCMmodulation Cb = 110 microF with class IIX6S capacitors andLf = 30 microH As discussed previously the CeraLink capac-itors exhibits much higher 120 Hz losses compared to theclass IIX6S capacitors which explains the drop in efficiency ofthe PCI converter designs with CeraLink capacitors as shownin Fig II-A (a) and the reduction in power density due to thehigher cooling effort As a consequence power density optimaldesigns with class IIX6S (P2) (P3) feature a low total buffercapacitance around 110 microF accordingly a large 120 Hz voltageripple with asymp 180 Vpp amplitude and a mean voltage Vb0

of 300 V On the other hand optimal designs employing theCeraLink capacitor feature comparably high total capacitancevalues of asymp 200 microF and a consequently low voltage ripplewith asymp 80 Vpp amplitude in order to to keep the lossessmall Moreover since the capacitance density of the CeraLinkcapacitors increases with applied bias optimal results (P4)(P5) exhibit increased bias voltages Vb0 asymp 330 V minus 340 VIn order to show the impact of the bias voltage on theoverall performance of the CeraLink PCI buffer and betterreflect the performance of the actually realized prototype (cfSection II-C1) the optimization results for a fixed bias voltageof Vb0 = 300 V which corresponds to a more conservativeenergy margin of Em = 30 are also included in Fig II-A

Also noticeable in the ηρ-space designs using TCM mod-ulation feature higher efficiency compared to PWM operationwith fs = 140 kHz Naturally designs (P2)-(P5) with maxi-mum power density tend towards the lowest energy marginsas specified in the design space (cf Tab II)

The volume of the PCI converter is clearly dominated bythe buffer capacitor as shown in Fig II-A (b) Also thevolume required for cooling is significant especially in thecase of design (P6) As stated earlier optimal designs usingCeraLink feature a higher total buffer capacitance conse-quently occupying more volume The loss distribution of theoptimal designs is given in Fig II-A (c) revealing the almostnegligible losses occurring in the class IIX6S designs (P2)(P3) and the almost 7 times higher losses in the CeraLink




6

ρ - Power Density (kWl)10 15 20 25 30 35 40 45

η - E

ffic

ienc

y (

)

985

9875

99

9925

995

9975

100

TCM X6S TCM CeraLink TCM CeraLinkVb0 = 300 V FixedPWM CeraLinkPWM X6S

(P2)(P3)

(P4)

(P6)

(P1)

(H1)

(P5)

Electrolytic capacitors

(a)

(b)

(c)

Loss

es (W

att)

0

5

10

15

20

25

30

Buffer CapacitorPower Semiconductor

InductorAdditional

Cooling

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

(P2) (P3) (P4) (P5) (P6)124

549

394

086

124

444

507 864 864

1679

34

487

158

264 242

304626

054

2664

10411291153

0881820

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

Vol

ume

(cm

3 )

0

20

40

60

80

(P2) (P3) (P4) (P5) (P6)

4771

1498

1728

697419429

1467

1728

1113419387

1995

2503

6612419482

2362

2503

691419440

60606415

346

1971

697419521

7068

5114

1536

(H2)

Realized Design Design With Max Power Density

Results of the PCI converter design optimization (a) ηρ-plotof the calculated designs with indicated Pareto fronts

(b) Volume distribution of the optimal designs (P2)-(P6)(c) Loss distribution of the optimal designs (P2)-(P6)

designs (P4) (P5) Surprising are the dominating losses inthe CeraLink capacitor of the pragmatic design (P6) whichdrastically reduces efficiency and substantially increases theheat sink volume Clearly the buffer capacitor operating pointoccurring at steady-state in design (P6) is not optimal giventhe characteristics of the CeraLink The category Additionalshown in Fig II-A (b) amp (c) includes the volume and lossdata of the current zero-crossing detector (required for TCMoperation) analog measurement circuits metal enclosure ofthe PCI converter and the power consumption of the heatsink fans respectively Given the gained insights from theηρ-space of the calculated designs it is clearly advisable torealize a PCI converter using class IIX6S capacitors Howeverpractical manufacturing considerations have to be includedin the decision making In order to realize 110 microF roughly150 single class IIX6S chips must be mounted in parallelWith the known issue of ceramic cracking due to mechanicaland thermal stress this certainly requires advanced packagingtechniques in order to achieve a reliable assembly On theother hand the CeraLink capacitor is available in a packagewith 20 chips mounted in parallel by means of a silver sinteredconnection onto a common lead-frame which is able to absorbmechanical stress Two different PCI converter designs wereselected from the presented Pareto optimization results forhardware implementation (i) Due to the easier and morereliable assembly of the buffer capacitor it was decided torealize the 28 kW

dm3 (4588 Win3) design (P6) in hardwarewith Cb = 150 microF comprised of individual 2 microF CeraLinkcapacitors despite the higher losses the conservative energymargin of Em = 30 (Vb0 = 300 V) and TCM modulationof the bridge-leg (ii) Aiming at maximum power densitythe 384 kW

dm3 (6293 Win3) design (P3) with Cb = 110 microFcomprised of individual 22 microF450 V class IIX6S a biasvoltage Vb0 = 280 V and 140 kHz PWM operation of thebridge-leg was also selected for hardware implementationdespite the more challenging buffer capacitor assembly Theactually achieved 2612 kW

dm3 (428 Win3) power density and9865 efficiency of the implemented CeraLink-TCM proto-type is indicated with label (H1) in Fig II-A (a) Likewise theimplemented class IIX6S-PWM prototype with an achievedηρ-performance of 994 and 413 kW

dm3 (6768 Win3) asindicated with label (H2) Both implemented PCI converterprototypes will be described in detail in Section II-C

B Control System of the PCI converter

One of the downsides of using an active approach to copewith the 120 Hz power pulsation is the required controlsystem which increases the overall complexity of the DCACconverter The cascaded control system for the PCI converterproposed in [6] is depicted in Fig 4 and contains dedicatedsubsystems with the objective to (a) control the meanbiasvoltage of the buffer capacitor (b) achieve a tight controlof the DC-link voltage during load transients (c) compensatethe fluctuating AC power by proper current injection and (d)combine all control objectives into a single reference value forthe underlying inductor current control In order to completelyeliminate the DC-link voltage ripple feed-forward control of




7

the fluctuating portion of the AC power and an additionalresonant controller [31] tuned at even multiples of the ACfrequency are employed as shown in Fig 4 (c) If only controlaspects are considered then the reference of the mean PCIconverter capacitor voltage V lowastb is set to a voltage level

Vbmid = Vdcradic

2 = 2828 V (11)

corresponding to half of the maximal stored energy Maintain-ing the bias of the buffer capacitor at Vbmid results in symmet-rical energy margins and load step-up and step-down can behandled equally well However as outlined in Section II-Athe DC bias of the buffer capacitor strongly affects the ηρ-performance results since (i) the prevailing capacitance densityof the considered ceramic capacitors is strongly dependent onthe DC bias and (ii) the amplitude of current iLf is inverselyproportional to vb Therefore a compromise between transienthandling capability and ηρ-performance must be made Incase of the realized Ceralink-TCM and class IIX6S-PWMPCI converter prototypes presented in Section II-C of thispaper the reference voltage V lowastb is set to 300 V and 280 Vrespectively The inner loop of the cascaded control structure(cf Fig 4 (b)) is required to tightly regulate the average DC-link voltage under all load conditions Due to the cascadedstructure controlling the DC-link voltage has always priorityover the mean buffer capacitor voltage This has significantadvantages in case of abrupt load changes since the averagebuffer capacitor voltage Vb can be temporarily deflected fromthe reference V lowastb keeping vdc tightly controlled As can beseen the individual current reference values computed bythe control subsystems (a)-(c) are then combined in a singlecurrent reference ilowastLf and forwarded to the inner PWM currentcontrol loop (cf control subsystem (d)) If TCM modulation isemployed (not shown in Fig 4) the turn-on and turn-off times

of the power transistors are computed such that on averageover one switching cycle the current in the inductor meetsilowastLf and ZVS of the bridge-leg applies The interested readeris referred to [6] for more details

C Hardware Implementation and Experimental Verification

1) Version 1 - CeraLink and TCM Modulation The firstimplemented prototype (Version 1) of the PCI converter con-cept is shown in Fig 5 (a) As mentioned before the half-bridge is implemented with 600 V70 mΩ CoolGaN devicesIn order to reduce reverse conduction losses of the GaN tran-sistors during the dead-times 600 V SiC Schottky diodes fromWolfspeed are mounted in parallel to the power transistorsThe bridge-leg is operated with a TCM modulation schemewith variable switching frequency in the range of 200 kHz -1000 kHz that enables ZVS transitions in all operating pointsThe inductor Lf asymp 21 microH of the power buffer was realized by aseries connection of two 105 microH inductors implemented basedon a novel multiple-gap multiple parallel foil winding designusing the DMR51 low-loss HF MnZn Ferrite core materialfrom DMEGC The buffer capacitor Cb with a large-signalequivalent capacitance of 150 microF is implemented by meansof 108 individual 2 microF500 V CeraLink capacitors By thecourtesy of EPCOSTDK a custom package with 18 capacitorchips mounted together on silver coated copper lead frameswas available The design parameters and selected features ofthe realized system are summarized in Tab III

Combined with a 2 kW high power density inverter stagedesigned for the Google Little Box Challenge (cf Fig 5 (a))the constructed PCI converter was experimentally tested Ascan be seen from the picture the power buffer was designedas a stand-alone module which allowed to directly substitutethe electrolytic capacitor bank of a preliminary version of

Lf

Cb

vacVdc vb vT2

iac

vaciac

iLf

iLf

++

+ +vLf

vT2

divide

_

_ _

_

Db

Vb

vdc

vdcvdc

T2

T1

GT1

GT1

vb

_ + iCbVdc

+++ +_

__

Vbnom

Vdcnom

divide

divide

iac= iac=

pac

+_

pac~

pac=

Vbnom

Vb

VSRSVdcnom

Vdcnom

Vbnom

iLf

VS

iSiinuRS

iLf= iLf~ff

_

iLf~

DC

AC

PWMGT2

GT2

(c)(d)

R

(c) Power Feed-Forward amp Ripple Compensation

(a) Bias Voltage Control

(d) PWM Current Control

(b) DC-link Voltage Control

Fig 4 Proposed cascaded control structure of the PCI converter (a) Control of the average buffer capacitor voltage (b) Control of the DC-link voltage(c) Compensation of the pulsating power by means of feed-forward control and resonant compensators (d) Inner loop PWM current control of the inductorcurrent




8

TABLE IIITECHNICAL DETAILS OF THE CERALINK-TCM PCI CONVERTER

Feature Value DescriptionVolume (no cooling) 473 cm3 (29 in3) Boxed volume of the constructed PCI converter without coolerVolume (with cooling) 766 cm3 (47 in3) Total boxed volume of the PCI converter with a CSPI = 257 W

Kdm3

heat sinkCapacitor volume 246 cm3 (15 in3) Total volume of the installed buffer capacitorη 9865 Efficiency at 2 kW

Lf 21 microH Foil winding and custom shape multi-gap MnZn ferrite core with 2times 105 microH in series

Cb 150 microF Equivalent large signal capacitance of the installed CeraLink capacitors

TABLE IVTECHNICAL DETAILS OF THE CLASS IIX6S-PWM PCI CONVERTER


Kdm3

heat sinkCapacitor volume 199 cm3 (15 in3) Total volume of installed buffer capacitorη 994 Efficiency at 2 kW

Lf 40 microH HF litz wire and RM 10 MnZn ferrite core (N87)Cb 120 microF Equivalent large signal capacitance of the installed 200 times

22 microF450 V MLCC

the initial Google Little Box converter developed at ETH

Buffer Capacitor - Cb200 x 22microF450VX6S MLCC

(a)

(b)

HF Inductor - Lf

2 x 105 μH Shielded HF Inductor - Lf

Buffer Capacitor - Cb108 x 2microF500V CeraLink

FPB

FPB

Fig 5 (a) Picture of the Google Little Box 10 (1st version of the LittleBox inverter developed at ETH Zurich) with PCI converter using CeraLinkcapacitors and TCM control of the bridge-leg (b) Picture of the Google LittleBox 20 (2nd further optimized version of the Little Box inverter) with PCIconverter using class IIX6S MLCC and constant 140 kHz PWM

Zurich In order to extract the power losses an optimizedforced-air cooled dual-sided heat sink with an effective CSPIof 257 W

dm3 Kis utilized The heat sink has a height of

only 45 mm and employs 6 Sunon 5 V DC micro blowers(30times 30times 3 mm) per element (UB5U3-700) It should benoted that in Fig 5 (a) the top-side heat sink is removed Thenovel control system presented in Section II-B is implementedon a TMS320F28335 from Texas Instrumentrsquos C2000 32-bit family of microcontrollers As mentioned previously inSection II-B the PWM current control highlighted in Fig 4is substituted with a cycle-by-cycle TCM control wherebythe turn-on and turn-off intervals of the power transistors arecomputed on the microcontroller and then forwarded to amodulator implemented on a Lattice XP2 FPGA

2) Version 2 - Class IIX6S and PWM Benefiting fromthe gained insights of the design optimization in Section II-Acarried out in the aftermath of the GLBC a second prototypeof the PCI converter (Version 2) was implemented and thedesign parameters and selected features of the realized sys-tem are summarized in Tab IV For the sake of maximumpower density the implemented power pulsation buffer isunlike before not designed as stand-alone module but insteadincorporated in the inverter stage as can be seen from thepicture in Fig 5 (b) of the 2nd version of the Google LittleBox inverter developed at ETH Zurich The bridge-leg of thePCI converter Version 2 prototype is implemented with thesame 600 V70 mΩ CoolGaN technology but uses two parallelconnected transistors per switch and is operated with an EMIfriendly constant 140 kHz PWM instead of TCM modulationThe inductor of the active power buffer Lf = 40 microH isimplemented on a RM 10 core using the MnZn ferrite materialN87 from TDK The winding is realized with 20 turns of a225times 71 microm HF litz wire without additional silk insulation




9

PCI V1 (CeraLink)PCI V2(X6S MLCC)

Fig 6 Measured efficiency of the constructed PCI converter prototypes as afunction of the peak value of the processed apparent power Sb

The limbs of the RM 10 core were shortened with a diamondwheel precision saw to achieve a total air gap length of 2 mm(1 mm per limb) while keeping the total height of the coreunchanged The buffer capacitor Cb features an effectivelarge-signal equivalent capacitance of asymp 120 microF and wasrealized by means of 200 individual 22 microF450 V class IIX6SMLCC As can be seen from Fig 5 (c) 200 of these chipcapacitors were soldered together on a PCB which is on theone hand a very challenging assembly task and on the otherhand bears the risk of electrical failures due to micro-cracksin the ceramic material caused by mechanical stress duringassembly andor operation

The novel control system presented in Section II-B isentirely implemented on the TMS320F28335 microcontrollerBecause conventional PWM current control is employed(cf Fig 4) no additional FPGA is needed which simplifiessoft- and hardware development of the digital control system

3) PCI converter ηρ-performance The conversion effi-ciency of the active power buffer is defined according to

η = 1minus Pv

Sb(12)

where Pv denominates the losses of the PCI buffer whenprocessing the apparent power Sb of the main inverter withohmic load (cf (2)) The efficiency measured with a YokogawaWT3000 precision power analyzer of the CeraLink-TCMprototype at 2 kW rated power is 9865 as depicted in Fig 6which corresponds to 27 W of losses The total volume of therealized PCI converter including cooling volume amounts to766 cm3 which corresponds to a power density of 261 kW

dm3

(428 Win3)The measured efficiency of the class IIX6S-PWM proto-

type as also depicted in Fig 6 is around 994 at close to2 kW which corresponds to only about 12 W of losses at ratedpower The total volume of the realized PCI converter Version2 including cooling volume amounts to 484 cm3 which cor-responds to a power density of 413 kW

dm3 (677 Win3)As described in Section II-A the main reason for the

significantly higher efficiency of the second implementedversion of the PCI converter is that compared to the CeraLink

vb (50 Vdiv)iLf (10 Adiv)vdc (1Vdiv AC) iS (500 mAdiv AC)

Time (5 msdiv)

Fig 7 Steady-state performance of the realized PCI converter at 2 kW ratedpower The timebase of the measurement is 5 msdiv Probes for measuringthe converter input current and the DC-link voltage are AC coupled in orderto highlight the excellent ripple cancellation

capacitor technology the class IIX6S MLCC exhibit a muchlower power loss (asymp 15 W instead of asymp 173 W at 2 kW)when cycled at low frequency (120 Hz) with a large amplitudevoltage swing

4) Experimental Waveforms Since both versions of thePCI converter are using the same control systems and exhibitvery similar stationary and transient behavior for the sake ofbrevity only the experimental waveforms of the CeraLink-TCM prototype are presented in the following

The steady-state performance at 2 kW rated power of theimplemented PCI converter controller is illustrated in Fig 7It can be seen from the recorded DC-link voltage and theconverter input current (cf is in Fig 1 (c)) that the powerpulsation was successfully shifted from the DC-link to thebuffer capacitor which features a distinctive 100 Vpp 120 Hzvoltage ripple The inductor current waveform is a result of theemployed TCM modulation clearly showing the envelope ofthe double-line frequency charging currents In order to verifythe dynamic performance of the implemented control systemthe inverter was subject to load variations The transientperformance of the PCI converter subject to a load step from0 W to 700 W is depicted in Fig 8 (a) Triggered by the loadstep the average buffer capacitor voltage drops 50 V belowthe 300 V at steady-state Simultaneously the control systemof the PCI converter starts to compensate the power pulsationby means of injecting an appropriate current ib in the DC-linkAs a consequence a distinct 120 Hz voltage ripple developsat the buffer capacitor immediately after the load step Aftera transient time of 60 ms the average buffer capacitor voltagehas recovered and the intrinsic single-phase power pulsationis completely compensated by the PCI converter During thetransient a small ripple is visible in the DC-link voltageTake note that because of the Rs = 10 Ω input resistor(cf Fig 1 (c)) the average DC-link voltage decreases withincreasing power and therefore settles at a lower value afterthe transient The reactive power drawn by the EMI filter ofthe inverter stage is also compensated by the PCI converterthus a small ripple is present in the buffer capacitor voltage




10

Time (20 msdiv)(a)

vb (50 Vdiv)iS (2 Adiv)iLf (10 Adiv) vdc (50 Vdiv)

50 V100 V

Time (20 msdiv)(b)


192 V316 V

Fig 8 PCI converter transient response to (a) an abrupt load step from0 W to 700 W and (b) an abrupt load drop from 700 W to 0 W The timebaseof the measurement is 20 msdiv

prior to the load step although no load is connected to theinverter Analogously a step down from 700 W to 0 W isdepicted in Fig 8 (b) Prior to the load step the convertersystem was operating in steady-state exhibiting a 50 V peak-to-peak voltage ripple in the buffer capacitor Triggered bythe load drop the average buffer capacitor voltage temporarilyincreases up to 350 V and settles after approximately 60 msto the reference value The DC-link voltage remains tightlycontrolled during the entire transient showing virtually noovershoot but a small voltage ripple of asymp 5 V during thetransient

This surpasses the required performance specified in theGLBC technical requirements [1] where load steps of max-imal 500 W had to be handled within 1 s Due to the 10 Ωresistor of the application the DC-link voltage settles at ahigher value after the transient

III [SVIC] POWER BUFFER

A Mathematical Model of the [SVIC] BufferFor the setup of the [SVIC] buffer as depicted in Fig 1 (d)

the DC-link capacitor voltage is likewise to (6) given by

vdc(t) =

radicV 2

dc0 minusSb sin(2ωtminus φ)

ωCdc (13)

wherein Vdc0 is the RMS value of vdc(t) and also correspondsto the initial voltage at t = φ

2ω Moreover referring toFig 1 (b) it must hold that

vdc =1

T

int T

0

vdc(t)dt= VS minus IS middotRS (14)

Because the voltage ripple of the DC-link capacitor iscompensated by means of the SVI converter a much widervoltage swing across the DC-link is feasible The actual sizeof the DC-link capacitor is limited by the voltage requirementof the inverter to generate vac at the output For this reasonvdc(t) gt vac(t) has to be ensured at all times which requiresa minimum capacitance of

Cdcmin ge maxt


ω(V 2

dc0 minus (Vac cos(ωt))2) (15)

For φ = 0 (15) can be expressed analytically in a compactform

Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)

The operation of the system with minimal DC-link capaci-tance which amounts to Cdcmin asymp 6266 microF for the givensystem parameters is shown in Fig 9 (a) From a practicalpoint of view it is not reasonable to design the power bufferwith Cdcmin since there is no voltage margin and the largeresulting voltage ripple of plusmn100 V requires the SVI converterto generate high voltages and process power levels of up to500 W at rated output power Following a more conservativeapproach

mintvdc(t) ge Vac

minumax (17)

the minimum DC-link capacitance is given by

Cdcmin =Sb

ω(V 2dc0 minus (Vacminumax)2)

= 2984 microF (asymp 5 middot Cdcmin)

(18)

whereby |minu| le minumax = 09 is the maximum allowedmodulation index of the inverter Note that (17) is moredemanding compared to the condition

mintvdc(t) ge vac(t)

minumax (19)

As can be seen from Fig 9 (a) the peak value of the varyingvoltage only amounts to asymp plusmn20 V and consequently theSVI converter only processes up to 100 W at rated outputpower of the inverter and thus can be implemented withlow voltage (100 V) components Likewise to (8) selecting amore conservative DC-link capacitor size (Cdc gt 5 middot Cdcmin)allows to approximate the square root function in the analyticalexpression of the DC-link voltage

vdc(t) asymp Vdc0 minus1

2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS

vdc (Cdcmin) vdc (~5timesCdcmin)

vcf (~5timesCdcmin)vcf (Cdcmin)

mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex

iLf (Cf= 100 microF) iLf asymp IS (Cf= 10 microF)

iCb(Cf= 100 microF) iCb(Cf= 10 microF) mb

Fig 9 Simulated waveforms of the derived mathematical model of the[SVIC] buffer for different component values (a) Operation with theoreticalminimal installed DC-link capacitance Cdcmin and more practical relevantdimensioning with Cdcmin = 5Cdcmin (b) Impact of the size of theswitching ripple filter capacitor Cf on average buffer capacitor current iCbThe averaging introduced by the duty cycle variation of the SVI results in asimilar average buffer capacitor current iCb regardless of whether the filterinductor current iLf is approximately constant or features are pronouncedsuperimposed twice mains-frequency harmonic component (c) Operation withtheoretical minimal installed buffer capacitance Cbmin and more practicalrelevant dimensioning with Cbmin asymp 14Cbmin

In order to compensate the remaining DC-link voltage rippleand meet the technical specifications the required voltageacross the filter capacitor Cf is given by

vCf(t) = minus1

2


ωCdcVdc0 (21)

The current in the filter inductor Lf averaged over the switch-ing cycle can then be expressed by

iLf(t) = Cf middotdvCf

dtminus IS asymp minusIS (22)

Typically for a small filter capacitance Cf asymp 10 microF theamplitude of the capacitive charging currents to meet the low-frequency (LF) sinusoidal compensation voltage is negligi-

ble compared to the ideally constant DC source current ISInterestingly for the sizing of the buffer capacitor this ap-proximation also holds for much larger filter capacitor valuesFig 9 (b) depicts the switching cycle averaged buffer capacitorcurrent iCb = mbiLf with constant filter inductor current(iLf asymp minusIS) and with pronounced ripple at twice the ACfrequency considering a large filter capacitor Cf = 100 microFBecause of the averaging introduced by the duty cycle varia-tion to generate the sinusoidal voltage at the SVI converteroutput the resulting buffer capacitor charging currents arenearly identical This also explains why the buffer capacitordoes not exhibit a voltage ripple at a quadruple of the ACfrequency while generating a sinusoidal voltage with twicethe fundamental AC frequency at the SVI converter outputIn order to ensure vCf according to (21) the H-bridge circuitmust generate

vfb = vCf minus vLf = vCf minus LfdiLf

dtasymp vCf (23)

at its output terminals on average with respect to the switchingcycle Even for a large filter inductance Lf = 100 microH and alarge peak value of the 120 Hz superimposed charging currentof asymp 15 A (cf Fig 9 (b)) the amplitude of the voltagedrop across the inductance only amounts to around 100 mVand is therefore negligible compared to vCf Based on theseapproximations the differential equation governing the buffercapacitor voltage can be expressed as

Cbdvb

dt= mb middot iLf = minusvcf

vbIS (24)


vb(t) =

radicV 2

b0 +ISSb cos(2ωtminus φ)

2ω2CbCdcVdc0 (25)

whereby Vb0 is the RMS value of the buffer capacitor voltageand represents the initial voltage at t = φminusπ2

2ω Similar to thederivation of the minimum DC-link capacitance it must holdthat vb(t) ge vCf(t) at all times which allows to calculate thetheoretical minimum value of the installed buffer capacitance

Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)

resulting in Cbmin = 1179 microF for a given bias voltage ofVb0 = 50 V Similar to the PCI power buffer concept theoffset or average voltage of the buffer capacitor is a degreeof freedom which will be exploited in the design optimizationdescribed in the next section The simulated waveforms foroperation with minimal buffer capacitance are depicted inFig 9 (c) The buffer capacitor is fully utilized since itsvoltage drops to zero after every buffer cycle As pointed outpreviously for a practical implementation it is by far morereasonable to dimension the buffer capacitor to meet

mintvb(t) ge Vcf

mbmax (27)

whereby |mb| le mbmax = 09 is the maximal allowedmodulation index of the H-bridge (cf Fig 1 (d)) and Vcf is




12

the crest value of the filter capacitor voltage vcf With thiscondition the minimum buffer capacitor size is given by

Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)

As can be seen from the waveforms in Fig 9 installing atleast 2 middot Cbmin asymp 240 microF of buffer capacitance allows toapproximate the exact buffer capacitor voltage (25) with

vbasymp(t) asymp Vb0 minus1

4

ISSb cos(2ωtminus φ)

ω2CbCdcVdc0Vb0 (29)

Likewise to the PCI converter the dimensioning and losscalculation of the DC-link and buffer capacitor of the [SVIC]buffer relies on the approximated waveforms given by (20) and(29)

B [SVIC] Pareto Optimization

As described in the previous section the minimum DC-linkvoltage requirement of the inverter stage defines the minimumfeasible capacitor size Moreover depending on the selectedcapacitor technology also the maximum allowed ripple currentimposes a restriction on the minimum feasible capacitancesize With decreasing size of the installed DC-link capacitancethe amplitude of the 120 Hz voltage ripple and thus the powerand voltage rating of the SVI converter increases In this workthe DC-link capacitance is chosen large enough such that theSVI converter only processes up to maximal 150 W and canbe implemented with LV technology In order to accomplisha cost-effective and reliable implementation of the [SVIC]buffer 450 V ultra-compact aluminum electrolytic capacitorsfrom TDK (B43630 series) in the range of 390 microF - 680 microF areconsidered in the design optimization for the implementationof the DC-link capacitance It would be in principle possibleto implement the DC-link capacitance with ceramic capacitortechnology however the prohibitively high cost and the largenumber of over 400 MLCC chips renders this design approachimpractical an unreliable Also the minimum available elec-trolytic capacitor 390 microF is reasonably close to the theoreticalminimum given by (18) for a maximum modulation index of09 of the inverter

For the implementation of the H-bridge 100 V7 mΩ E-Mode GaN transistors from EPC (EPC2001C) with unipolarPWM and a switching frequency in the range of 50 kHz -300 kHz are considered in the design optimization Similarto the design space of the PCI converter for the design ofthe HF filter inductor Lf various E-type core geometries withN87 MnZn ferrite material and available HF-litz wires areconsidered in the optimization For the implementation of thebuffer capacitor Cb both 100 V15 microF class IIX7S MLCC and200 V ultra-compact aluminum electrolytic capacitors (alsofrom TDKrsquos B43630 series) are considered For cost andassembly related restrictions as mentioned previously a buffercapacitance range of 200 microF - 1000 microF is considered in caseof the buffer capacitance implementation with MLCC Theeffective capacitance for the class IIX7S buffer capacitorsubject to a DC bias was obtained from the datasheet providedby the manufacturer [32] Furthermore the power loss due to

TABLE VSYSTEM PARAMETERS amp SEARCH LOCUS OF THE [SVIC] CONVERTER

PARETO OPTIMIZATION

Feature RangeOptionDC-link CapTechnology

450 V ultra-compact aluminum electrolytic(TDK B43630-Series)

Cdc [390 microF 680 microF]

Buffer Cap Technology

100 V X7Sclass II (TDKC5750X7S2A156M250KB)200 V ultra-compact aluminum electrolytic(TDK B43630-Series)

Cb[200 microF 1 mF] (MLCC)[390 microF 33 mF] (electrolytic cap)

Vb0 mb0 = [035 065] Vb0 = VCfmb0

Inductor Technology N87 ferrite E-core round and HF litz wireLf [1 microH 100 microH]Semiconductor 100 V7 mΩ GaN e-HEMT (EPC 2001C)fs [50 kHz 300 kHz] (PWM w const fs)Heat sink CSPI = 257 W

Kdm3

the LF voltage ripple was calculated based on the extrapolatedEquivalent Series Resistance (ESR) value of the class IIX7SMLCC specified at 1 kHz in the datasheet (minimum fre-quency with specified ESR value) In accordance with theavailable capacitance values of the 200 V B43630 series acapacitance in the range of 390 microF - 3300 microF is considered

020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )

Capacitance (microF)

80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)

Fig 10 (a) Capacitance density and (b) boxed volume as a function ofavailable capacitance of TDKrsquos B43630 and B41231 electrolytic capacitorseries




13

in the design space As shown in Fig 10 (a) capacitors withlower voltage rating typically feature higher capacitance pervolume However as can be seen from Fig 10 (b) for verylow capacitance values in the range of 390 microF - 1000 microF theeffective boxed volume of 80 V 100 V and 200 V electrolyticcapacitors are very similar Thus in order to limit the modelingeffort the same electrolytic capacitor technology (B43630ultra-compact series) is considered for the implementation ofthe DC-link (450 V model) and the buffer capacitor (200 Vmodel) As described in the previous section the bias voltageof the buffer capacitor is a further degree of freedom in theoptimization and is adjusted by means of varying the averagemodulation index of the SVI converter

mb0 =VCf

Vb0 (30)

in the range of 035 - 065 for a given size of the DC-linkcapacitor and resulting output voltage amplitude VCf Thedesign space variables are summarized in Tab V Giventhe described design space and elaborate loss and volumemodels of the utilized components a large number of possible[SVIC] designs was calculated Fig 11 (a) and (b) display the

10 15 20 25 30 35 40 45ρ - Power Density (kWdmsup3)

9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

390 μF 470 microF 560 microF 680 microFCdc

(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)

Design With Max Power Density

Al Electrolytic Buffer Cap

X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)

Fig 11 ηρ-plot of the calculated [SVIC] designs with indicated Paretofronts (a) Both DC-link and buffer capacitor are implemented with 450 Vand 200 V electrolytic capacitor technology respectively (b) The DC-linkis implemented with 450 V electrolytic capacitor technology and the buffercapacitor is implemented with 100 V class IIX7S MLCC technology

ηρ-performance of the designs with aluminum electrolytic andceramic buffer capacitor respectively Designs with differentDC-link capacitor size are distinguished by color

As can be seen in Fig 11 (a) using electrolytic capacitorsto implement the buffer capacitance a maximal power densityof about 35 kW

dm3 (574 Win3) at an efficiency of 9977 isachieved for design (S5) with the smallest considered DC-link capacitance of 390 microF As can be seen from Fig 11 (b)the power density can be further increased if the buffercapacitor is implemented with 100 VX7S ceramic capacitorsFor the smallest available DC-link capacitance a maximalpower density of almost 45 kW

dm3 (737 Win3) at a nominalefficiency of 9983 of design (S1) is possible according tothe optimization results

The volume and loss distribution of several selected Paretooptimal designs is shown in Fig 12 (a) and (b) respectivelyFrom the volume balance it can be clearly seen that the sizeof the DC-link capacitor is dominating the overall volumeComparing the two designs with maximal power density (S1)and (S5) using ceramic and electrolytic capacitor it can beseen that the higher power density of design (S1) is mainlyascribed to the more compact implementation of the bufferwith X7S MLCC As can be seen from Fig 12 (b) theelectrolytic buffer capacitor also exhibits higher power loss

The realized design indicated with label (H3) in Fig 11 (b)and described in detail in Section III-D achieves a powerdensity of 345 kW

dm3 (565 Win3) at an efficiency of 995

0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)

Buffer CapacitorDC-Link CapacitorPower SemiconductorInductor Additional

Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009

Fig 12 (a) Volume and (b) loss distribution of selected Pareto optimal[SVIC] designs




14

C Control System of the SVI converter

The control system proposed to regulate the SVI converteris depicted in Fig 13 The installed DC-link capacitor islarge enough to prevent severe overshoots and sags in theDC-link voltage during load transients For this reason thereis less demand on the dynamic performance of the controlsystem which allows to omit the feed-forward control ofthe fluctuating AC power and the cascaded DC-link voltagecontrol Referring to Fig 13 control subsystem (c) cancelsthe 120 Hz voltage ripple present in vdc The reference vlowastdcsimof the auxiliary converter output voltage control is obtainedby means of subtracting the average DC-link voltage vdc=from the measured value vdc In order to extract the averageDC-link voltage vdc= a moving-average low-pass filter withwindow size of one 120 Hz period is employed A purelyresonant compensator (proportional gain set to zero) tunedat 120 Hz is employed to regulate the output voltage vcf

to precisely track the reference vlowastdcsim and thus completelycancel the 120 Hz voltage ripple present in vdc Likewiseto the PCI converter controls presented in the Section II-Bcontrol subsystem (a) is employed to keep the mean value ofthe buffer capacitor voltage vb = Vb at a chosen referenceThe output of the PI controller current reference ilowastCb ismultiplied with the constant scaling factor minusVbnomISnom toobtain voltage reference vlowastcf This scaling factor relates thechargingdischarging power of the buffer capacitor vb middot ib tothe power which must be providedabsorbed at the output ofthe SVI converter asymp vcfIs According to the voltagecurrentdirections as shown in Fig 13 and the condition IS ge 0a positivenegative bias in vCf dischargescharges the buffercapacitor over time respectively During idle mode of theconverter when no real power is transferred to the AC side and

IS is essentially zero the buffer capacitor voltage cannot bekept at its desired bias voltage level For this reason it is crucialto include an anti-windup logic in the series compensatingvoltage PI controller The average filter capacitor bias voltagevCf is then regulated to meet the reference vlowastCf by means ofan inner-loop PI controller which outputs current referenceilowastCf= (cf Fig 13 (a)) Similar to the PCI converter controlsdescribed previously the control objectives are combined in asingle reference for the filter inductor current ilowastLf Note thatthe source current IS must flow entirely through Lf since itholds that iCf = 0 in steady-state For this reason ilowastLf= iscalculated based on the real power of the AC load and added tothe filter current reference (cf Fig 13 (b)) A satisfying initialset of control parameters for the PI and Resonant compensatorswas empirically determined with the aid of extensive circuitsimulations and then fine tuned during testing of the converterprototype (cf Section III-D)

D Hardware Implementation and Experimental Verification

Benefiting from the gained insights of the design optimiza-tion in Section III-B a prototype of the [SVIC] buffer asshown in Fig 14 was implemented in hardware The designparameters and selected features of the realized system aresummarized in Tab VI By the courtesy of TDK a custom560 microF450 V aluminum electrolytic capacitor with asymp 40 higher capacitance density but reduced lifetime compared toB43630 series (cf Section III-B) was available The buffercapacitor Cb was implemented with a total of 45 single15 microF100 V class IIX7S MLCC chips With a bias voltageof the buffer capacitor set to 55 V in the control system (cfSection III-C) the effective large-signal capacitance amountsto 260 microF

vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4



(b) Avg Power Feed-Forward

(c) Ripple Compensation

vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom

Fig 13 Proposed cascaded control structure of the SVI converter of the [SVIC] power buffer (a) Control of the average buffer capacitor voltage vb (b)Feed-forward control of the average AC power (real power) (c) Compensation of the DC-link voltage ripple (d) Inner loop control of filter inductor currentiLf with PWM




15

TABLE VITECHNICAL DETAILS OF THE REALIZED [SVIC] BUFFER

Feature Value DescriptionVolume (no cooling) 540 cm3 (21 in3) Boxed component volume of the [SVIC] buffer without heat sinkVolume (with cooling) 58 cm3 (35 in3) Total volume of the constructed [SVIC] buffer with a CSPI =

275 W

Kdm3 heat sink

Capacitor volume 429 cm3 (26 in3) Total volume of installed buffer capacitor and DC-link capacitorvolume (boxed)

η 9952 Efficiency at 2 kW

Lf 33 microH Coilcraft XAL1510-333MEDCf 60 microF 4times 15 microF 100 VX7S MLCCCb 260 microF Equivalent large signal capacitance of the installed 45times

15 microF100 VX7S MLCCCdc 560 microF Ultra-compact aluminum electrolytic capacitor technology (EPCOS

B43991-X0009-A224)

DC-Link Capacitor Cdc

Control Board Interface

EPC2033 GaNFull-Bridge

Lf

Cf

Buffer Capacitor Cb45 х 15microF100VX7S

Gate Signal amp VoltageIsolation

Fig 14 Picture of the implemented [SVIC] buffer The shown aluminumelectrolytic capacitor is buffering the DC-link and the buffer capacitor of theSVI converter is implemented with ceramic capacitors

Since the EPC2001C 7 mΩ100 V GaN transistors wereunavailable at the time of the prototype design the H-bridgewas implemented with EPC2033 7 mΩ150 V e-mode GaNtransistors from EPC which feature similar Rdson valuesbut higher output capacitance Coss The switching frequencyper bridge-leg is set to 70 kHz which in case of the em-ployed unipolar PWM corresponds to an effective switchingfrequency of 140 kHz and matches the switching frequencyof the 2nd version of the Little Box inverter operated withPWM (cf Fig 5 (b)) The gate-drive is implemented basedon the LM5113 half-bridge driver IC with bootstrap supply ofthe high-side transistors In addition power and gate-signalisolation is implemented with the ADuM500 and SI8620

ICs respectively The filter inductor Lf = 33 microH was im-plemented by means of an off-the-shelf available inductorfrom Coilcraftrsquos XAL1510 series (XAL1510-333MED 12 ARdc = 20 mΩ) The maximum current ripple amounts toapproximately 25 A peak-to-peak and occurs at the maximumof the output voltage vCf The control system proposed in theprevious section was also implemented on the TMS320F28335microcontroller from Texas Instruments which was located onan external control PCB (cf Fig 14 control board interface)All necessary analog measurement circuits to sense vdc vcf iLf and the buffer voltage vb are placed on the prototype PCBThe inner current feedback loop is executed with a frequencyof 140 kHz and the voltage feedback loops and feed-forwardcontrol are executed at 28 kHz

The efficiency according to (12) of the [SVIC] buffermeasured with a Yokogawa WT3000 precision power analyzeris depicted in blue in Fig 15 For comparison the efficiencycurves of the two variants of PCI converter presented inSection II-C are shown in grey At rated output power of2 kW the [SVIC] buffer exhibits an efficiency of 9952 As can be seen at high output power gt 17 kW the efficiencyof the PCI converter with class IIX6S capacitors is justslightly lower However as mentioned before one of the major

PCI V1[SVIC]

PCI V2

Fig 15 Measured efficiency of the constructed [SVIC] buffer prototypeas a function of apparent power Sb For reference the efficiency of the PCIconverter prototypes is shown in grey




16

iLf (2 Adiv)vCf (10 Vdiv)vb (20 Vdiv) vdc (10 Vdiv)

iinu (5 Adiv)iS (5 Adiv)vin (10 Vdiv) vdc (10 Vdiv AC)

360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)

Fig 16 Steady-state performance of the realized [SVIC] buffer at 2 kWrated power (a) Characteristic waveforms of the SVI converter (b) Elimina-tion of DC-link voltage ripple and resulting constant input voltage vin andsource current is

advantages of the [SVIC] approach is the excellent partial-load efficiency The measured peak efficiency amounts to998 at about 578 W output power Even at a very lowoutput power of around 200 W the efficiency of the bufferremains above 992 The achieved power density based onaggregated boxed component volume amounts to 345 kW

dm3

(565 Win3) Since the [SVIC] buffer prototype was designedto facilitate testing in the laboratory the components werenot arranged to fit tightly in a rectangular enclosure andusing the boxed volume of the entire prototype would leadto wrong conclusions regarding the achieved power density ofthe implemented [SVIC] buffer

The steady-state performance at 2 kW rated power of theproposed control system is illustrated by the experimentalmeasurements shown in Fig 16 It can be seen from therecorded converter input voltage (cf vin in Fig 16 (a)) thatthe 120 Hz voltage ripple in the DC-link voltage vdc is almostentirely compensated Note that the ripple of vdc with anamplitude of around 22 Vpp would violate the GLBC technicalspecification of 12 Vpp (3 of 400 V) Although the currentprovided to the inverter iinu exhibits the characteristic squaredsinusoidal shape with a peak current of 10 A for delivering

iLf (2 Adiv)vcf (10 Vdiv)vb (20 Vdiv) vin (20 Vdiv)


320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)

Fig 17 [SVIC] buffer transient response to (a) an abrupt load step from1000 W to 2000 W and (b) an abrupt load drop from 1250 W to 500 W

2 kW of real power to the inverter the current coming fromthe source iS is perfectly constant due to the operation of theSVI converter The characteristic waveforms of the auxiliaryconverter during stationary operation at rated power are shownin Fig 16 (b) As discussed in Section III-A because of thesource current bias of iLf and the small amplitude of therequired 120 Hz charging current such that vCf compensatesthe voltage ripple present in vdc the buffer capacitor voltagevb exhibits only a distinct 120 Hz voltage ripple and no 240 Hzcomponent In order to verify the dynamic performance ofthe implemented control system the main DCAC converterwas subject to load variations The corresponding transientperformance of the [SVIC] buffer for a load step from 1 kWto 2 kW is depicted in Fig 17 (a) Triggered by the loadstep the average SVI buffer capacitor voltage drops onlyroughly Rs = 10 V below the 55 V at steady-state and recoverswithin 20 ms The voltage controller immediately adapts vCf

to the increased amplitude of the DC-link voltage ripple whichfacilitates a very smooth transition of both the input voltage vin

and input current iS As already pointed out before becauseof the 10 Ω input resistor (cf Fig 1) the input voltage vin

decreases with increasing power and therefore settles at alower value after the transient As a consequence of theincrease in power being processed by the SVI converter the




17

amplitude of the characteristic 120 Hz voltage ripple acrossthe buffer capacitor becomes more pronounced immediatelyafter the load step Analogously a step down from 1250 W to500 W is depicted in Fig 17 (b) Triggered by the load dropthe input voltage and current attains the new steady-state valuesmoothly without any overshoot The output voltage vCf isimmediately adjusted by the control system and therefore noconsiderable voltage fluctuation is present in vin even duringthe transient which is approximately settled within 15 ms -20 ms This also clearly surpasses the required performanceof the GLBC technical specifications

IV DISCUSSION

Fig 18 summarizes and compares the Pareto optimizationresults of the PCI buffer presented in Section II-A and the[SVIC] buffer presented in Section III-B In general boththe PCI converter equipped with 450 V class IIX6S MLCCand the [SVIC] buffer equipped with 100 V class IIX7SMLCC and a 390 microF electrolytic DC-link capacitor can reachpower densities above 40 kW

dm3 (656 Win3) and high effi-ciencies above 994 at rated power Based on the Paretooptimization results it seems that the [SVIC] buffer ap-proach can potentially outperform the PCI converter both interms of power density and conversion efficiency Howeverin accordance with the experimental results presented in theprevious chapter this has not been demonstrated in hardwareso far The maximum power density of 413 kW

dm3 (677 Win3)was achieved with the PCI converter prototype equippedwith 450 V class IIX6S MLCC and operated with 140 kHzPWM Moreover the implemented [SVIC] buffer prototype(cf Fig 14) is a first proof-of-concept implementation primar-ily designed to facilitate experimental testing and verify theproposed control system described in Section III-C For thisreason the components have not been arranged to fit tightlyinto a cuboidal shape with minimum volume as it is the casefor the PCI converter prototypes (cf Fig 5) which are alreadyin a later refined stage of development As mentioned beforefor a fair comparison the sum of all boxed component volumeswas used to calculate the power density of the [SVIC] buffer

993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM

Electrolytic Buffer Cap

X7S MLCC Buffer CapX6S MLCC

amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)

Fig 18 Comparison of calculated ηρ-Pareto fronts of the PCI buffer and the[SVIC] buffer

prototype rather than the boxed rectangular volume of theentire system shown in Fig 14

It is worth noting that by employing aluminum electrolyticcapacitors to implement both the DC-link and the buffercapacitance the [SVIC] buffer can still potentially reachhigh power densities up to 35 kW

dm3 which outperforms the PCIconverter with TCM modulation and CeraLink capacitors Thisis particularly of interest regarding a cost-effective realizationof the active power buffer To exemplify the 2nd version of thepresented PCI converter uses 200 pieces of the 22 microF450 Vclass IIX6S MLCCs which amounts to $290 of componentcost for the buffer capacitor (order quantities above 1000pieces considered) In contrast a 390 microF450 V electrolyticcapacitor costs $4 and a 390 microF200 V electrolytic capacitorcosts just $2 Hence the capacitor component cost of theall-electrolytic [SVIC] buffer design (S5) amounts to onlyabout $6 Striving for maximum power density the buffercapacitor can be implemented with 35times 15 microF100 V X7SMLCC (S1) which amounts to $623 and therefore resultsin a total capacitor component cost of about $663 for the[SVIC] system From this point of view the [SVIC] bufferand in particular the all-electrolytic [SVIC] buffer is a verycost competitive approach and clearly outperforms the PCIconverter in this regard Although it was not considered in theoptimization of the PCI converter it is in principle also possi-ble to use aluminum electrolytic capacitors to implement Cb

and thus achieve a significantly lower cost However becauseof the imposed lifetime related ripple current limitations theminimum feasible buffer capacitor size results in a comparablylow capacitor utilization (small amplitude of the buffer voltageswing) and it is therefore unlikely that this approach wouldactually yield a ηρ-competitive design

As can be seen from the measured efficiencies of the imple-mented buffer prototypes (cf Fig 15) the [SVIC] approachfeatures the highest efficiency of 995 at rated output poweras opposed to the efficiency of 994 of the PCI converterwith class IIX6S MLCCs It is important to mention thatthe worst case power measurement accuracy of the employedYokogawa WT3000 power analyzer [33] amounts to plusmn8 Wwhich corresponds to an uncertainty of the measured efficiencyof up to plusmn04 This also suggests that the discrepancybetween the efficiency of the Pareto optimal design S1 andthe realized hardware H3 (cf Fig 18) is besides a suboptimalimplementation of the SVI converter and imperfections in theunderlying component models of the optimization attributedto uncertainty in the power measurements

Due to the nature of the partial-power approach the aux-iliary converter only processes a small share of the entirefluctuating power and thus exhibits a very low power losswhich explains the high efficiency In this regard one of theclear advantages of the [SVIC] buffer is its excellent partial-load efficiency At 500 W output power the efficiency of theimplemented [SVIC] system amounts to around 997 incontrast to the substantially lower efficiency of 98 of theimplemented PCI converter The high partial-load efficiencyis in particular beneficial to achieve a high CEC or Europeanweighted efficiency of the inverter equipped with active buffer

The presented experimental waveforms of the implemented




18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)

η - electrolytic cap (P1)

Vol - electrolytic cap (P1)

η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)

LBC ΔV limit current limit

inverter vdcmin limit

(A1)

(A2)

(A4)(A3)Vol - (S1)

Fig 19 Volume and efficiency comparison between conventional DC-linkwith electrolytic capacitors and optimally designed current or voltage injectionpower buffers with respect to the 25 ∆V limit specified in [1]

prototypes are clearly demonstrating that the proposed controlsystems in Section II-B and Section III-C both achieve excel-lent mitigation of the 120 Hz DC-link voltage ripple and alsoclearly meet the transient response requirements specified in[1] Because of the still comparably large size of the installedaluminum electrolytic capacitor in case of the [SVIC] bufferabrupt load changes are handled with much less demandon the dynamic performance of the control system becausethe DC-link capacitance provides enough passive buffering totemporarily accommodate the power mismatch between DCand AC side without pronounced sags or overshoots in theDC-link voltage On the contrary the small remaining DC-linkcapacitor of around 15 microF in case of the PCI converter conceptintended as commutation capacitor to reduce the parasitic in-ductance of the power loop requires active stabilization of theDC-link voltage which leads to a somewhat more complicatedcontrol system From this perspective it can be argued thatthe [SVIC] buffer in combination with the proposed controlsystem for the SVI is more robust and exhibits better transientperformance

It is also interesting to compare the performance of thepower buffers based on parallel current or series voltageinjection with a conventional passive DC-link comprised ofelectrolytic capacitors and to determine the voltage ripple ∆V

Vlimit when it actually becomes beneficial in terms of volumeto employ a converter based buffer concept and accept theincreased hardware effort A volume model was extracted bymeans of a least-square fit to the calculated boxed volumesof all possible DC-link assemblies generated with the ultra-compact 450 V electrolytic capacitors from TDK consideredin this work [34] allowing at maximum five capacitors tobe connected in parallel The resulting volume of the DC-link with respect to the voltage ripple limit is depicted inFig 19 Decreasing ∆V results in a larger volume sincemore electrolytic capacitors have to be installed to meet themore stringent requirement Likewise relaxing the voltageripple limit results in a volume reduction until the specified

ripple current limitation of the electrolytic capacitor preventsa further reduction in volume (A4) Given the calculated ESRfor each capacitor assembly obtained from the data providedin [34] [35] the power losses caused by the 120 Hz chargingcurrent is calculated and the resulting efficiency is depictedin Fig 19 The Pareto optimal design (P2) with TCM andclass IIX6S capacitors and the optimal design (P6) with TCMand CeraLink capacitors were chosen from the PCI converterdesigns for the volume benchmarks Typically the proposedcontrol system as proposed in Section II-B achieves completeripple cancellation but can be modified to tolerate a certain∆V across Cdc which slightly changes the rated power ofthe PCI converter design according to Sb = Sbminus∆Edcω Theperformance of the designs (P2) and (P6) were recalculatedfor several voltage ripple limits Likewise the Pareto optimal[SVIC] buffer design (S1) is also included in the benchmarkFor the 390 microF DC-link capacitor employed in (S1) thevoltage ripple at the input if the SVI converter compensationreference is set to zero amounts to ∆V = 34 V and explainswhy the trace stops at ∆V

V asymp 85 As indicated by inter-section (A2) between the total volume of design (P2) and theelectrolytic capacitor it becomes beneficial (only consideringvolume) to employ a PCI converter if a ∆VV = 6 or less isdemanded For the design (P6) with CeraLink the intersection(A1) occurs at ∆VV = 37 Considering the intersection(A3) between the total volume of the optimal [SVIC] bufferdesign (S1) and the electrolytic capacitor it becomes beneficialto employ an [SVIC] buffer (with ceramic buffer capacitor)if a ∆VV = 68 or less is demanded Also indicated inthe plot is the admissible 25 voltage ripple limit specifiedin [1] (cf Section I) which reveals that roughly 35 cm3 ofvolume were saved with the PCI converter (CeraLinkTCM)in the 1st version of the Google Little Box and about 65 cm3

of volume were saved with the PCI buffer (class IIX6S-PWM) in case of the 2nd implementation of the Little BoxConcerning efficiency Fig 19 shows that passive capacitiveDC-link buffering with electrolytic capacitors always achievesa higher efficiency compared to an optimal designed bufferemploying current or voltage injection stages regardless of thespecified voltage ripple limit

V CONCLUSION

In order to shrink the volume of the energy storage requiredin single-phase inverter systems to cope with the 120 Hzfluctuating AC power the power pulsation buffer conceptsselected by the 1st and 2nd prize winner of the GoogleLittle Box Challenge (GLBC) were analyzed in detail andcomparatively evaluated in this paper Based on Pareto op-timization results the full-power processing Parallel CurrentInjector (PCI approach of the 1st prize winner) can reachpower densities as high as 413 kW

dm3 (6771 Win3) mainlybecause of the small feasible buffer capacitance values The[SVIC] buffer (approach of the 2nd prize winner) employ-ing a partial-power Series Voltage Injector (SVI) converterequipped with 100 V class IIX7S ceramic capacitors can reachpower densities as high as 45 kW

dm3 (737 Win3) and mainlybenefits from the low heat sink volume due to its very high




19

efficiency Experimental results obtained from three prototypeimplementations of the considered concepts were presentedThe first version of the PCI converter employing CeraLinkcapacitors features an efficiency of 987 at rated power andan overall volume of 766 cm3 (47 in3) which correspondsto a power density of 261 kW

dm3 (428 Win3) The secondversion of the PCI converter employing 450 V class IIX6Scapacitors features an efficiency of 994 at rated power andan overall volume of 484 cm3 (30 in3) which corresponds toa power density of 413 kW

dm3 (6768 Win3) The implemented[SVIC] buffer prototype achieved an efficiency of 995 atrated power and an overall volume of 58 cm3 (35 in3) whichcorresponds to a power density of 345 kW

dm3 (565 Win3)Clearly one major advantage of the presented [SVIC] bufferis the remarkable partial-load efficiency with a measured peakvalue of 998 at asymp 580 W output power According tothe comparison with a conventional capacitive buffered DC-link using only electrolytic capacitors it becomes beneficialin term of volume to employ an optimized active powerbuffer if a ripple requirement of ∆VV = 6 minus 7 or lessis demanded by the application The outstanding performanceof the presented cascaded control structures for the PCI and[SVIC] buffer under stationary conditions (120 Hz voltageripple compensation) and subject to stepwise load changeswas demonstrated by means of experimental waveforms whichshowed that the technical requirements of the Google LittleBox Challenge (GLBC) were clearly met Because of thestill comparably large capacitance provided by the installedelectrolytic capacitor in case of the [SVIC] buffer approachabrupt load changes are handled with much less demandon the dynamic performance of the digital control systemWith respect to cost it is possible to implement an all-electrolytic [SVIC] buffer design with according to theconducted Pareto optimization still high power density ofasymp 35 kW

dm3 (574 Win3) but at a very low expense of only$ 6 of total capacitor cost as opposed to the $ 290 needed toimplement the class IIX6S buffer capacitor of the presentedPCI buffer approach

ACKNOWLEDGMENT

The authors are very much indebted to G Deboy fromInfineon Austria AG for his active support during the GoogleLittle Box Challenge and for providing a very generous quan-tity of Infineon CoolGaN transistors used in the PCI converterhardware prototypes The authors would also like to extendtheir gratitude to EPCOSTDK for providing custom CeraLinkand aluminum electrolytic capacitors used in the constructionof the PCI converter and the [SVIC] buffer prototypes

REFERENCES

[1] Goolge ldquoDetailed Inverter Specifications Testing Procedure andTechnical Approach and Testing Application Requirements for theLittle Box Challengerdquo Google Tech Rep 2015 [Online] Availablehttpswwwlittleboxchallengecom

[2] K A Kim Y Liu M Chen and H Chiu ldquoOpening the Box Survey ofHigh Power Density Inverter Techniques from the Little Box ChallengerdquoCPSS Trans on Power Electronics and Applications vol 2 no 2 pp131ndash139 2017

[3] W Ruxi F Wang D Boroyevich R Burgos L Rixin N Puqi andK Rajashekara ldquoA High Power Sensity Single-Phase PWM Rectifierwith Active Ripple Energy Storagerdquo IEEE Trans on Power Electronicsvol 26 no 5 pp 1430ndash1443 2011

[4] T Yi F Blaabjerg L Poh Chiang J Chi and W Peng ldquoDecouplingof Fluctuating Power in Single-Phase Systems Through a SymmetricalHalf-Bridge Circuitrdquo IEEE Trans on Power Electronics vol 30 no 4pp 1855ndash1865 2015

[5] A C Kyritsis N P Papanikolaou and E C Tatakis ldquoA Novel ParallelActive Filter for Current Pulsation Smoothing on Single Stage Grid-Connected AC-PV modulesrdquo in Proc of Eur Conf on Power ElectronAppl (EPE) 2007

[6] D Neumayr D Bortis and J W Kolar ldquoUltra-Compact Power PulsationBuffer for Single-Phase DCAC Converter Systemsrdquo in Proceedings ofthe 8th IEEE Intern Power Electronics and Motion Control Conference- (ECCE Asia IPEMC) 2016

[7] J Lin ldquoDecentralized Control of an Active Capacitor with NDO-BasedFeedforward Compensationrdquo IEEE Journal of Emerging and SelectedTopics in Power Electronics 2019 [Early Access]

[8] J Lin and G Weiss ldquoAn Indirect Approach to Control an ActiveCapacitorrdquo IEEE Journal of Emerging and Selected Topics in PowerElectronics 2019 [Early Access]

[9] G C Christidis A C Kyritsis N P Papanikolaou and E C TatakisldquoInvestigation of Parallel Active Filtersrsquo Limitations for Power Decou-pling on Single-StageSingle-Phase Microinvertersrdquo IEEE Journal ofEmerging and Selected Topics in Power Electronics vol 4 no 3 pp1096ndash1106 Sep 2016

[10] H Wang W Liu H Chung and F Blaabjerg ldquoStability Analysisand Dynamic Response of a DC-Link Module with a Series VoltageCompensatorrdquo in Proc of the IEEE Energy Conversion Congress andExposition (ECCE USA) 2013

[11] R Ghosh M Wang S Mudiyula U Mhaskar R Mitova D Reilly andD Klikic ldquoIndustrial Approach to Design a 2-kVA Inverter for GoogleLittle Box Challengerdquo IEEE Trans on Industrial Electronics vol 65no 7 pp 5539ndash5549 2018

[12] R Ghosh M Srikanth R Mitova M Wang and D Klikic ldquoNovelActive Ripple Filtering Schemes Used In Little Box Inverterrdquo in Procof the Int Exhibition and Conference for Power Electronics IntelligentMotion Renewable Energy and Energy Management (PCIM) May 2017

[13] Z Qin Y Tang P C Loh and F Blaabjerg ldquoBenchmark of AC andDC Active Power Decoupling Circuits for Second-Order Harmonic Mit-igation in kW-Scale Single-Phase Invertersrdquo IEEE Journal of Emergingand Selected Topics in Power Electronics vol 4 no 1 pp 15ndash25 2016

[14] S Qin Y Lei C Barth W Liu and R C N Pilawa-Podgurski ldquoAHigh Power Density Series-Stacked Energy Buffer for Power PulsationDecoupling in Single-Phase Convertersrdquo IEEE Trans on Power Elec-tronics vol 32 no 6 pp 4905ndash4924 June 2017

[15] L Hongbo Z Kai Z Hui F Shengfang and X Jian ldquoActive PowerDecoupling for High-Power Single-Phase PWM Rectifiersrdquo IEEE Transon Power Electronics vol 28 no 3 pp 1308ndash1319 2013

[16] H Hu S Harb N Kutkut I Batarseh and Z J Shen ldquoA Review ofPower Decoupling Techniques for Microinverters With Three DifferentDecoupling Capacitor Locations in PV Systemsrdquo Proc of the IEEETrans on Power Electronics vol 28 no 6 pp 2711ndash2726 June 2013

[17] Y Sun Y Liu M Su W Xiong and J Yang ldquoReview of Active PowerDecoupling Topologies in Single-Phase Systemsrdquo IEEE Trans on PowerElectronics vol 31 no 7 pp 4778ndash4794 July 2016

[18] H Haibing S Harb N Kutkut I Batarseh and Z J Shen ldquoAReview of Power Decoupling Techniques for Microinverters With ThreeDifferent Decoupling Capacitor Locations in PV Systemsrdquo IEEE Transon Power Electronics vol 28 no 6 pp 2711ndash2726 June 2013

[19] A S Morsy and P N Enjeti ldquoComparison of Active Power DecouplingMethods for High-Power-Density Single-Phase Inverters Using Wide-Bandgap FETs for Google Little Box Challengerdquo IEEE Journal ofEmerging and Selected Topics in Power Electronics vol 4 no 3 pp790ndash798 Sept 2016

[20] S Pervaiz A Kumar and K K Afridi ldquoA Compact Electrolytic-FreeTwo-Stage Universal Input Offline LED Driver With Volume-OptimizedSSC Energy Bufferrdquo IEEE Journal of Emerging and Selected Topics inPower Electronics vol 6 no 3 pp 1116ndash1130 Sep 2018

[21] S Xu R Shao L Chang and M Mao ldquoSingle-Phase DifferentialBuckndashBoost Inverter With Pulse Energy Modulation and Power Decou-pling Controlrdquo IEEE Journal of Emerging and Selected Topics in PowerElectronics vol 6 no 4 pp 2060ndash2072 Dec 2018

[22] S Bhowmick and L Umanand ldquoDesign and Analysis of the Low DeviceStress Active Power Decoupling for Single-Phase Grid Connection for aWide Range of Power Factorrdquo IEEE Journal of Emerging and SelectedTopics in Power Electronics vol 6 no 4 pp 1921ndash1931 Dec 2018




20

[23] mdashmdash ldquoA High-Performance Dynamic Controller for an Active PowerDecoupler with AC-Side Storage Elementrdquo IEEE Journal of Emergingand Selected Topics in Power Electronics vol 7 no 3 pp 2041ndash2056Sep 2019

[24] C P Henze H C Martin and D W Parsley ldquoZero-Voltage Switchingin High Frequency Power Converters using Pulse Width Modulationrdquoin Proc of the 3rd Annual IEEE Applied Power Electronics Conferenceand Exposition (APEC) 1998

[25] C B Barth I Moon Y Lei S Qin C N Robert and Pilawa-PodgurskildquoExperimental Evaluation of Capacitors for Power Buffering in Single-Phase Power Convertersrdquo in Proc of the IEEE Energy ConversionCongress and Exposition (ECCE) Sep 2015

[26] C B Barth T Foulkes I Moon Y Lei S Qin and R C NPilawa-Podgurski ldquoExperimental Evaluation of Capacitors for PowerBuffering in Single-Phase Power Convertersrdquo IEEE Transactions onPower Electronics vol 34 no 8 pp 7887ndash7899 Aug 2019

[27] D Neumayr D Bortis J W Kolar and J Konrad ldquoComprehensiveLarge-Signal Performance Analysis of Ceramic Capacitors for PowerPulsation Buffersrdquo in Proc of the 17th IEEE Workshop on Control andModel of Power Electron (COMPEL) 2016

[28] D Bortis D Neumayr and J W Kolar ldquoηρ -Pareto Optimization andComparative Evaluation of Inverter Concepts Considered for the GoogleLittle Box Challengerdquo in Proc of the 17th IEEE Workshop on ControlModel Power Electron (COMPEL) 2016

[29] D Neumayr D Bortis and J W Kolar ldquoEssence of the GOOGLE LittleBox Challenge - Part A Key Challenges and Solutionsrdquo CPSS Trans onPower Electronics and Applications 2020 [Accepted for Publication]

[30] R M Burkart H Uemura and J W Kolar ldquoOptimal Inductor Designfor 3-phase Voltage-Source PWM Converters Considering DifferentMagnetic Materials and a Wide Switching Frequency Rangerdquo in Procof the IEEE Int Power Electron Conf (ECCE ASIA IPEC) 2014

[31] D Zmood and D Holmes ldquoStationary Frame Current Regulation ofPWM Inverters with Zero Steady-State Errorrdquo IEEE Trans on Power

Electronics vol 18 no 3 pp 814ndash822 2003[32] TDK ldquoC5750 Series 15 microF 100 V X7S MLCCrdquo TDK Tech Rep

X7S Specs Sheet 2016 [Online] Available httpsproducttdkcomensearchcapacitorceramicmlccinfopart no=C5750X7S2A156M250KB

[33] Yokogawa ldquoWT3000 Precision Power Analyzer User ManualrdquoYokogawa Tech Rep 2014 [Online] Available httpscdntmiyokogawacomIM760301-01Epdf

[34] TDK ldquoAluminum Electrolytic Capacitors B43640rdquo TDK Tech RepNovember 2015

[35] mdashmdash ldquoAlCap Useful Life Calculation Tool - Web-BasedApplicationrdquo TDK Tech Rep 2017 [Online] Avail-able httpswwwtdk-electronicstdkcomen180482design-supportdesign-toolsalcap-useful-life-calculation-tool

Dominik Neumayr (Mrsquo18) received the MScand PhD degree in electrical engineering fromthe Swiss Federal Institute of Technology (ETH)Zurich Switzerland in 2015 and 2019 respectivelyBetween 2008 and 2010 he was with the Centerfor Advanced Power Systems (CAPS) at FloridaState University working on PowerControllerHardware-in-the-Loop simulations and controlsystems design for PEBB-based converter systemsfrom ABB Since spring 2015 he is with thePower Electronic Systems (PES) Laboratory ETH

Zurich His research focuses on the design implementation and controlof ultra-compact and high efficiency converter systems Mr Neumayr iscurrently also acting as technical advisor for rural electrification and off-gridsolar power at MPower Ventures

Gustavo Carlos Knabben (Srsquo17) received his BScdegree in Electrical Engineering from the State Uni-versity of Santa Catarina Brazil in 2015 and hisMSc degree in Electrical Engineering from the Fed-eral University of Santa Catarina Brazil in 2017specializing in solar photovoltaic energy conversionIn 2014 he was with SMA Solar Technology AGGermany working as an intern on medium-powerPV inverters He joined the Power Electronic Sys-tems Laboratory (PES) of ETH Zurich Switzerlandas a scientific assistant in 2017 where he is cur-

rently working toward his PhD degree with focus on ultra-compact DCDCconverters

Dominik Bortis (Mrsquo08) received the MSc and PhD degree in electrical engineering from the Swiss Fed-eral Institute of Technology (ETH) Zurich Switzer-land in 2005 and 2008 respectively In May 2005 he joined the Power Electronic Systems Laboratory (PES) ETH Zurich as a PhD student From 2008 to 2011 he has been a Postdoctoral Fellow and from 2011 to 2016 a Research Associate with PES co-supervising PhD students and leading industry research projects Since January 2016 Dr Bortis is heading the research group Advanced Mechatronic

Systems at PES which concentrates on ultra-high speed motors magneticbearings and bearingless drives new linear-rotary actuator and machineconcepts with integrated power electronics In this context multi-objectiveoptimizations concerning weightvolumeefficiencycosts the analysis of in-teractions of power electronics and electric machines and EMI are givenspecial attention Targeted applications include advanced industry automationand manufacturing eg highly dynamic and precise positioning systemsmedical and pharmaceutical systems eg ultra-high purity and blood pumpsand future mobility concepts including motors and actuators for hybrid andelectric vehicles more electric aircraft and satellites Dr Bortis has publishedmore than 90 scientific papers in international journals and conferenceproceedings He has filed 32 patents and has received 6 IEEE ConferencePrize Paper Awards

Johann W Kolar (Frsquo10) received his MSc andPhD degree (summa cum laudepromotio sub aus-piciis praesidentis rei publicae) from the Universityof Technology Vienna Austria in 1997 and 1999respectively Since 1984 he has been working asan independent researcher and international consul-tant in close collaboration with the University ofTechnology Vienna in the fields of power elec-tronics industrial electronics and high performancedrive systems He has proposed numerous novelPWM converter topologies modulation and control

concepts and has supervised 70+ PhD students He has published 880+scientific papers in international journals and conference proceedings 4 bookchapters and has filed 190+ patents The focus of his current research is onultra-compact and ultra-efficient SiC and GaN converter systems solid-statetransformers advanced variable speed three-phase motor drives integratedmodular motor drives ultra-high speed motors bearingless motors actuatorsand design automation in power electronicsmechatronics Dr Kolar hasreceived 31 IEEE Transactions and Conference Prize Paper Awards the2014 IEEE Middlebrook Award the 2016 IEEE William E Newell PowerElectronics Award the 2016 IEEE PEMC Council Award and two ETHZurich Golden Owl Awards for excellence in teaching He initiated andoris the founder of four ETH Spin-off companies He is a member of thesteering committees of several leading international conferences in the fieldand has served from 2001 through 2013 as an associate editor of the IEEETransactions on Power Electronics Since 2002 he also is an associate editor ofthe Journal of Power Electronics of the Korean Institute of Power Electronicsand a member of the Editorial Advisory Board of the IEEJ Transactions onElectrical and Electronic Engineering

Elise Varescon received the MSc degree in electri-cal engineering from the Swiss Federal Institute of Technology Lausanne (EPFL) Switzerland in 2016 with a focus on power electronics high voltage technology and electric power systems For her master thesis Elise was working on the optimal design and implementation of ultra-compact power buffer concepts at the Power Electronic Systems Laboratory of ETH Zurich She is currently working as Propulsion Control Software engineer at Bom-bardier Transportation Switzerland in Zurich




Comparative Evaluation of a Full- and Partial-PowerProcessing Active Power Buffer for Ultra-Compact

Single-Phase DCAC Converter SystemsDominik Neumayr Member IEEE Gustavo C Knabben Student Member IEEE Elise Varescon

Dominik Bortis Member IEEE and Johann W Kolar Fellow IEEEPower Electronic Systems Laboratory ETH Zurich Switzerland

Corresponding Author Dominik Neumayr ETL I12 Physikstrasse 3 8092 Zurich SwitzerlandE-Mail neumayrlemeeethzch Tel +41 44 633 83 58

AbstractmdashOne of the key technical challenges of the Googleamp IEEE Little Box competition an international contest to buildthe worldrsquos smallest 2 kW single-phase inverter in 2015 wasto shrink the volume of the energy storage required to copewith the twice mains-frequency (120Hz) pulsating power at theAC side and meet the stringent 25 input voltage ripple atthe DC side In this paper first a full-power processing buck-type converter active buffer approach selected by the 1st prizewinner of the Little Box Challenge (LBC) is analyzed in detailBeing relieved from strict voltage ripple requirements a largervoltage ripple is allowed across the buffer capacitor significantlyreducing the capacitance requirement Second a partial-poweractive buffer approach selected by the 2nd prize winner of theLBC where conventional passive capacitive buffering of the DC-link is combined with a series-connected auxiliary converter usedto compensate the remaining 120Hz voltage ripple across the DC-link capacitance is studied in detail In this paper both selectedconcepts are comparatively evaluated in terms of achievableefficiency power density and ripple compensation performanceunder both stationary and transient conditions Novel controlschemes and optimally designed hardware prototypes for bothconsidered buffer concepts are presented and accompanied withexperimental measurements to support the claimed efficiency andpower density and assess the performance of the implementedcontrol systems Finally by means of comparison with conven-tional passive DC-link buffering using only electrolytic capacitorsit is determined at what voltage ripple requirement it actuallybecomes beneficial in terms of volume to employ the consideredactive buffer concepts

Index TermsmdashPower Pulsation Buffer Active Power Decou-pling Series Voltage Injector Partial-Power Converter GoogleLittle Box Challenge

I INTRODUCTION

In order to achieve a cost reduction in solar power andpromote wide bandgap (WBG) power semiconductors for thenext generation of high efficiency and ultra-compact powerelectronics Google and IEEE launched the Little Box Chal-lenge (GLBC [1]) in 2015 aiming for a massive power densityenhancement of a 2 kW single-phase DCAC converter systemcompared to state-of-the-art technology advertising $1 millionprize money

One of the key technical challenges in the implementa-tion of the Google Little Box was to shrink the volume of

the energy storage required to cope with the twice mains-frequency (120 Hz) pulsating power at the AC side whilemeeting the stringent 25 (10 V pk-pk)1 input voltage rippleThe additional challenging technical requirements as listed inTab I and the attractive prize money created a remarkableinterest in the power electronics community which led to theparticipation of 2000+ teams ndash companies research institutesconsultants and universities ndash in the GLBC Finally 100+teams submitted technical descriptions of realized systemsOut of these applications 18 finalists [2] were selected topresent their technical approaches and hand over their proto-types to the National Renewable Energy Laboratory (NREL)Golden (Co) USA for final testing The team from theBelgian company CE+T Power was finally awarded the grandprize of $1 million for the most compact inverter passing alltests eg also the 100 hours testing achieving a power densityof 872 kW

dm3 (1429 Win3) and a CEC weighted efficiency of

1The specified 20 input current ripple limit (cf Tab I) is more stringentand for the stated Rs = 10 Ω input resistor implies a 25 (10 V pk-pk)limit for the maximal permissible 120 Hz input voltage ripple

TABLE IKEY INVERTER SPECIFICATIONS OF THE GOOGLE LITTLE BOX

CHALLENGE

Parameter Requirement

Input Voltage Source 450 Vdc with Rs = 10 Ω

Output Voltage amp Frequency 240 Vrms60 Hz

Maximum Apparent Output Power S 2 kVA

Power Factor 07 1 lead amp lagMaximum Load Steps 500 W

Power Density gt 3 kW

dm3 (gt 50 Win3)

CEC Efficiency ge95

Lifetime (Test Duration) gt 100 h

Max Outer Enclosure Temperature le 60 C

DC Input Voltage Ripple (120 Hz) le 25 (ie le 10 V pk-pk)DC Input Current Ripple (120 Hz) le 20 (ie le 1 A pk-pk)GroundLeakage Current le 50 mA (initially le 5 mA)Electromagnetic Compliance FCC Part 15BCISPR11 Class BAC Output VoltageCurrent THD lt5




2


dm3








t

Is

ib

i =Vdc

AC

DC

AC

DC

Cdc

pac

Vdc

t

vCf

Vs

RsRsis

+minus

+ minus

idc+

minus

ib

Vs

is

+minus

iac iac

+

minusvac

+

minusvac


+

minus

vdc

+

minus

Vin

t

Is

idc

vCf

i =Vdc

pac

pPPB = IS vaux

pFPB = Vdc ib

vdc

t

vdc=Vin

(a)

(c) (d)

(b)

RSiS

+

minusVS

450 V

10 Ω

+ +minus minus

Cb

Cdc

idc

iinuiinu

ib

iinuiinu

+

+

minus

minusvfb Lf

Cf

vCf

+

minus

Vin

Zl

iac

iLf

iCf

iCb

+

minus

vac

DC

AC

vbvdc

+

minusvb

Cb

Cdc

RS

ZlLf

iS

iLf

iac

+

minus+

minusVS

vac450 V

450 V 450 V

DC

AC

10 Ω

10 Ω 10 Ω

+

minus

Vin=Vdc

Vin=Vdc





3










Sb =radicP 2







(2 kW

300 V

)2

= 335 mW




4

Vol

tage

(V)

0

100

200

300

400

0

vb(t) Cbmin

vb(t) 2 ∙ Cbmin






vb middot Cbdvbdt



vb(t) =

radicV 2


ωCb (6)




dc

= 663 microF (7)



2


ωCbVb0 (8)





1000 200 300 4000

100

200

300

400

4681012141618202224

1000 200 300 4000

100

200

300

400

4681012141618202224

0 100 200 300 4000

100

200

300

400

0 100 200 300 4000

100

200

300

400

500

V C

eraL

ink


450

V

X6S

MLC

C

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vacpp (V)

Vacpp (V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vacpp (V)

Vacpp (V)



PARETO OPTIMIZATION

Feature RangeOption




[E0min E0max

]Em 5 - 30



PWM fs = 140 kHz


Kdm3



cm3








5


∆E =Sbω

= 531 J (9)




E0min = Em +∆E


∆E

2


Emax = 12CbV2dc














6


η - E

ffic

ienc

y (

)

985

9875

99

9925

995

9975

100


(P2)(P3)

(P4)

(P6)

(P1)

(H1)

(P5)


(a)

(b)

(c)

Loss

es (W

att)

0

5

10

15

20

25

30


InductorAdditional

Cooling

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

(P2) (P3) (P4) (P5) (P6)124

549

394

086

124

444

507 864 864

1679

34

487

158

264 242

304626

054

2664

10411291153

0881820

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

Vol

ume

(cm

3 )

0

20

40

60

80

(P2) (P3) (P4) (P5) (P6)

4771

1498

1728

697419429

1467

1728

1113419387

1995

2503

6612419482

2362

2503

691419440

60606415

346

1971

697419521

7068

5114

1536

(H2)














7


Vbmid = Vdcradic

2 = 2828 V (11)






Lf

Cb

vacVdc vb vT2

iac

vaciac

iLf

iLf

++

+ +vLf

vT2

divide

_

_ _

_

Db

Vb

vdc

vdcvdc

T2

T1

GT1

GT1

vb

_ + iCbVdc

+++ +_

__

Vbnom

Vdcnom

divide

divide

iac= iac=

pac

+_

pac~

pac=

Vbnom

Vb

VSRSVdcnom

Vdcnom

Vbnom

iLf

VS

iSiinuRS

iLf= iLf~ff

_

iLf~

DC

AC

PWMGT2

GT2

(c)(d)

R









8



Kdm3






Kdm3



22 microF450 V MLCC



(a)

(b)

HF Inductor - Lf



FPB

FPB









9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























2


dm3








t

Is

ib

i =Vdc

AC

DC

AC

DC

Cdc

pac

Vdc

t

vCf

Vs

RsRsis

+minus

+ minus

idc+

minus

ib

Vs

is

+minus

iac iac

+

minusvac

+

minusvac


+

minus

vdc

+

minus

Vin

t

Is

idc

vCf

i =Vdc

pac

pPPB = IS vaux

pFPB = Vdc ib

vdc

t

vdc=Vin

(a)

(c) (d)

(b)

RSiS

+

minusVS

450 V

10 Ω

+ +minus minus

Cb

Cdc

idc

iinuiinu

ib

iinuiinu

+

+

minus

minusvfb Lf

Cf

vCf

+

minus

Vin

Zl

iac

iLf

iCf

iCb

+

minus

vac

DC

AC

vbvdc

+

minusvb

Cb

Cdc

RS

ZlLf

iS

iLf

iac

+

minus+

minusVS

vac450 V

450 V 450 V

DC

AC

10 Ω

10 Ω 10 Ω

+

minus

Vin=Vdc

Vin=Vdc





3










Sb =radicP 2







(2 kW

300 V

)2

= 335 mW




4

Vol

tage

(V)

0

100

200

300

400

0

vb(t) Cbmin

vb(t) 2 ∙ Cbmin






vb middot Cbdvbdt



vb(t) =

radicV 2


ωCb (6)




dc

= 663 microF (7)



2


ωCbVb0 (8)





1000 200 300 4000

100

200

300

400

4681012141618202224

1000 200 300 4000

100

200

300

400

4681012141618202224

0 100 200 300 4000

100

200

300

400

0 100 200 300 4000

100

200

300

400

500

V C

eraL

ink


450

V

X6S

MLC

C

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vacpp (V)

Vacpp (V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vacpp (V)

Vacpp (V)



PARETO OPTIMIZATION

Feature RangeOption




[E0min E0max

]Em 5 - 30



PWM fs = 140 kHz


Kdm3



cm3








5


∆E =Sbω

= 531 J (9)




E0min = Em +∆E


∆E

2


Emax = 12CbV2dc














6


η - E

ffic

ienc

y (

)

985

9875

99

9925

995

9975

100


(P2)(P3)

(P4)

(P6)

(P1)

(H1)

(P5)


(a)

(b)

(c)

Loss

es (W

att)

0

5

10

15

20

25

30


InductorAdditional

Cooling

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

(P2) (P3) (P4) (P5) (P6)124

549

394

086

124

444

507 864 864

1679

34

487

158

264 242

304626

054

2664

10411291153

0881820

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

Vol

ume

(cm

3 )

0

20

40

60

80

(P2) (P3) (P4) (P5) (P6)

4771

1498

1728

697419429

1467

1728

1113419387

1995

2503

6612419482

2362

2503

691419440

60606415

346

1971

697419521

7068

5114

1536

(H2)














7


Vbmid = Vdcradic

2 = 2828 V (11)






Lf

Cb

vacVdc vb vT2

iac

vaciac

iLf

iLf

++

+ +vLf

vT2

divide

_

_ _

_

Db

Vb

vdc

vdcvdc

T2

T1

GT1

GT1

vb

_ + iCbVdc

+++ +_

__

Vbnom

Vdcnom

divide

divide

iac= iac=

pac

+_

pac~

pac=

Vbnom

Vb

VSRSVdcnom

Vdcnom

Vbnom

iLf

VS

iSiinuRS

iLf= iLf~ff

_

iLf~

DC

AC

PWMGT2

GT2

(c)(d)

R









8



Kdm3






Kdm3



22 microF450 V MLCC



(a)

(b)

HF Inductor - Lf



FPB

FPB









9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























3










Sb =radicP 2







(2 kW

300 V

)2

= 335 mW




4

Vol

tage

(V)

0

100

200

300

400

0

vb(t) Cbmin

vb(t) 2 ∙ Cbmin






vb middot Cbdvbdt



vb(t) =

radicV 2


ωCb (6)




dc

= 663 microF (7)



2


ωCbVb0 (8)





1000 200 300 4000

100

200

300

400

4681012141618202224

1000 200 300 4000

100

200

300

400

4681012141618202224

0 100 200 300 4000

100

200

300

400

0 100 200 300 4000

100

200

300

400

500

V C

eraL

ink


450

V

X6S

MLC

C

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vacpp (V)

Vacpp (V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vacpp (V)

Vacpp (V)



PARETO OPTIMIZATION

Feature RangeOption




[E0min E0max

]Em 5 - 30



PWM fs = 140 kHz


Kdm3



cm3








5


∆E =Sbω

= 531 J (9)




E0min = Em +∆E


∆E

2


Emax = 12CbV2dc














6


η - E

ffic

ienc

y (

)

985

9875

99

9925

995

9975

100


(P2)(P3)

(P4)

(P6)

(P1)

(H1)

(P5)


(a)

(b)

(c)

Loss

es (W

att)

0

5

10

15

20

25

30


InductorAdditional

Cooling

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

(P2) (P3) (P4) (P5) (P6)124

549

394

086

124

444

507 864 864

1679

34

487

158

264 242

304626

054

2664

10411291153

0881820

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

Vol

ume

(cm

3 )

0

20

40

60

80

(P2) (P3) (P4) (P5) (P6)

4771

1498

1728

697419429

1467

1728

1113419387

1995

2503

6612419482

2362

2503

691419440

60606415

346

1971

697419521

7068

5114

1536

(H2)














7


Vbmid = Vdcradic

2 = 2828 V (11)






Lf

Cb

vacVdc vb vT2

iac

vaciac

iLf

iLf

++

+ +vLf

vT2

divide

_

_ _

_

Db

Vb

vdc

vdcvdc

T2

T1

GT1

GT1

vb

_ + iCbVdc

+++ +_

__

Vbnom

Vdcnom

divide

divide

iac= iac=

pac

+_

pac~

pac=

Vbnom

Vb

VSRSVdcnom

Vdcnom

Vbnom

iLf

VS

iSiinuRS

iLf= iLf~ff

_

iLf~

DC

AC

PWMGT2

GT2

(c)(d)

R









8



Kdm3






Kdm3



22 microF450 V MLCC



(a)

(b)

HF Inductor - Lf



FPB

FPB









9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























4

Vol

tage

(V)

0

100

200

300

400

0

vb(t) Cbmin

vb(t) 2 ∙ Cbmin






vb middot Cbdvbdt



vb(t) =

radicV 2


ωCb (6)




dc

= 663 microF (7)



2


ωCbVb0 (8)





1000 200 300 4000

100

200

300

400

4681012141618202224

1000 200 300 4000

100

200

300

400

4681012141618202224

0 100 200 300 4000

100

200

300

400

0 100 200 300 4000

100

200

300

400

500

V C

eraL

ink


450

V

X6S

MLC

C

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vacpp (V)

Vacpp (V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vdc

(V)

Vacpp (V)

Vacpp (V)



PARETO OPTIMIZATION

Feature RangeOption




[E0min E0max

]Em 5 - 30



PWM fs = 140 kHz


Kdm3



cm3








5


∆E =Sbω

= 531 J (9)




E0min = Em +∆E


∆E

2


Emax = 12CbV2dc














6


η - E

ffic

ienc

y (

)

985

9875

99

9925

995

9975

100


(P2)(P3)

(P4)

(P6)

(P1)

(H1)

(P5)


(a)

(b)

(c)

Loss

es (W

att)

0

5

10

15

20

25

30


InductorAdditional

Cooling

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

(P2) (P3) (P4) (P5) (P6)124

549

394

086

124

444

507 864 864

1679

34

487

158

264 242

304626

054

2664

10411291153

0881820

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

Vol

ume

(cm

3 )

0

20

40

60

80

(P2) (P3) (P4) (P5) (P6)

4771

1498

1728

697419429

1467

1728

1113419387

1995

2503

6612419482

2362

2503

691419440

60606415

346

1971

697419521

7068

5114

1536

(H2)














7


Vbmid = Vdcradic

2 = 2828 V (11)






Lf

Cb

vacVdc vb vT2

iac

vaciac

iLf

iLf

++

+ +vLf

vT2

divide

_

_ _

_

Db

Vb

vdc

vdcvdc

T2

T1

GT1

GT1

vb

_ + iCbVdc

+++ +_

__

Vbnom

Vdcnom

divide

divide

iac= iac=

pac

+_

pac~

pac=

Vbnom

Vb

VSRSVdcnom

Vdcnom

Vbnom

iLf

VS

iSiinuRS

iLf= iLf~ff

_

iLf~

DC

AC

PWMGT2

GT2

(c)(d)

R









8



Kdm3






Kdm3



22 microF450 V MLCC



(a)

(b)

HF Inductor - Lf



FPB

FPB









9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























5


∆E =Sbω

= 531 J (9)




E0min = Em +∆E


∆E

2


Emax = 12CbV2dc














6


η - E

ffic

ienc

y (

)

985

9875

99

9925

995

9975

100


(P2)(P3)

(P4)

(P6)

(P1)

(H1)

(P5)


(a)

(b)

(c)

Loss

es (W

att)

0

5

10

15

20

25

30


InductorAdditional

Cooling

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

(P2) (P3) (P4) (P5) (P6)124

549

394

086

124

444

507 864 864

1679

34

487

158

264 242

304626

054

2664

10411291153

0881820

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

Vol

ume

(cm

3 )

0

20

40

60

80

(P2) (P3) (P4) (P5) (P6)

4771

1498

1728

697419429

1467

1728

1113419387

1995

2503

6612419482

2362

2503

691419440

60606415

346

1971

697419521

7068

5114

1536

(H2)














7


Vbmid = Vdcradic

2 = 2828 V (11)






Lf

Cb

vacVdc vb vT2

iac

vaciac

iLf

iLf

++

+ +vLf

vT2

divide

_

_ _

_

Db

Vb

vdc

vdcvdc

T2

T1

GT1

GT1

vb

_ + iCbVdc

+++ +_

__

Vbnom

Vdcnom

divide

divide

iac= iac=

pac

+_

pac~

pac=

Vbnom

Vb

VSRSVdcnom

Vdcnom

Vbnom

iLf

VS

iSiinuRS

iLf= iLf~ff

_

iLf~

DC

AC

PWMGT2

GT2

(c)(d)

R









8



Kdm3






Kdm3



22 microF450 V MLCC



(a)

(b)

HF Inductor - Lf



FPB

FPB









9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























6


η - E

ffic

ienc

y (

)

985

9875

99

9925

995

9975

100


(P2)(P3)

(P4)

(P6)

(P1)

(H1)

(P5)


(a)

(b)

(c)

Loss

es (W

att)

0

5

10

15

20

25

30


InductorAdditional

Cooling

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

(P2) (P3) (P4) (P5) (P6)124

549

394

086

124

444

507 864 864

1679

34

487

158

264 242

304626

054

2664

10411291153

0881820

TCM

X6S

PWM

X6S

TCM

Cer

aLin

k

PWM

Cer

aLin

k

TCM

Cer

aLin

k V

b =

300V

Vol

ume

(cm

3 )

0

20

40

60

80

(P2) (P3) (P4) (P5) (P6)

4771

1498

1728

697419429

1467

1728

1113419387

1995

2503

6612419482

2362

2503

691419440

60606415

346

1971

697419521

7068

5114

1536

(H2)














7


Vbmid = Vdcradic

2 = 2828 V (11)






Lf

Cb

vacVdc vb vT2

iac

vaciac

iLf

iLf

++

+ +vLf

vT2

divide

_

_ _

_

Db

Vb

vdc

vdcvdc

T2

T1

GT1

GT1

vb

_ + iCbVdc

+++ +_

__

Vbnom

Vdcnom

divide

divide

iac= iac=

pac

+_

pac~

pac=

Vbnom

Vb

VSRSVdcnom

Vdcnom

Vbnom

iLf

VS

iSiinuRS

iLf= iLf~ff

_

iLf~

DC

AC

PWMGT2

GT2

(c)(d)

R









8



Kdm3






Kdm3



22 microF450 V MLCC



(a)

(b)

HF Inductor - Lf



FPB

FPB









9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























7


Vbmid = Vdcradic

2 = 2828 V (11)






Lf

Cb

vacVdc vb vT2

iac

vaciac

iLf

iLf

++

+ +vLf

vT2

divide

_

_ _

_

Db

Vb

vdc

vdcvdc

T2

T1

GT1

GT1

vb

_ + iCbVdc

+++ +_

__

Vbnom

Vdcnom

divide

divide

iac= iac=

pac

+_

pac~

pac=

Vbnom

Vb

VSRSVdcnom

Vdcnom

Vbnom

iLf

VS

iSiinuRS

iLf= iLf~ff

_

iLf~

DC

AC

PWMGT2

GT2

(c)(d)

R









8



Kdm3






Kdm3



22 microF450 V MLCC



(a)

(b)

HF Inductor - Lf



FPB

FPB









9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























8



Kdm3






Kdm3



22 microF450 V MLCC



(a)

(b)

HF Inductor - Lf



FPB

FPB









9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























9






η = 1minus Pv

Sb(12)


dm3






Time (5 msdiv)








10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























10

Time (20 msdiv)(a)


50 V100 V

Time (20 msdiv)(b)


192 V316 V







vdc(t) =

radicV 2


ωCdc (13)



vdc =1

T

int T

0



Cdcmin ge maxt


ω(V 2



Cdcmin geSb

ωVdc0

radicV 2

dc0 minus V 2ac

(16)


mintvdc(t) ge Vac

minumax (17)


Cdcmin =Sb



(18)



minumax (19)



2


ωCdcVdc0 (20)




11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























11

5 10 15 20 25 30

-200

-400

200

0

400

5 10 15 20 25 30

-20

20

0 0

40

60

-2

21

-1

4

6

Volta

ge (V

)Vo

ltage

(V)

Time (ms)

Time (ms)

Mod

Ind

ex

(a)

(b)

(c)

vac

VS



mb

vbasymp

vCfvb (Cbmin)

vb (~2timesCbmin)

5 10 15 20 25 30

-6

-2

-4

0

2

-2

2

0

4

6

1

-1

Time (ms)

Cur

rent

(A)

Mod

Ind

ex





vCf(t) = minus1

2


ωCdcVdc0 (21)







dtasymp vCf (23)


Cbdvb


vbIS (24)


vb(t) =

radicV 2


2ω2CbCdcVdc0 (25)



Cbmin =ISSb

2ω2CdcV 2b0Vdc0

(26)


mintvb(t) ge Vcf

mbmax (27)





12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























12


Cbasymp =2m2

bmaxCdcVdc0ISSb

4m2bmaxω

2C2dcV

2dc0V

2b0 minus S2

b

= 1559 microF (28)



4








PARETO OPTIMIZATION







Vb0 mb0 = [035 065] Vb0 = VCfmb0


Kdm3


020406080

100120140160180

0 2000 4000 6000 8000 10000

Cap

acita

nce

Den

sity

(uF

cm3 )


80 V (B41231) 100 V (B41231) 200 V (B43630)

01020304050607080

0 2000 4000 6000 8000 10000

Vol

ume

(cm

3 )


(a)

(b)





13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























13


mb0 =VCf

Vb0 (30)



9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)

(b)


9965

997

9975

998

9985

999

9995

100

η - E

ffic

ienc

y (

)


(a)

(P1)

(S5)

(S1)(S2)

(S3)

(S3a)

(S4)

(S6)

(S7)

(S8)



X7S MLCC Buffer Cap

Realized Design

995 (H3)

(P1)









0

1

2

3

4

5

Loss

es (W

att)

(S1) (S4) (S5) (S8)

(S1) (S4) (S5) (S8)

0

20

40

60

80

Vol

ume

(cm

3 )

(a)

(b)


Cooling

28

040

054

3218

27

27138

459

3456

303459

303

138

044

133

034

025

066

083

092161

708

574584

449

456

236

359

2944

3218

1927

322725

18

092

040057038

159011

061

084

044

009





14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























14







vb vcfvfb

GT1

GT2

GT3

GT4

iLf Vdc

VS

iS

iinuRS

vac

iac

DC

AC

Cb Cf

Lf

vaciac

divide

Vdcnom

pacpac=

iLf

++

+vLfvfbdivide

_

Db

vb

GT1

vb

+ iCb

+

_

vCf

_ __

_

_

iLf

vdc~

PWM

GT2GT3GT4





vCfVb

vb vCf

vdc

+

+

_

_

iCf~

iLf=

iCf=

vdc=

R

Vbnom

ISnom





15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























15



275 W

Kdm3 heat sink





B43991-X0009-A224)




Lf

Cf







PCI V1[SVIC]

PCI V2





16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























16



360 V

340 V

Time (5 msdiv)

Time (5 msdiv)

(a)

(b)



dm3





320 V

300 V

Time (5 msdiv)

Time (5 msdiv)(a)

(b)









17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























17


IV DISCUSSION




993

994

995

996

997

998

999

1000

η - E

ffic

ienc

y (

)

(P2)(P3)

(H2)(H3)

(S5)

(S1)

CeraLink amp TCM

X6S MLCCamp PWM



amp TCM

Full-Power PCI

[SVIC] Buffer


Passive Buffering


(P1)

987 (H1)












18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























18

ΔV V ()100 5 15 20 25 30 35

Vol

ume

(cm

3 )

0

50

100

150

200

96

97

98

99

100

Effic

ienc

y (

)



η - (P2)

η - (S1)

Vol - (P2)

Vol - (P6)

η - (P6)



(A1)

(A2)

(A4)(A3)Vol - (S1)








V CONCLUSION







19






ACKNOWLEDGMENT


REFERENCES


























20



























19






ACKNOWLEDGMENT


REFERENCES


























20



























20

























Comparative Evaluation of a Full-and Partial-Power ...€¦ · Comparative Evaluation of a Full- and Partial-Power Processing Active Power Buffer for Ultra-Compact Single-Phase DC/AC

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