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Companion Website of the book DIGITAL ELECTRONICS: PRINCIPLES, DEVICES AND APPLICATIONS
Companion website of the book Digital Electronics: Principles, Devices and Applications
1
Application Relevant Information on DIGITAL INTEGRATED CIRCUITS
The companion website contains application relevant information on different categories of digital integrated circuits discussed in detail in the text. The information is presented under the following headings.
1. Numerical index of digital integrated circuits of TTL family 2. Functional index of digital integrated circuits of TTL family 3. Numerical index of digital integrated circuits of CMOS logic family 4. Functional index of digital integrated circuits of CMOS logic family 5. Numerical index of digital integrated circuits of ECL family 6. Functional index of digital integrated circuits of ECL family 7. Popular A/D converters 8. Popular D/A converters 9. Popular microprocessors 10. Popular microcontrollers 11. Pin connection diagrams and other relevant application information on logic
gates and related devices 12. Pin connection diagrams and other relevant application information on
multiplexers and de-multiplexers 13. Pin connection diagrams and other relevant application information on
digital ICs for arithmetic operations 14. Pin connection diagrams and other relevant application information on flip
flops and related devices 15. Pin connection diagrams and other relevant application information on
counters 16. Pin connection diagrams and other relevant application information on shift
registers 17. Pin connection diagrams and other relevant application information on
microprocessors and peripheral devices 18. Pin connection diagrams and other relevant application information on
microcontrollers
Companion website of the book Digital Electronics: Principles, Devices and Applications
2
1. Numerical index of digital integrated circuits of TTL family Table C.1 lists the numerical index of the digital integrated circuits belonging to the TTL family.
The devices covered include logic gates and related devices, arithmetic circuits, multiplexers, de-multiplexers, encoders and decoders, flip flops and counters and registers. (TTL family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book).
Table C.1 Numerical index of Digital Integrated Circuits
Type No. Function 7400 Quad 2-input NAND gate 7401 Quad 2-input NAND gate (open collector) 7402 Quad 2-input NOR gate 7403 Quad 2-input NAND gate (open collector) 7404 Hex Inverter 7405 Hex Inverter (open collector) 7408 Quad 2-input AND gate 7409 Quad 2-input AND gate (open collector) 7410 Triple 3-input NAND gate 74107 Dual JK Flip Flop with CLEAR 74109 Dual JK Positive Edge Triggered Flip Flop with PRESET
and CLEAR 7411 Triple 3-input AND gate 74112 Dual JK Negative Edge Triggered Flip Flop with PRESET
and CLEAR 74113 Dual JK Negative Edge Triggered Flip Flop with PRESET 74114 Dual JK Negative Edge Triggered Flip Flop with PRESET
74641 Octal tristate Non-inverting Bus Transceiver (Open collector)
74645 Octal tristate Non-inverting Bus Transceiver
7473 Dual JK Negative Edge Triggered Flip flop with CLEAR
7474 Dual D-type Positive Edge Triggered Flip Flop with PRESET and CLEAR
7475 4-Bit D-type Latch
7476 Dual JK flip flop with PRESET and CLEAR
7478 Dual JK flip flop with PRESET and CLEAR
7483 4-Bit Full Adder
7485 4-Bit Magnitude Comparator
7486 Quad 2-input EX-OR gate
74885 8-bit Magnitude Comparator
7490 Decade Counter
7491 8-bit Shift Register (Serial-in/Serial-out)
7493 4-bit Binary Counter
Companion website of the book Digital Electronics: Principles, Devices and Applications
6
2. Functional index of digital integrated circuits of TTL family Tables C.2 to C.6 list the functional indices of the digital integrated circuits of the TTL family for
logic gates and related devices, arithmetic circuits, multiplexers and de-multiplexers, flip flops, counters and registers respectively. (TTL family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book).
Companion website of the book Digital Electronics: Principles, Devices and Applications
12
3. Numerical index of digital integrated circuits of CMOS logic family Table C.7 lists the numerical index of the digital integrated circuits of the CMOS family. The
devices covered include logic gates and related devices, arithmetic circuits, multiplexers, de-multiplexers, encoders and decoders, flip flops and counters and registers. (CMOS family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book).
Table C.7
Numerical index of Digital Integrated Circuits of the CMOS logic family Type Number Function
4001B Quad 2-input NOR gate
4002B Dual 4-input NOR gate
4008 4-Bit Binary Full Adder
40097B Tristate Hex Non-inverting Buffer
40098B Tristate Inverting Buffer
4011B Quad 2-input NAND gate
4012B Dual 4-input NAND gate
4013 Dual D-type Flip Flop
4014 B 8-Bit Static Shift Register (Synchronous Parallel or Serial-in/Serial-out)
40147 10-line to 4-line BCD priority encoder
4015 B Dual 4-bit Static Shift Register (Serial-in/Parallel-out)
40160 B Decade Counter with Asynchronous Clear
40161 B Binary Counter with Asynchronous Clear
40162 B Decade Counter
40163 B Binary Counter
4017 B 5-stage Johnson Counter
40174 Hex D-type Flip Flop
40175 Quad D-type Flip Flop
40181 4-Bit Arithmetic Logic Unit
40182 Look Ahead Carry Generator
4019 Quad 2-input multiplexer
40192B Presettable BCD UP/DOWN Counter
40193 B Presettable Binary UP/DOWN Counter
4021 B 8-bit Static Shift Register (Asynchronous Parallel-in or Synchronous Serial-in/Serial-out)
4023B Triple3-input NAND gate
4025B Triple 3-input NOR gate
4027 Dual JK Flip Flop
4028 1-of-10 decoder
4029 B Synchronous Presettable 4-bit UP/DOWN Counter
Companion website of the book Digital Electronics: Principles, Devices and Applications
13
Table C.7 (Contd.)
Type Number Function 4030B Quad 2-input EX-OR gate 4035 B 4-bit Universal Shift Register 4042 Quad D-type Latch 4044 Quad R/S Latch with 3-state output 4047 Low Power Monostable/Astable Multivibrator 4049B Hex Inverting Buffer 4050B Hex Non-inverting Buffer 4069UB Hex Inverter 4070B Quad 2-input EX-OR gate 4071B Quad 2-input OR gate 4076 Quad D-type Flip Flop with 3-state output 4081B Quad 2-input AND gate 4086B 4-wide 2-input AND-OR-INVERT gate 4093B Quad 2-input Schmitt NAND 4510 B Presettable UP/DOWN BCD Counter 4511 BCD to 7-segment latch/decoder/driver 4511 BCD-to-7 segment Latch/Decoder/Driver 4512 8-input 3-state multiplexer 4514 1-of-16 decoder/demultiplexer with input latch 4515 1-of-16 decoder/demultiplexer with input latch 4518 B Dual 4-bit Decade Counter 4520B Dual 4-bit binary counter 4522 B 4-bit BCD Programmable divide-by-N counter 4527 BCD Rate Multiplier 4528 Dual Retriggerable Resettable Monostable Multivibrator 4532 8-line to 3-line priority encoder 4539 Dual 4-input multiplexer 4543 BCD to 7-segmnt latch/decoder/driver for LCD displays 4543 BCD-to-7 segment Latch/Decoder/Driver for LCD 4555 Dual 1-of-4 decoder/demultiplexers 4556 Dual 1-of-4 decoder/demultiplexers 4585 4-Bit Magnitude Comparator 4722 B Programmable Counter/Timer 4723 Dual 4-bit addressable latch 4723 Dual 4-bit Addressable Latch 4724 8-bit addressable latch 4724 8-bit Addressable Latch 4731 B Quad 64-bit Static Shift Register
Companion website of the book Digital Electronics: Principles, Devices and Applications
14
4. Functional index of digital integrated circuits of CMOS logic family Table C.8 to Table C.12 list the functional indices of the digital integrated circuits of the CMOS
family for Logic gates and related devices, arithmetic circuits, multiplexers and demultiplexers, Flip Flops and Counters and Registers respectively. (CMOS family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book)
Table C.8
Logic Gates belonging to CMOS family
Type Number Function 4001B Quad 2-input NOR gate
4002B Dual 4-input NOR gate
4011B Quad 2-input NAND gate
4012B Dual 4-input NAND gate
4023B Triple3-input NAND gate
4025B Triple 3-input NOR gate
4030B Quad 2-input EX-OR gate
4049B Hex Inverting Buffer
4050B Hex Non-inverting Buffer
40097B Tristate Hex Non-inverting Buffer
40098B Tristate Inverting Buffer
4069UB Hex Inverter
4070B Quad 2-input EX-OR gate
4071B Quad 2-input OR gate
4081B Quad 2-input AND gate
4086B 4-wide 2-input AND-OR-INVERT gate
4093B Quad 2-input Schmitt NAND
Companion website of the book Digital Electronics: Principles, Devices and Applications
15
Table C.9 Arithmetic circuits belonging to CMOS family
Type Number Function 4008 4-Bit Binary Full Adder
4527 BCD Rate Multiplier
4585 4-Bit Magnitude Comparator
40181 4-Bit Arithmetic Logic Unit
40182 Look Ahead Carry Generator
Companion website of the book Digital Electronics: Principles, Devices and Applications
16
Table C.10 Multiplexer and Demultiplexer Circuits belonging to CMOS family
Type Number Function 4019 Quad 2-input multiplexer
4028 1-of-10 decoder
40147 10-line to 4-line BCD priority encoder
4511 BCD to 7-segment latch/decoder/driver
4512 8-input 3-state multiplexer
4514 1-of-16 decoder/demultiplexer with input latch
4515 1-of-16 decoder/demultiplexer with input latch
4532 8-line to 3-line priority encoder
4539 Dual 4-input multiplexer
4543 BCD to 7-segmnt latch/decoder/driver for LCD displays
4555 Dual 1-of-4 decoder/demultiplexers
4556 Dual 1-of-4 decoder/demultiplexers
4723 Dual 4-bit addressable latch
4724 8-bit addressable latch
Companion website of the book Digital Electronics: Principles, Devices and Applications
4543 BCD-to-7 segment Latch/Decoder/Driver for LCD
4723 Dual 4-bit Addressable Latch
4724 8-bit Addressable Latch
Companion website of the book Digital Electronics: Principles, Devices and Applications
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Table C.12
Counters and Registers belonging to the CMOS family
Type Number Function
4014 B 8-Bit Static Shift Register (Synchronous Parallel or Serial-in/Serial-out)
4015 B Dual 4-bit Static Shift Register (Serial-in/Parallel-out)
4017 B 5-stage Johnson Counter
4021 B 8-bit Static Shift Register (Asynchronous Parallel-in or Synchronous Serial-in/Serial-out)
4029 B Synchronous Presettable 4-bit UP/DOWN Counter
4035 B 4-bit Universal Shift Register
40160 B Decade Counter with Asynchronous Clear
40161 B Binary Counter with Asynchronous Clear
40162 B Decade Counter
40163 B Binary Counter
40192B Presettable BCD UP/DOWN Counter
40193 B Presettable Binary UP/DOWN Counter
4510 B Presettable UP/DOWN BCD Counter
4518 B Dual 4-bit Decade Counter
4520B Dual 4-bit binary counter
4522 B 4-bit BCD Programmable divide-by-N counter
4722 B Programmable Counter/Timer
4731 B Quad 64-bit Static Shift Register
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5. Numerical index of digital integrated circuits of ECL family Table C.13 lists the numerical index of the digital integrated circuits of the ECL family. The
devices covered include logic gates and related devices, arithmetic circuits, multiplexers, de-multiplexers, encoders and decoders, flip flops and counters and registers. (ECL family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book).
Table C.13 Numerical Index of Digital Integrated circuits of ECL family
Type Number Function 10100 Quad 2-input NOR gate with strobe
10195 Hex Buffer with Invert/ Non-invert control 10198 Monostable multivibrator
10231 High Speed Dual D-type M/S Flip Flop
1658 Voltage Controlled Multivibrator
1666 Dual Clocked RS Flip Flop
1668 Dual Clocked Latch
1670 D-type Master/slave Flip Flop
Companion website of the book Digital Electronics: Principles, Devices and Applications
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6. Functional index of digital integrated circuits of ECL family Table C.14 to Table C.19 list the functional indices of the digital integrated circuits of the ECL
family for Logic gates and related devices, arithmetic circuits, multiplexers and demultiplexers, Flip Flops and Counters and Registers respectively. (ECL family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book).
Table C.14
Logic Gates belonging to ECL family
Type Number Function 10100 Quad 2-input NOR gate with strobe
UltraSparc II Sun Microsystems Second generation of UltraSparc processors
UltraSparcIIi Sun Microsystems Second generation of UltraSparc processors
UltraSparc III Sun Microsystems Third generation of UltraSparc processors
Companion website of the book Digital Electronics: Principles, Devices and Applications
38
10. Popular microcontrollers Table C.25-27 lists some of the popular 8-bit, 16-bit and 32-bit microcontroller type numbers along with their salient features. (Microcontrollers are discussed in detail in chapter-14 of the book).
Table C.25 8-bit microcontrollers
Type Number Manufacturer Salient features
80C51/87C51/80C31
Dallas Semiconductor and Other Manufacturers
MCS-51 architecture, CMOS technology
80C31FA/8XC51FA/FB/FC
Dallas Semiconductor and Other Manufacturers
Same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K ROM and 256 bytes RAM
80C31RA+/8XC51RA+/RB+/RC+
Dallas Semiconductor and Other manufacturers
The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K ROM and 512 bytes RAM
8XC51RD+
Dallas Semiconductor and Other manufacturers
The same as 80C51 except for the size of ROM and RAM, which is 64K ROM and 1024 bytes RAM
80C32/8XC52/54/58
Dallas Semiconductor and Other Manufacturers
The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K ROM and 256 bytes RAM
Freescale Semiconductor Eight-bit M68HC05 core, a clock speed of 4 MHz, 920 bytes of on-chip RAM, 32K of ROM
68HC11 Family
Freescale Semiconductor Fully static chip design using an eight-bit M68HC11 core, a clock speed of 5 MHz, 0/256/512/768/1024 bytes of on-chip RAM (in different variants), 0/12/20 kB of on-chip ROM or EPROM
PIC 16X84 Family
(Microchip Technology) High-performance RISC CPU, 14-bit wide instructions, eight-bit wide data path, 1024 14 EEPROM program memory, 64 bytes of on-chip data EEPROM
XC-800 Family
Infineon High performance microcontrollers
MCS-51 Intel 128 or 256 bytes of RAM up to 128 bytes of I/O, 512 bytes to 64kB ROM
Z8 Zilog 8-bit Harvard architecture ROM/EPROM/OTP microcontroller with on-chip SRAM
eZ8 (Encore Z8)
Zilog Improved version of Z8 with better pipelining feature and with on-chip flash memory and SRAM
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39
Table C.26 16-bit microcontrollers
Type
Number Manufacturer Salient features
68HC12 Family
Freescale Semiconductor High-performance 16-bit CPU core with 1024 bytes of RAM, 32K of flash EEPROM and 768 bytes of EEPROM
68HC16 Family
Freescale Semiconductor 16-bit enhancement of the eight-bit 68HC11 family with 8K of ROM, 4K of RAM
XC166 Family Infineon The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K ROM and 512 bytes RAM
PIC 24F Microchip Technology 16-128 kB of Flash memory, 4kB/8kB data RAM
PIC 24H Microchip Technology 12-256 kB of Flash memory, 1kB/8kB/16kB data RAM
MCS-96 family
Intel Commonly used in Embedded systems
MCS 296 family
Intel Improved version of MCS-96 family
Companion website of the book Digital Electronics: Principles, Devices and Applications
40
Table C.27 32-bit microcontrollers
Type Number Manufacturer Salient features
683XX Family
Freescale Semiconductors 10K of RAM, 256K of flash, a clock speed of 33 MHz, 48 I/O lines, a 16-bit timer, a 16-channel/10-bit A/D converter and four serial communication channels
MCORE Family
Freescale Semiconductors 32K of RAM, 256K of flash, 33 MHz of clock speed, two serial communication channels, 104 I/O lines, an eight-channel A/D converter and two timers
MPC500 Family
Freescale Semiconductors Configured around a 32-bit PowerPC core with 36K of RAM, 1024K of flash, a 66 MHz clock, three serial communication channels, 101 I/O lines, 40 channels of A/D conversion and 70 timer channels
MCFXXX Family
Freescale Semiconductors Configured around ColdFire Version 2 core with 64K RAM, 66 MHz clock, 5 serial communication channels, including an I2C bus and CAN support, 150 I/O lines and 4 timer channels
LPC3000 Family
Philips Semiconductors Based on Philips’ Nexperia platform, configured around an ARM926EJ core with the VFP9 floating-point coprocessor with 32K of instruction cache and 32K of data cache
TRICORETM Family
Infineon Unified, single-core 32-bit microcontroller– DSP architecture optimized for real-time embedded systems
Companion website of the book Digital Electronics: Principles, Devices and Applications
41
11. Pin connection diagrams and other relevant application information on
logic gates and related devices Figs.C.1 to C.31 give the pin connection diagram and other application relevant information of some of the popular logic gates and related devices. (Logic gates and other related devices are discussed in detail in chapter-4 of the book).
Fig.C.1
Fig.C.2
Fig.C.3
Quad 2-input NAND
1A
GND
1B
1Y
2A
2B
2Y
VCC
4B
4A
4Y
3B
3A
3Y
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y1110
Y=A.B = A+B
1 14
1 14
7400
1 14
7 8
Quad 2-input NOR
1Y
GND
1A
1B
2Y
2A
2B
VCC
4Y
4B
4A
3Y
3B
3A
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y1000
Y=A+B=A.B
7402
1 14
7 8
1 14
1 14
7400
Hex Inverter
1A
7404
1 14
GND
1Y
2A
2Y
3A
3Y
VCC6A
6Y
5A
5Y
4A
4Y7 8
nA = Data InputsnY = Data Output
A01
Y10
Y=A
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Fig.C.4
Fig.C.5
Fig.C.6
1 14
1 14
7400
Quad 2-Input AND
1A
7408
1 14
GND
1B
1Y
2A
2B
2Y
VCC4B
4A
4Y
3B
3A
3Y7 8
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y0001
Y=A.B
Triple 3-Input NAND
1A
7410
1 14
GND
1B
2A
2B
2C
2Y
VCC1C
1Y
3C
3B
3A
3Y7 8
nA, nB, nC = Data InputsnY = Data Output
A00001111
B00110011
C01010101
Y11111110
Y=A.B.C
Triple 3-Input AND
1A
7411
1 14
GND
1B
2A
2B
2C
2Y
VCC
1C
1Y
3C
3B
3A
3Y7 8
nA, nB, nC = Data InputsnY = Data Output
A00001111
B00110011
C01010101
Y00000001
Y=A.B.C
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43
Fig.C.7
Fig.C.8
Fig.C.9
Dual 4-Input NAND
1A
7420
1 14
GND
1B
NC
1C
1D
1Y
VCC
2D
2C
NC
2B
2A
2Y7 8
nA, nB, nC, nD = Data Inputs nY = Data Output
A0XXX1
B
0
1
X
XX
C
0
1
XX
X
Y11110
Y=A.B.C.D
D
01
XXX
Dual 4-Input AND
1A
7421
1 14
GND
1B
NC
1C
1D
1Y
VCC
2D
2C
NC
2B
2A
2Y7 8
nA, nB, nC, nD = Data InputsnY = Data Output
A0XXX1
B
0
1
X
XX
C
0
1
XX
X
Y00001
Y=A.B.C.D
D
01
XXX
Triple 3-Input NOR
1A
7427
1 14
GND
1B
2A
2B
2C
2Y
VCC1C
1Y
3C
3B
3A
3Y7 8
nA, nB, nC = Data InputsnY = Data Output
A00001111
B00110011
C01010101
Y10000000
Y=(A+B+C)
Companion website of the book Digital Electronics: Principles, Devices and Applications
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Fig.C.10
Fig.C.11
Fig.C.12
8-Input NAND
A
7430
1 14
GND
B
C
D
E
F
VCCNC
H
G
NC
NC
Y7 8
A through H = Data InputsY = Data Output
A0X
1
XXXXX
B
0
1
X
XXXXX
C
0
1
XX
XXXX
Y11111110
Y=(A.B.C.D.E.F.G.H )
D
0
1
XXX
XXX
E
0
1
XXXX
XX
F
X0
1
XXXX
X
G
X01
XXXXX
H
X1
XXXXXX
Quad 2-Input OR
1A
7432
1 14
GND
1B
1Y
2A
2B
2Y
VCC4B
4A
4Y
3B
3A
3Y7 8
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y0111
Y=A+B
Quad 2-Input NOR
1A
7436
1 14
GND
1B
1Y
2A
2B
2Y
VCC
4B
4A
4Y
3B
3A
3Y7 8
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y1000
Y=(A+B)
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Fig.C.13
Fig.C.14
Fig.C.15
Dual 4-Input NAND
1A
7440
1 14
GND
1B
NC
1C
1D
1Y
VCC
2D
2C
NC
2B
2A
2Y7 8
nA, nB, nC, nD = Data InputsnY = Data Output
A0XXX1
B
0
1
X
XX
C
0
1
XX
X
Y11110
D
01
XXX
Y=A.B.C.D
Quad Non-inverting tristate buffer
1OC
74125/74126
1 14
GND
1A
1Y
2OC
2A
2Y
VCC
4OC
4A
4Y
3OC
3A
3Y7 8
nA = Data InputsnY = Data OutputnOC = 3-state active control(Active LOW for 74125,Active HIGH for 74126)
OC001
A01X
Y01Z
OC110
A01X
Y01Z
74125 74126
Dual 4-Bit Buffer
1G
74240/74241/74244
1 20
GND
1A0
2Y3
1A1
VCC2G
10 11
nA0 through nA3 = Data InputsnY0 through nY3 = Data Outputs
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Fig.C.16
Fig.C.17
Fig.C.18
Quad 2-Input NOR
1A
4001
1 14
VSS
1B
1Y
2Y
2A
2B
VDD4B
4A
4Y
3Y
3B
3A7 8
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y1000
Y=A+B = A.B
Dual 4-Input NOR
1Y
4002
1 14
1A
1B
1C
1D
NC
VDD
2Y
2D
2C
2B
2A
NC7 8
nA, nB, nC, nD = Data InputsnY = Data Output
A01XXX
B0
1X
XX
C0
1
XX
X
Y10000
D0
1
XXX
Y=A+B+C+DVSS
Quad 2-Input NAND
1A
4011
1 14
VSS
1B
1Y
2Y
2A
2B
VDD
4B
4A
4Y
3Y
3B
3A7 8
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y1110
Y=A.B
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Fig.C.19
Fig.C.20
Fig.C.21
Quad 2-Input EX-OR
A1
4030
1 14
VSS
B1
Y1
Y2
A2
B2
VDD
B4
A4
Y4
Y3
B3
A3 7 8
A , B = Data InputsY = Data Output
n nn
A0011
B0101
Y0110
Y=A B+
4049
1 16 NC
6Y6ANC5Y
5A4Y
8 9 4A
VDD
1Y1A2Y2A
3Y3A
VSS
nA = Data InputsnY = Data Output
A01
Y10
Y = A
Hex Inverting Buffer
4050
1 16 NC
6Y6ANC5Y
5A4Y
4A
VDD
1Y1A2Y2A
3Y3A
VSS 8 9
nA = Data InputsnY = Data Output
A01
Y01
Y=A
Hex Non-inverting Buffer
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Fig.C.22
Fig.C.23
Fig.C.24
Quad 2-input EX-OR
1A
4070
1 14
VSS
1B
1Y
2Y
2A
2B
VDD
4B
4A
4Y
3Y
3B
3A7 8
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y0110
Y=A B+
Quad 2-Input OR
1A
4071
1 14
VSS
1B
1Y
2Y
2A
2B
VDD
4B
4A
4Y
3Y
3B
3A 7 8
nA nBnY
, = Data Inputs = Data Outputs
A0011
B0101
Y0111
Y=A+B
Quad 2-Input AND
1A
4081
1 14
VSS
1B
1Y
2Y
2A
2B
VDD
4B
4A
4Y
3Y
3B
3A7 8
nA, nB = Data InputsnY = Data Output
A0011
B0101
Y0001
Y=A.B
Companion website of the book Digital Electronics: Principles, Devices and Applications
49
Fig.C.25
Fig.C.26
Fig.C.27
Quad 2-Input Schmitt NAND
1A
4093
1 14
VSS
1B
1Y
2Y
2A
2B
VDD
4B
4A
4Y
3Y
3B
3A 7 8
nA nBnY
, = Data Inputs = Data Output
A0011
B0101
Y1110
Y=A.B
10101
1 16 VCC24Y3Y4AB
3Y3A
8 9 4Y
VCC11Y2Y1A1Y
2Y2A
VEE
B100
nY101
nY = nA+B
Quad 2-Input OR/NOR
nAX01
nY010
nA = Independent Data InputnB = Common Data inputnY = OR (true) OutputnY = NOR (inverted) Output
10103
1 16 VCC24Y3Y4B4A
3B3A
4Y
VCC11Y2Y1A1B
2A2B
VEE 8 9
nB0011
Y = (nA+nB)n = 1,2,3
Quad 2-Input OR Gate
nA0101
nY0111
4B0011
4A0101
4Y0111
4Y––
1000
4Y = (4A+4B)
nA, nB = Data Inputs1Y through 3Y= Data Outputs4Y, 4Y = Complementary Output (gate 4)
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50
Fig.C.28
Fig.C.29
Fig.C.30
Quad 2-input AND
10104
1 16
8 9
Vcc1
1Y2Y1A1B
2A2B
VEE
Vcc2
4Y3Y4B4A
3B3A
4Y
nA,nB = Data Inputs1Y through 3Y= Data outputs4Y, 4Y = Complementary Output (gate 4)
nB0011
nY = (nA.nB)n= 1,2,3
nA0101
nY0001
4B0011
4A0101
4Y0001
4Y––
1110
4Y = (4A.4B)
Quad 2-Input Ex-OR Gate
nA nBnY
, = Data Inputs = Data Outputs
Y=OE (A + B) —–
10113
1 16
8 9
VCC1
1Y2Y1A1B
2A2B
VEE
VCC2
4Y3Y4B4A
3B3A
OE
OE10000
BX0011
AX0101
Y00110
Triple Line Receiver(Differential Inputs and Outputs)
10114/10116
1 16
8 9
VCC1
Aout
Ain
BoutBout
VEE
VCC2
Cout
Cin
VBin
xin0011
xin0101
xout0011
xout0101
Aout
AinCout
Cin
Bin
Ain through Cin = Active-high data inputsAout through C = Active-low data outputsVBB = Input bias voltage
out
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51
Fig.C.31
Quad Line Receiver(Differential Inputs, single-ended Outputs)
10115
1 16
8 9
VCC1
Bout
Ain
BinBin
VEE
VCC2
Dout
Din
Cin
Aout
AinCout
Din
VBB
Ain through Din = Active-high data inputsAout through Dout = data outputsV = Input Bias voltage
xin0011
xin0101
xout0001
Cin
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52
12. Pin connection diagrams and other relevant application information on
multiplexers and de-multiplexers Figs.C.32 to C.48 give the pin connection diagram and other application relevant information of some of the popular multiplexer and demultiplexer devices. (Multiplexers and demultiplexers are discussed in detail in chapter-8 of the book).
Fig.C.32
Fig.C.33
0
1
5
4
Gnd
6
7
3
8
9
A
D
Vc c
B
C
2
7441
1 16
8 9
D C B A0000000011
0000111100
0011001100
0101010101
111111
001111
110011
010101
0 1 2 3 4 5 6 7 8 90111111111
1011111111
1101111111
1110111111
1111011111
1111101111
1111110111
1111111011
1111111101
1111111110
011111
101111
110111
111011
111101
111110
111111
111111
111111
111111
Over range
BCD-to-Decimal Decoder (Open Collector Outputs)
A through D: Data Inputs (A is LSB)0 through 9 : Decoded Outputs (Active LOW)
Vcc
A
B
C
D
9
8
7
7442
1 16
8 9
0
1
2
3
4
5
6
Gnd
D C B A0000000011
0000111100
0011001100
0101010101
111111
001111
110011
010101
0 1 2 3 4 5 6 7 8 90111111111
1011111111
1101111111
1110111111
1111011111
1111101111
1111110111
1111111011
1111111101
1111111110
111111
111111
111111
111111
111111
111111
111111
111111
111111
111111
Invalid
A through D: Data Inputs (A is LSB)0 through 9 : Decoded Outputs (Active LOW)
BCD-to-Decimal decoder
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53
Fig.C.34
Fig.C.35
Vcc
A
B
C
D
9
8
7
7445
1 16
8 9
0
1
2
3
4
5
6
Gnd
D C B A
0000000011
0000111100
0011001100
0101010101
111111
001111
110011
010101
0 1 2 3 4 5 6 7 8 9
0111111111
1011111111
1101111111
1110111111
1111011111
1111101111
1111110111
1111111011
1111111101
1111111110
111111
111111
111111
111111
111111
111111
111111
111111
111111
111111
Invalid
A through D : Data Inputs (A is LSB)0 through 9 : Decoded Outputs (Active LOW)
BCD-to-Decimal decoder
D C B ALT RBI
1xxxxxxxxxxxxxxxx0x
0123456789101112131415
BlankRipple Blank
Lamp Test
Funtion
1111111111111111x10
0000000011111111x0x
0000111100001111x0x
0011001100110011x0x
0101010101010101x0x
1111111111111111001
BI/RBO
0100101000111011110
0000011000110111110
0010000000101111110
0100100101001001110
0101110101011101110
0111000100110001110
1100000100000001110
a b c d e f gVcc
f
g
a
b
c
d
e
7447
1 16
8 9
B
C
LT
BI/RBO
RBI
D
A
Gnd
A through D : Data Inputs (A is LSB)a through g : Decoded Outputs (Active LOW)LT : Lamp Test InputRBI : Ripple Blanking InputBI/RBO : Blanking Input/ Blanking Output
BCD-to-7 Segment Decoder(Active LOW Open Collector Outputs)
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54
Fig.C.36
Fig.C.37
1xxxxxxxxxxxxxxxx0x
0123456789101112131415
BlankRipple Blank
Lamp Test
Funtion
1111111111111111x10
0000000011111111x0x
0000111100001111x0x
0011001100110011x0x
0101010101010101x0x
1111111111111111001
1011010111000100001
1111100111001000001
1101111111010000001
1011011010110110001
1010001010100010001
1000111011001110001
0011111011111110001
Vcc
f
g
a
b
c
d
e
7448
1 16
8 9
B
C
LT
BI/RBO
RBI
D
A
Gnd
A through D : Data Inputs (A is LSB)a through g : Decoded Outputs (Active LOW)LT : Lamp Test InputRBI : Ripple Blanking InputBI/RBO : Blanking Input/ Blanking Output
BCD-to-7 Segment Decoder(Active LOW Open Collector Outputs)
D C B ALT RBI BI/RBO a b c d e f g
Vcc
Y0
Y1
Y2
Y3
Y4
Y5
Y6
74131
1 16
8 9
A
B
C
Clk
G2
G1
Y7
Gnd
XX--------X
X0111111111
1X000000000
XX00001111X
XX00110011X
XX01010101X
11011111110
11101111110
11110111110
11111011110
11111101110
11111110110
11111111010
11111111100
Clk G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
3 : 8 Line Decoder/Demultiplexer
A, B, C : Select InputsY0 through Y7 : Data OutputsClk : Clock InputG1, G2 : Output Enables
Companion website of the book Digital Electronics: Principles, Devices and Applications
1 through 9 : Decimal InputsA, B, C, D : BCD Priority Outputs
Vcc
D8
D9
D10
D11
D12
D13
D14
D15
A
B
C
D7
D6
D5
D4
D3
D2
D1
D0
S
W
D
Gnd
1 24
12 13
74150
X0000000011111111
D C B A S W
X0000111100001111
X0011001100110011
X0101010101010101
10000000000000000
1D0DDDDDDDDD
DDDDDD
123456789
101112131415
16 : 1 Multiplexer
D0 through D15 : Data InputsW : Data Output (Active LOW)A, B, C, D : Select InputsS : Strobe
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56
Fig.C.40
Fig.C.41
Vcc
D4
D5
D6
D7
S0
S1
S2
74151
1 16
8 9
D3
D2
D1
D0
Y
W
G
Gnd
100000000
X00001111
X00110011
X01010101
0D0D1D2D3D4D5D6D7
1D0D1D2D3D4D5D6D7
G S2 S1 S0 Y W
8 : 1 Multiplexer (With strobe input)
D0 through D7 : Data InputsY : Data Output (Active HIGH)W : Data Output (Active LOW)S2, S1, S0 : Select InputsG : Strobe Input
Vcc
S0
S1
S2
S3
G2
G1
15
14
13
12
11
0
1
2
3
4
5
6
7
8
9
10
Gnd
1 24
12 13
74154
S0 through S3 : Select Inputs0 through 15 : Data OutputsG1, G2 : Strobe Inputs
4 : 16 Line Decoder
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57
Fig.C.42
Fig.C.43
Fig.C.44
Vcc
f
g
a
b
c
d
e
74247/74248/74249
1 16
8 9
B
C
LT
BI/RBO
RBI
D
A
Gnd
BCD-to-Seven Segment Decoder
A through D : BCD Inputsa through g : Seven Segment outputsLT : Lamp Test inputRBI : Ripple Blanking InputBI/RBO : BlankingInput/Ripple blanking Output
74247 : Active LOW outputs, Open Collector Outputs Function Table same as that of 744774248 : Active HIGH outputs, Internal Pull-up resistors Function Table same as that of 744874249 : Active HIGH outputs, Open Collector outputs Function Table same as that of 7448
Vcc
D4
D5
D6
D7
S0
S1
S2
74251
1 16
8 9
D3
D2
D1
D0
Y
W
G
Gnd
8 : 1 Data Selector/Multiplexer
S0, S1, S2 : Select InputsD0 through D7 : Data inputsW : Inverted Data outputY : Non-inverted Data outputG : 3-state output control
Vcc
2G
S0
2C3
2C2
2C1
2C0
2Y
74253
1 16
8 9
1G
S1
1C3
1C2
1C1
1C0
1Y
Gnd
Dual 4 : 1 Data Selector/Multiplexer
S0, S1 : Select InputsnC0 through nC3 : Data inputsnY : Data outputnG : 3-state output control
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58
Fig.C.45
Fig.C.46
Fig.C.47
VDD
f
g
a
b
c
d
e
4511
1 16
8 9
B
C
LT
BL
LE/Strobe
D
A
Vss
BCD-to-7 Segment Latch Decoder Driver
A, B, C, D : BCD inputs'a' through 'g' : SevenSegment outputs LT : Lamp Test inputBL : Blanking inputLE : Latch Enable input
Vcc
0
D
3
2
1
9
A
40147
1 16
8 9
4
5
6
7
8
C
B
Vss
01XXXXXXXXX
001XXXXXXXX
0001XXXXXXX
00001XXXXXX
000001XXXXX
0000001XXXX
10000000011
10000111100
10011001100
10101010101
1 2 3 4 5 6 7 8 9 D C B A 00000001XXX
000000001XX
0000000001X
00000000001
0
Inputs Outputs
10-line to 4-line BCD priority encoder
Vcc
2Q
2Q
2D0
2D1
A1
0CE
1CE
10134
1 16
8 9
Dual Multiplexers
Vcc1
1Q
1Q
1D0
1D1
A0
Cc
VEE
LLLLH
LLHHX
LHXXX
LHLH
Qn
C A0 nD0 nD1LHLH
Qn
Qn+1
C=CE+Cc
A0, A1 : Input SelectnD0-nD1 : Data InputsnQ, nQ : Data OutputsnCE : Clock Enable
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nD0, nD1 : Data inputsnY : Data outputsSEL : Select input
Companion website of the book Digital Electronics: Principles, Devices and Applications
60
13. Pin connection diagrams and other relevant application information on
digital ICs for arithmetic operations Figs.C.49 to C.60 give the pin connection diagram and other application relevant information of some of the popular digital ICs for arithmetic operations. (Arithmetic circuits discussed in detail in chapter-7 of the book).
Fig.C.49
Fig.C.50
B4
S4
C4
C0
Gnd
B1
A1
S1
A4
S3
A3
B3
Vcc
S2
B2
A2
7483
1 16
8 9
A1 to A4 : Word A InputsB1 to B4 : Word B InputsC0 : Carry InputS1 to S4 : Sum Word OutputsC4 : Carry Output
Vcc
A3
B2
A2
A1
B1
A0
B0
B3
A<B
A=B
A>B
A>B
A=B
A<B
Gnd
7485TTLLSS
ALSAS
1 16
8 9
}} O
utpu
ts
Inpu
ts
A0 to A3 : Word A InputsB0 to B3 : Word B Inputs
Companion website of the book Digital Electronics: Principles, Devices and Applications
61
Fig.C.51
Vcc
A1
B1
A2
B2
A3
B3
G
Cn+4
P
A=B
F3
B0
A0
S3
S2
S1
S0
Cn
M
F0
F1
F2
Gnd
1 24
12 13
74181
00000
0
0
0111
11111
00001
1
1
1000
01111
00110
0
1
1001
10011
01010
1
0
1010
10101
S3 S2 S1 S0
SELECTION
AABA+B 1 (A+B)
B
A B
A+BABA BB
A+B0ABABA
+
+
A Minus 1AB Minus 1A B Minus 1
Minus 1A Plus (A+B)
AB plus(A+B)
A Minus B minus 1
A+BA Plus (A + B)
A plus BA B plus(A + B)A + B
A Plus A AB plus A
A B minus AA
M=1Logic
FunctionArithmetic
Fuction
M=0 Cn = 0
A0 through A3 : Word A inputB through B : Word B inputF through F : Output WordS through S : Function Select inputM : Mode Select inputCn : Carry inputA=B : Equality Output (Active HIGH)Cn + 4 : Carry OutputG : Carry Generate Output (Active LOW)P : Carry Propagate Output (Active LOW)
0 30 30 3
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63
Fig.C.53
Fig.C.54
Vcc
B3
A3
S3
A4
B4
S4
C4
S2
B2
A2
S1
A1
B1
C0
Gnd
1 16
8 9
74283
A1A30101010101010101
OUTPUT
B1B30011001100110011
A2A40000111100001111
B2B40000000011111111
S1S30110011001100110
S2S40001111011100001
C2C40000000100011111
S1S31001100110011001
S2S40111100010000111
C2C40000011101111111
C0=0C2=0
C0=1C2=1
INPUT
Vcc
PLE
P7
P6
P5
P4
P3
P2
P1
P0
(P<Q)OUT
(P>Q)OUT
L/A
(P<Q)IN
(P>Q)IN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Gnd
1 24
12 13
74885
For P = Q cases, (P > Q) output follows (P > Q)input and (P < Q) output follows (P < Q) inputAG : Arithmetically greater thanPLE : P Latch EnableL/A : Function select (HIGH for logic operations and LOW for Arithmetic operations
Comparison
LOGICALLOGICALLOGICAL
ARITHMETICARITHMETICARITHMETIC
HHHLLL
P > QP < QP = Q
P AG QQ AG PP = Q
XX
H ORLXX
H ORL
InputP<Q P>Q
LH
H ORLLH
H ORL
L/A Data InputsP0-P7, Q0-Q7
InputP>Q
XX
H ORLXX
H ORL
HL
H ORLHL
H ORL
Output P<Q
Function Table
Companion website of the book Digital Electronics: Principles, Devices and Applications
64
Fig.C.55
Fig.C.56
VDD
B3
Co
S3
S2
S1
S0
Ci
A3
B2
A2
B1
A1
B0
A0
Vss
1 16
8 9
4008
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
Ci B A Co S
A0 through A3 : Word A inputB0 through B3 : Word B inputS0 through S3 : Sum outputCi : Carry inputC0 : Carry output
VDD
A1
B1
A2
B2
A3
B3
G
Cn+4
P
A=B
F3
B0
A0
S3
S2
S1
S0
Cn
M
F0
F1
F2
Vss
1 24
12 13
40181
A0 through A3 : Word A input (Active LOW)B0 through B3 : Word B input (Active LOW) S0 through S3 : Function select inputsCn : Carry IN, Cn+4 :Ripple Carry OUT M : Mode controlG, P : Look ahead carry outputs F0 through F3 : Function outputs (Active LOW)
Companion website of the book Digital Electronics: Principles, Devices and Applications
65
Fig.C.57
Fig.C.58
Fig.C.59
VDD
P2
G2
Cn
Cn+x
Cn+y
G
Cn+z
G1
P1
G0
P0
G3
P3
P
Vss
1 16
8 9
40182
G0 through G3 : Active LOW Carry Generate inputsP0 through P3 : Active LOW Carry propagate inputsCn : Active HIGH Carry inputCn + x, Cn + y, Cn + z :Active HIGH carry outputsG : Active LOW group carry generate inputP : Active LOW group carry propagate input
VDD
A3
B3
(A > B) OUT
(A < B) OUT
B0
A0
B1
B2
A2
(A = B) OUT
(A > B) IN
(A < B) IN
(A = B) IN
A1
Vss
1 16
8 9
4585
A0 - A3: Word A inputsB0 - B3: Word B inputs
VCC
1S
2S
2Cout
2Cin
2A
2B
S1
2S
1S
1 Cout
1Cin
1A
1B
S0
VEE
1 16
8 9
10180
nA, nB : Data inputsn Cin : Carry inputnS, nS : Data outputs S0, S1 : Mode selects
Companion website of the book Digital Electronics: Principles, Devices and Applications
66
Fig.C.60
Vcc2
M
Cn
A0
B0
B1
A1
S1
A2
S2
S0
S3
1 24
12 13
10181
0000000011111111
S3 S2 S1 S0
0000111100001111
0011001100110011
0101010101010101
M=1
AA+BA+B
Logical '1'ABB
A BA+BA BA BB
A+BLogical '0'
A BABA
+
+
M = 0, Cn = 0
AA Plus A BA Plus ABA times 2
(A+B) Plus 0(A + B) plus (AB)
A Plus BA plus (A + B)(A+B) plus 0
A minus B minus 1(A + B) plus (AB)
A plus (A + B)minus 1
A B minus 1AB minus 1A minus 1
A0 through A3 : Word A inputsB0 through B3 : Word B inputsCn : Carry input F0 through F3 : Word F inputsGG : Group generate outputCn + 4 : Carry outputM : mode SelectS0 through S3 : Function Selects
Vcc1
F0
F1
GG
Cn+4
F3
F2
PG
B3
A3
B2
VEE
Companion website of the book Digital Electronics: Principles, Devices and Applications
67
14. Pin connection diagrams and other relevant application information on flip flops and related devices Figs.C.61 to C.84 give the pin connection diagram and other application relevant information of some of the popular flip flops and related devices. (Flip Flops and related devices are discussed in detail in chapter-10 of the book).
Monostable Multvibrator (Positive and Negative Edge Triggered)
–Q
74121
1 14 VCC
7 8
NC
A1
A2
B
Gnd
NC
NC
R/CEXTCEXTRINTNC
Q
A1, A2 : Negative going trigger inputB : Positive going trigger inputRINT : Connection to internal timing resistorCEXT : Connection for external timing capacitorR/CEXT : Connection for common point between external timing capacitor and resistor–Q, Q : Outputs
A10XX11¯¯0X
A2X0X1¯1¯X0
Q0000
–Q1111
74122
1 14 VCC
7 8
A2
B1
B2
Clr
Gnd
R/CEXT
NC
NC
Q–
CEXT
RINT
Q
A1 A1, A2 : Negative going trigger inputB : Positive going trigger inputRINT : Connection to internal timingresistorCEXT : Connection for external timingcapacitorR/CEXT : Connection for common pointbetween external timing capacitor and resistor–Q, Q: Outputs
Retriggerable Monostable Multivibrator(Positive an Negative Edge Trigger)
Companion website of the book Digital Electronics: Principles, Devices and Applications
69
Fig.C.67
Fig.C.68
Fig.C.69
74123
1 16
8 9
nA : Negative going trigger inputsnB : Positive going trigger inputsnCEXT : Connection for external timing capacitornR/CEXT : Connection for common point between resistor and capacitornQ, nQ : Outputs
1A Vcc1R/CEXT1CEXT
2Q
2Clr
2B
2A
1Q
1B
1Clr
1Q
2Q
2CEXT
2R/CEXTGnd
Dual Retriggerable Monostable Multivibrator(Positive and Negative Edge Triggered)
74174
1 16
8 9
nD : Data InputsnQ : Data OutputsClk : Clock (Positive Edge Trigger)Clr : Clear Input (Active LOW)
Clr Vcc6Q1Q
1D
2Q
Gnd
6-Bit D-Type Flip-Flop
2D
3D
3Q
6D
5D
5Q
4D
4Q
Clk
Dual Monostable Multivibrator(Non-Retriggerable)
74221
1 16
8 9
1A Vcc1B
1Clr
1Q—
2Q
2Cext
Gnd
nA : Negative going trigger inputnB : Positive going trigger inputnCext : Connection for external timing capacitornR/Cext : Connection for common point between external timing resistor and capacitornQ, nQ : Outputs
2R/Cext
1R/Cext
1Cext1Q
2Q—
2Clr
2B
2A
Companion website of the book Digital Electronics: Principles, Devices and Applications
70
Fig.C.70
Fig.C.71
Fig.C.72
4-Bit D-Type Flip-Flop(Complementary Outputs)
74175
1 16
8 9
Clr Vcc
4Q
3D
3Q
Clk
4D
4Q—
3Q
1Q
1Q—
1D
2D–2Q
2Q
Gnd
nD : Data InputsnQ, nQ : Data OutputsCLK : Clock (Positive Edge Trigger)CLR : Clear Input (Active LOW)
Dual 4-Bit Addressable D-Type Latch
74256
1 16
8 9
A0 Vcc
A1
1D
1Q0
Gnd
nD : Data InputsnQ0 through nQ3 :Data outputs (Active HIGH)A0, A1 : Data Output SelectsClr : Clear Control (Active LOW)EI : Latch Control (Active LOW)
Clr
EI
2D
2D3
2Q1
1Q1
1Q2
1Q3
2Q2
2Q0 Memory
Demultiplex
CLEAR
MODE
AddressableLatchoutput
8-bit D-Type Flip Flop
74273
1 20
10 11
Clr Vcc
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Gnd
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Clk
D0 through D7 : Data inputsQ0 through Q7 : Data outputsCLK : Clock input (Positive Edge)Clr : Clear Input (Active LOW)
Companion website of the book Digital Electronics: Principles, Devices and Applications
71
Fig.C.73
Fig.C.74
Fig.C.75
Octal D-Type Latch
74373
1 20
10 11
OE Vcc
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Gnd
Q7
D7
D6
Q6
Q5
D5
D4
Q4
G
D0 through D7 : Data inputsQ0 through Q7 : Data outputsG : Latch Enable (Active LOW)OE : 3-state output enable (Active LOW)
8-bit D-Type Flip Flop
74374
1 20
10 11
OE Vcc
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Gnd
Q7
D7
D6
Q6
Q5
D5
D4
Q4
Clk
D0 through D7 : Data inputsQ0 through Q7 : Data outputsClk : Clock input (Positive Edge)OE : 3-state output enable
8-bit D-Type Flip Flop
4013
1 20
10 11
Clr Vcc
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Gnd
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Clk
nS : SET inputnR : RESET inputnD : Data inputnCLK : ClocknQ, nQ : Data outputs—
R = S = 1 is invalid
Companion website of the book Digital Electronics: Principles, Devices and Applications
nR : R input (RESET)nS : S input (SET)nJ, nK : J, K inputsnQ, nQ : Data outputsC : Clock input
VEE
Dual J-K Flip Flop
1K
1J
1S
1R
1Q
1Q
VCC 2
2Q
2R
2S
2K
2J
CLK
Companion website of the book Digital Electronics: Principles, Devices and Applications
74
Fig.C.82
Fig.C.83
Fig.C.84
10168
1 16
8 9
nD : Data inputsnQ : Data outputsnG : Output EnableLE : Latch Enable
Quad D-Type Latch
VCC2
4Q
LE
3G
4D
3Q
4G
3D
VCC1
1Q
1D
2G
1G
2Q
2D
VEE
G1000
LEX011
DXX01
Q0
Q01
0
10176
1 16
8 9
nD : Data inputsnQ : Data outputsCLK : Clock input (Postive edge trigger)
Hex D-Type Flip Flop
VCC2VCC1
1Q
1D
2D
3D
VEE
CLK0-
QQD
0
2Q
3Q
6Q
6D
5D
4D
CLK
5Q
4Q
10186
1 16
8 9
nD : Data inputsnQ : Data outputsCLK : Clock input (Postive edge trigger)RST : RESET input
Hex D-Type Flip Flop
VCCRST
Q0
VEE
RST100
CLK
Q1
Q2
D0
D1
D2
Q5
Q4
Q3
D5
D4
D3
CLKX-0
Q0
DnQn
n
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75
15. Pin connection diagrams and other relevant application information on
counters Figs.C.85 to C.100 give the pin connection diagram and other application relevant information of some of the popular counter devices. (Counters are discussed in detail in chapter-11 of the book).
Fig.C.85
Fig.C.86
Input A
NC
QA
QD
Gnd
QB
QC
7490
1 16
8 9
Inputs B
R01
R02
NC
V
R91
R92
CC
Input A, B : InputsQA through QD : OutputsR01, R02 : Reset to '0' inputsR91, R92 : Reset to '9' inputs
1
1
X
X
0
0
X
1
1
X
0
X
X
0
0
X
1
X
0
X
0
X
0
1
0
X
0
X
0
0
1
R01
0
0
0
Count
Count
Count
Count
0
0
0
0
0
1
R02 R19 R92 QD QC QB QA
BCD Counter (Decade)
Input A
NC
QA
QD
Gnd
QB
QC
7493
1 16
8 9
Input B
R01
R02
NC
V
R91
R91
CC
Input A, B : InputsQA through QD : OutputsR01, R02 : Reset to '0' inputs
1
0
X
1
X
0
0
R01
0
Count
Count
0 0
R02 QD QC QB QA
4-Bit Binary Counter
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76
Fig.C.87
V
RCO
Q0
Q1
Q2
Q3
ENT
LOAD
CC
74160/74162
1 16
8 9
Clr
Clk
D0
D1
D2
D3
ENP
Gnd
D0 through D3 : PresetData InputsQ0 throughQ3 : DataOutputsRCO : Ripple Carry OutputClk : Clock Input(Positive Edge Triggered)LOAD : Preset Control(Synchronous, Active LOW)Clr : Clear Input(Asynchronous, Active LOW)for74160 and synchronous,Active LOW for 74162ENP : Count Enable ParallelENT : Count Enable Trickle
4-Bit Counter
X
X
X
X
0
1
1
1
1
1
X
1
0
0
X
1
X
0
1
0
X
1
X
1
1
1
0
1
Clk Clr ENP ENT LOAD Function
X
X
X
0
1
1
1
1
1
X
1
0
0
X
1
X
0
1
0
X
1
X
1
1
1
0
1
Clk Clr ENP ENT LOAD Function
Clear
Count/RCO
Count Disabled
Count/RCO
LOAD
COUNT
Clear
Count/RCO
Count Disabled
Count/RCO
LOAD
COUNT
74160
74162
Disabled
Disabled
Disabled
Disabled
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77
Fig.C.88
D0 through D3 : PresetData InputsQ0 throughQ3 : DataOutputsRCO : Ripple Carry OutputClk : Clock Input(Positive Edge Triggered)LOAD : Preset Control(Synchronous, Active LOW)Clr : Clear Input(Asynchronous, Active LOW)for74161 and synchronous,Active LOW for 74163ENP : Count Enable ParallelENT : Count Enable Trickle
4-Bit Binary Up-Counter
X
X
X
0
1
1
1
1
X
1
0
X
1
X
0
1
X
1
X
1
1
0
1
Clk Clr ENP ENT LOAD Function
Clear
Count/RCO Disabled
Count Disabled
LOAD
COUNT
V
RCO
Q0
Q1
Q2
Q3
ENT
LOAD
CC
74161/74163
1 16
8 9
Clr
Clk
D0
D1
D2
D3
ENP
Gnd
X
X
X
0
1
1
1
1
1
X
1
0
0
X
1
X
0
1
0
X
1
X
1
1
1
0
1
Clk Clr ENP ENT LOAD Function
Clear
Count/RCO Disabled
Count Disabled
Count/RCODisabled
LOAD
COUNT
74161
74162
Companion website of the book Digital Electronics: Principles, Devices and Applications
78
Fig.C.89
Fig.C.90
V
D0
CLK
RCO
Max/Min
LD
D2
D3
CC
74190/74191
1 16
8 9
D1
Q1
Q0
EN
U/D
Q2
Q3
Gnd
D0 through D3 : Parallel data inputsQ0 through Q3 : Count outputsCLK : Clock inputU/D : Count Up/Down control LD : Parallel Load ControlMax/Min : Max/Min count outputRCO : Ripple Clock Output74190 : BCD74191 : 4-Bit Binary
Up/Down Counter
1
1
0
1
LD EN U/D
0
0
X
1
0
1
X
X
CLK
X
X
Count UP
Count DOWN
Load
No Change
Function
Synchronous
V
D0
Clr
BRW
CRY
LD
D2
D3
CC
74192/74193
1 16
8 9
D1
Q1
Q0
CK DN
CK UP
Q2
Q3
Gnd
D0 through D3 : Parallel data inputsQ0 through Q3 : Count outputsCK UP : Up-Count clock inputCK DN : Down-Count clock inputLD : Parallel load controlClr : Clear inputCRY : Carry inputBRW : Borrow output74192 : BCD74193 : 4-Bit Binary
Up/Down Counter
CKUP CKDN
0
0
1
0
Clr
1
X
X
Count UP
Count Down
Clear
Load
Function
1
X
X
1
1
X
0
LD
Synchronous
Companion website of the book Digital Electronics: Principles, Devices and Applications
79
Fig.C.91
Fig.C.92
Fig.C.93
V
R02
R01
CKB
CKA
QA
QD
CC
74290
1 14
7 8
R91
NC
R92
QC
QB
NC
Gnd
CKA : Clock for section A,CKB : Clock for section B, C, D,QA through QD : OutputsR01, R02 : Reset-to-0 InputsR91, R92 : Reset-to-9 InputsCKA, CKB : Negative edgeTriggered
BCD Counter(Divide-by-2/Divide-by-5)
R01 R02
1
1
X
X
0
0
X
1
1
X
0
X
X
0
0
X
1
X
0
X
0
R91 R92
X
0
1
0
X
0
X
QD
0
0
1
0
0
0
Count
Count
Count
Count
QC
0
0
0
QB
0
0
1
QA
V
R02
R01
CKB
CKA
QA
QD
CC
74293
1 14
7 8
NC
NC
NC
QC
QB
NC
Gnd
CKA : Clock for section A,CKB : Clock for section B, C, DQA through QD : OutputsR01, R02 : Reset-to-0 InputsR91, R92 : Reset-to-9 InputsCKA, CKB : Negative edgeTriggered
R01 R02
1
0
X
1
X
0
QD
0
Count
Count
0
QC
0
QB
0
QA
V
RST
Clk
CI
CO
9
4
8
DD
4017
1 16
8 9
5
1
0
2
6
7
3
VSS
Decade Counter
Clk : Clock0 through 9 : Decimal outputsRST : ResetC : Clock InhibitCO : Carry Out
RST CE
1
0
0
X
0
1
Clk
X
Function
Reset to '0'
Count
Count
1000000000
0100000000
0010000000
0001000000
0000100000
0000010000
0000001000
0000000100
0000000010
0000000001
1111100000
0 1 2 3 4 5 6 7 8 9 CO
Count Sequence Table
Function Table
Companion website of the book Digital Electronics: Principles, Devices and Applications
80
Fig.C.94
Fig.C.95
V
Carry Out
Q1
Q2
Q3
CP
TE
LOAD
DD
40160/40161/40162/40163
1 16
8 9
Clear
Clock
P1
P2
P3
P4
PE
VSS
Synchronous Programmable4-Bit Counter
40160 : Decade with Asynchronous Clear40161 : Binary with Asynchronous Clear40162 : Decade with Synchronous Claear
V
J1
RESET
BORROW
CARRY
PRESET ENBALE
J3
J4
DD
40192/40193
1 16
8 9
J2
Q2
Q1
Clock DOWN
Clock UP
Q3
Q4
VSS
Presettable 4-Bit UP/DOWN Counter
40192 : BCD Counter40193 : Binary Counter
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81
Fig.C.96
Fig.C.97
Fig.C.98
VDD
Clk
Q3
P3
P2
Q2
U/D
RST
4510/4516
1 16
8 9
/Preset
Q4
P4
P1
CI
Q1
CO
VSS
Presettable UP/DOWN Counter
P1 through P4 : preset inputsQ1 through Q4 : outputsRST : Reset inputClk : Clock inputCI : Carry INCO : Carry OUTNOTE 4510 in a BCD-counter while4516 is a 4-bit binary counter
D0 through D3 : Preset data inputsQ0 through Q3 : Data outputsCin : Carry inputS0, S1 : Mode controlsClk : Clock inputC : Carry outputout
V 2
Q1
Q0
Clk
D0
D1
Cin
S0
CC
X
0
1
0
1
X
Cin S0
0
0
0
1
1
1
S1
0
1
1
0
0
1
Load
Count UP
Hold Count
Count DOWN
Hold Count
Stop Count
MODE
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82
Fig.C.99
Fig.C.100
10154
1 16
8 9
V 1CC
Q3
Q3
Q2
S3
S2
S1
VEE
4-Bit Binary Counter
S0 through S3 : SETinputsRST : RESET inputClk0 : Clock forsection 0Clk 1 : Clock for sections 1,2 and 3Q0 through Q3 : Active HIGH countoutputsQ0, Q3 : Active LOWoutputsRST = S = 1 is invalid
V 2CC
Q0
Q0
Q1
Clk1
S0
Clk2
RST
0
0
1
RST S
0
1
0
Clk
X
X
Count
1
0
Q
10178
1 16
8 9
V 1CC
Q3
Q3
Q2
S3
S2
S1
VEE
4-Bit Binary Counter
S0 through S3 : SETinputsRST : RESET inputClk0 : Clock forsection 0Clk 1 : Clock for sections 1,2 and 3Q0 through Q3 : Active HIGH countoutputsQ0, Q3 : Active LOWoutputs
V 2CC
Q0
Q0
Q1
Clk1
S0
Clk2
RST
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83
16. Pin connection diagrams and other relevant application information on
shift registers Figs.C.101 to C.105 give the pin connection diagram and other application relevant information of some of the popular shift register devices. (Shift Registers are discussed in detail in chapter-11 of the book).
Fig.C.101
Fig.C.102
V
Q4
Q6
QF
QE
Clr
Clk
CC
74164
1 14
7 8
SIA
SIB
QA
QB
QC
QD
Gnd
SIA, SIB :Serial InputsQA through Q4 : Data OutputsClk : Clock InputClr : Clear Input
0
1
1
1
Clr SIA SIB
X
1
0
X
X
1
0
X
Clk
X
QA
0
1
0
0
QB
0
QB
Q1
Q1
N
0
0
QC
0
QC
Q2
Q2
N
0
0
QD
0
QD
Q3
Q3
N
0
0
QE
0
QE
Q4
Q4
N
0
0
QF
0
QF
Q5
Q5
N
0
0
QG
0
Q
Q6
Q6
0
0
0
QH
0
QA
Q0
Q0
N
0
0
8-Bit SIPO Shift Register
V
S/L
Q7
D7
D6
D5
D4
CLR
CC
74166
1 16
8 9
SI
D0
D1
D2
D3
CKIN
Clk
Gnd
D0 through D7 : Parallel inputsSI : Serial inputCLK : ClockQ7 :Data Output S/L : Shift/Parallel-load ControlCKIN : Clock Inhibit
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84
Fig.C.103
Fig.C.104
Fig.C.105
V
D2
D3
Shift
Q3
Load
Q2
CC
74178
1 14
7 8
D1
D0
SI
Q0
Clk
Q1
GND
D0 through D3 : Parallel inputsSI : Serial inputQ0 through Q3 : Data OutputsLoad : Parallel Load ControlShift : Serial Shift ControlClk : Clock Input
4-Bit Universal Shift Register
0
0
1
1
Shift Load
0
1
X
X
Clk SI
X
X
1
0
Q1
D1
Q0
Q0
0
0
0
Q1 Q2Q0
Q0
D0
1
0
0 Q2
D2
Q1
Q1
0
0
0
Q3
Q3
D3
Q2
Q2
0
0
0
V
P6
P5
P4
Q6
S
Clk
P/S
DD
4021
1 16
8 9
P7
Q5
Q7
P3
P2
P1
P0
VSS
8-Bit Shift Register
P0 through P7 : ParallelData inputClk : ClockP/S : Parallel/Serial SelectQ5, Q6, Q7 : Data output
P/S
X 1
0
Clk Function
Parallel in
Shift right
V
Q0
Q1
Q2
Q3
Clock
S1
S0
DD
40194
1 16
8 9
RESET
Shift Right
D0
D1
D2
D3
Shift Left
VSS
4-Bit Bidirectional universal Shift Register
Parallel Outputs
Select Inputs
Parallel Data
Inputs
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85
17. Pin connection diagrams and other relevant application information on microprocessors and peripheral devices Figs.C.106 to C.126 give the pin connection diagram and other application relevant information of some of the popular microprocessors. (Microprocessors and peripheral devices are discussed in detail in chapter-13 of the book).
Companion website of the book Digital Electronics: Principles, Devices and Applications
99
Fig.C.126
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15161718
SAB8286A
1920A0
A1A2A3A4A5A6A7OE
GND
VccB0B1B2B3B4B5B6B7T
Octal Bus Transceiver
Companion website of the book Digital Electronics: Principles, Devices and Applications
100
18. Pin connection diagrams and other relevant application information on
microcontrollers Figs.C.127 to C.137 give the pin connection diagram and other application relevant information of some of the popular microcontrollers. (Microcontrollers are discussed in detail in chapter-14 of the book).