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D D Como,18-Oct-01 Silvia Tentindo Repond 1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration) 7th International Conference on Advanced Techniques and HEP - Como, 15-19 October 2001
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Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Page 1: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Como,18-Oct-01 Silvia Tentindo Repond 1

The Online Central Tracker of D0

Silvia Tentindo RepondFlorida State University at Fermilab

(for the D0 Collaboration)

7th International Conference on Advanced Techniques and HEP - Como, 15-19 October

2001

Page 2: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Como,18-Oct-01 Silvia Tentindo Repond 2

Motivation

New Physics !

New Technology : ( new Tev new D0 new trigger , CTT )

Research

Discovery

Page 3: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Contents

Overview ( Physics, Tev, D0 )

The New Central Tracker in the D0 Trigger ( CTT ) :

- description of the D0 Trigger components ( CTT components in detail )

- The subDetectors for CTT - The Hardware and the Algorithms of

CTT: L1CTT and L2CTT ( L2STT ) Conclusions

Page 4: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Discovery of Higgs at Tevatron is constrained by Luminosity:

MH < 107.7 GeV excluded (LEP)

For :Run IIa 2fb-1Run IIb 10 fb1 - >3 s.d. evidence for

MH < 180 Gev - >5 s.d. discovery for

MH < 120 Gev - exclude SM at 95% CL

up to 190 Gev if no Higgs signal

New Physics : Higgs ! etcNew Physics : Higgs ! etc

SM MSSM

8 fb-1

Page 5: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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The Fermilab Tevatron Collider

Main Injector(new)

Tevatron

DØCDF

Chicago

p source

Booster

TeV collider at Fermilab

Peak Luminosity 1032

cm-1s-1( 5X1032 cm-1s-1 ) Energy at CMS 2TevIntegrated Luminosity 2fb-1 ( 8[30?]fb-1 )Bunch crossing time 396 ns (132ns) Turn-on March 1, 2001First collisions April 3, 2001

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D0 Run II Detector

Page 7: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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ForwardPreshower

Silicon Tracker Fiber Tracker

Solenoid Central Preshower

D0 Central Tracker

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New D0 for Run II

Muon System Upgrades Enhanced Muon Trigger Excellent Run I Calorimeter EM and HAD Energy 2 Tesla Magnetic Field Momentum Scintillating Fiber Tracker Improved Tracking Silicon Microstrip Tracker Secondary Vertexing Preshower Detectors Enhanced EM Identification

L1 Central Track Trigger Selection of Stiff Tracks L2 Impact Parameter Trigger Identification of Long-

Lived Particles

Page 9: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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D0 Detector Performance

Tracking Efficiency - 95% for ||<3

Momentum resolution –dpT/pT

2=0.002 Vertex reconstruction

primary: =15-30m secondary: =35m (r-),

80m (r-z) Lepton ID acceptance

muons: pT>1.5 GeV/c, ||<2 electrons: pT>1 GeV/c, ||<2.5

Offline algorithms

Page 10: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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b Taggingb Tagging

HIGGS Physics

NewPHYSICS ! ….but …

~ 10 fb

???

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New Trigger ! ! !

Field Programmable Gate Arrays

Digital Signal Processors

Alpha Processors

FPGA

DSP

Alpha

Page 12: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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The hardware for the new Trigger

Inputs

VMEBus

DSPs

FPGAs

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Alpha Processor

CPU (+fan)

PCI Slots

Main Memory

VME Bus

MagicBus

L3 CacheMemory

DataSwitches

PCI-VMEBridge

PCI-Mbus PIO

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D0 CTT Performance

+ momentum resolution

+ impact parameter t tbar b bar

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Trigger Requirements for D0RunII

The D0 RunII trigger: Must be flexible Must be fast Must recognize interesting signatures Must select one of ~10**6 events Must have high efficiency and high

rejection Dead time must be reduced to

minimal

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Trigger Requirements for D0 RunII

The D0 RunII trigger: Is re-programmable Does parallel processing Uses fast devices Uses new algorithms that reliably

select interesting signatures These algorithms are sophisticated

and able of high rejection Pipelining reduces dead time to

minimal

FPGAs,DSPs,Alpha’s

FPGAs

FPGAs

Pipeline

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Run II Trigger System

L2FW:Combined objects (e, , j)

L2FW:Combined objects (e, , j)

L1FW: towers, tracks, correlations L1FW: towers, tracks, correlations

L1CAL

L2STT

Global L2 L2CFT

L2PS

L2Cal

L1CTT

L2Muon

L1Muon

L1FPD

Detector L1 Trigger L2 Trigger7 MHz 5-10 kHz

CAL

FPSCPS

CFT

SMT

Muon

FPD

1000 Hz

3 us 100us 100ms

L3

Page 18: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Silicon Microstrip Tracker SMT

Read-out: SVX-II chips 800.000 channels

Hit resol. 10um, secondary vertex resol. 35um (r,phi) ; 80um(r,z)

240 cm

6 Barrels 12 Disks“F” 4 Disks

“H”

Page 19: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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SMT Barrel

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Central Fiber Tracker

A

S

16.000 channels Read-out: SVX-II chips Fast enough for L1 2.6 m scintillation fibers,

VLPC readout + 10m waveguides

Mounted on 8 cylinders 20<r<50 cm

8 alternating axial and stereo doublets (2deg pitch)

Page 21: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Preshower Detectors

Central and forward 16.000 + 8.000 channels Extruded triangular

scintillator strips with embedded WLS fibers

Axial and ±20° stereo layers

Refines position and energy measurements of EM showers

Reduces electron trigger backgrounds by a factor of 5

Page 22: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Level 3 Global Tracker Real data, Run 2001

Track with 5 fiber tracker hits, 5 3D silicon hits

Relative alignmentof silicon and fiber trackersverified to 40 m level

Page 23: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Central Tracker Trigger :Hardware and Algorithms

L1CTT(L2CTT)L2STT

Page 24: Como,18-Oct-01Silvia Tentindo Repond1 The Online Central Tracker of D0 Silvia Tentindo Repond Florida State University at Fermilab (for the D0 Collaboration)

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Level 1 CTT

Axial CFT ( Central Fiber tracker ) and CPS ( central PreShower )

Triggers are integrated : CFT - uses FPGA electronics to perform tracking in 4 pt bins - tracks are then matched to clusters CFT stereo layers are not included CPS stereo layers are not included - not used in L1, processed for readout to L2CPS preprocessor

Special boards provide interface to the L2STT preprocessor by distributing the CFT tracks from the octant geometry of CFT to the sextant geometry of SMT

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Level 1 CTT (cont.)

L1 CFT/CPS sends 64 trigger terms to L1 framework, formed from :

- Number of clusters without tracks - Number of tracks as function of :

Charge Pt bin Association , or lack, with a – high or low – threshold

preshower cluster- Occupancy level of the detector- Total pt- Phi sector with highest pt

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AFE MIX DFE- BC- TMCOL-

CFT Ax.

CPS Ax.

L2STT L3

L2STT L3

L2STT L3L2STT L3

L2STT L3

L2STT L3

L1CFT /CPS Ax.L3

L2CFT L2PSL2CFT L2PSL2CFT L2PSL2CFT L2PS

L3L3L3L3L3L3L3L3 L1 T

40

4

75

5

CPS Stereo 20

CFT Stereo.75

L2FPS L3

L2FPS L3

L2FPS L3

L2FPS L3

L1FPSL316FPS

32

     

3

     

3

CTT Organization showing links to the L1 TM, L2 PreProcessors and L3

LVDS LINK

DAUGHTER CARDS Each filling corresponds to a

different flavor

TRANSITION CARDS Each color corresponds

to a different flavor

LVDS LINKFSC LINK

G LINK

LEGEND

Created by Manuel I. MartinMay. 6, 99

Review October 2001

Created by Manuel I. MartinMay. 6, 99

Review October 2001

L2PS L3

CTOC

CTOC

FPSS

CTOC

CTOC

CTOC

CTOC

CTOC

CTOC

CTQD

CTQDCTQD

CTQD

STSX

STSX

STSX

STSX

STSX

STSX

STOV

STOV

STOV

STOV

STOV

STOV

FPSS

FPSS

FPSS

CTTT

FPTT

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DFE DaughterBoard for L1CTT trigger

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L1CTT Tracking Algorithms

L1CTT Tracking Algorithms

Find tracks of particles down to Pt of 1.5 GeV

Tag categories (incl. CPS info): track, isolated track, electron, ...

Find tracks of particles down to Pt of 1.5 GeV

Tag categories (incl. CPS info): track, isolated track, electron, ...

Trigger response for Z ee with 4 min.bias

A track example

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L1CTT DFEA Firmware L1CTT DFEA Firmware

Finds CFT tracks from CFT doublet hits in 4 Pt bin each with 4 sub-bins; In the lowest bin there are ~8,000 track equations

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In each Pt bin, track equations are repre-sented as a two dimensional array 44 wide (phi) and 8 tall (±4 sub-bins).

L1CTT DFEA Firmware L1CTT DFEA Firmware

In the above array, 8 tracks are found, however, only six tracks are reported as follows:

Track A is reported.

Track B is reported, C is pushed on the stack.

Track D is reported

Track E is reported, G is pushed on the stack, F is Lost.

Track H is reported.

Track G is popped from the stack and reported. Stack is then cleared.

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

AB C

D

E F GH

+–+–+–+–

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L2 preprocessor CTT

as it is at present is L2CFT; will be substituted by L2STT:

receives tracks from L1 CFT - sorts and possibly truncates the tracks before

sending to Global Output to Global - tracks sorted by pt - tracks sorted by impact parameter

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L2 preprocessor STT L2STT uses custom built hardware, but enters standard

L2 system through the CFT preprocessor to provide a standard interface to Global

receives tracks from L1 CFT Receives hits from SMT Reconstructs clusters and clusters centroids from SMT hits Associates SMT clusters to CFT tracks ( clusters in roads) Fits associated clusters into STT tracks Calculates impact parameter Sends STT tracks to L2Global Sends SMT hits ( axial and stereo) to L3

- improves pt resolution - provides vertex information

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L2STT Hardware Design

CPU

1 2

spare

3

VBD

4 5 6 7

STC

8

STC

9

STC

10

STC

11

STC

12

STC

13

FRC

14

STC

15

STC

16

TFC

20

TFC

1918

STC

17 21

spare

spare

spare

terminator

spare

terminator

Sector 1 Sector 2

Since most high-pT

tracks stay in 30° SMT sector, 12

STT sectors are independe

nt

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L2STT DaughterBoards

L1CTT SMT

L2CTT

preprocess SMT datafind clusters

associate clusters with L1CTT tracks L3

STCFRC

TFC

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L2STT Card Flavors

fiber road card receive SCL fan out L1CTT data manage L3 buffers arbitrate VME bus

silicon trigger card preprocess SMT data associate hits with

CFT tracks

track fit card fit trajectory to hits

CPU initialization downloading monitoring resets

VBD

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TFCDaughter

Board

of

STT

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L2STT Hit Filtering Algorithm

CFT A layer

CFT H layer

SMT barrels

2-mm road

To optimize track-finding efficiency, track purity and execution time, look for hits in all four layers but allow hits in only three out of four layers

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L2STT Track Fit Card

Eight TI DSP processors, each receives 2 CFT hits and r- SMT clusters in road defined by CFT track C program on DSP selects clusters closest

to road center at each of 4 layers and performs a linearized track fit:

0)( rr

br

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Central Tracker (L2STT) Performance

Impact parameter resolution of 35 m includes beam spot size (30 m) SMT resolution (15 m)

STT introduces negligible uncertainty to resolution

Queuing simulation predicts average STT latency is 25 s with negligible dead-time

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Conclusions

The requirements for new Physics have been addressed

by providing a new Accelerator, a new D0

Detector, and a new Trigger System. The most advanced Technology once again has

offered and produced the right tools for the HEP Physicists of HEP Physicists of the newthe new generationgeneration to go one step further, in the path of discovery and knowledge.

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Back to Work ………..and D0

well ! ! !

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Appendix

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The new role of Software in the Trigger Hardware

“software trigger “(L3) uses sophisticated algorithms, almost

identical to the offline reconstruction software .

Programmable chips - FPGAs, DSPs and alpha preprocessors - ( L1 and

L2 ) use fast versions of such algorithms ( “online algorithms”)

on reduced sets of digital information from the detector.

3 us

100 us

100 ms

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L2STT SIMULATOR

L1CTT

SMT

L2CTT

preprocess SMT datafind clustersassociate clusters

with L1CTT tracksL3

Tsim_l2sttread SMT hits

calculate clustersread L1_CFT roads

use filter LUTcalculate clusters in road

send to TFC

L2stt_fittingread clusters in road

LUT to phys coordfit SMT & CFT to track

send to L2CTT

Tsim_L1sttread CFT tracks

order in ptorder in overlays

make LUTs

L2stt_utilcreate LUTs

clusters factoryhits in road factory

tracks factory

L2stt_analyzecreate Ntuples

for clusters, roads and

tracks

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L2STT SIMULATOR - Roads

X vs Y display of Clusters in Roads

t tbar + 2 min bias event

blue = CFT tracks hit green = SMT Cluster red = Cluster in Road

Title:cluster_plot.ps (Portrait A 4)Creator:HIGZ Version 1.23/09Preview:This EPS picture was not savedwith a preview included in it.Comment:This EPS picture will print to aPostScript printer, but not toother types of printers.

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L2STT Emulator -Test vectorsL1CTT SMT

preprocess SMT datafind clusters

associate clusters with L1CTT tracks

Cluster FPGA

--------- STC ---------

Filter FPGA

FRC

TFC

FRC Test vectors

STC Test Vectors

SMT Test vectors

Clusters test vectors

Roads&ClustersTest vectors