Communication Frameworks for HPC and Big Data

Communication Frameworks for HPC and Big Data

Dhabaleswar K. (DK) PandaThe Ohio State University

E-mail: [email protected]://www.cse.ohio-state.edu/~panda

Talk at HPC Advisory Council Spain Conference (2015)

by

http://www.cse.ohio-state.edu/~panda

High-End Computing (HEC): PetaFlop to ExaFlop

HPCAC Spain Conference (Sept '15) 2

100-200 PFlops in 2016-2018

1 EFlops in 2020-2024?

Trends for Commodity Computing Clusters in the Top 500 List (http://www.top500.org)

3HPCAC Spain Conference (Sept '15)

Nov-96

Nov-97

Nov-98

Nov-99

Nov-00

Nov-01

Nov-02

Nov-03

Nov-04

Nov-05

Nov-06

Nov-07

Nov-08

Nov-09

Nov-10

Nov-11

Nov-12

Nov-13

Nov-14

050

100150200250300350400450500

0102030405060708090100Percentage of Clusters

Number of Clusters

Timeline

Num

ber o

f Clu

ster

s

Perc

enta

ge o

f Clu

ster

s

87%

Drivers of Modern HPC Cluster Architectures

• Multi-core processors are ubiquitous• InfiniBand very popular in HPC clusters•

• Accelerators/Coprocessors becoming common in high-end systems• Pushing the envelope for Exascale computing

Accelerators / Coprocessors high compute density, high performance/watt

>1 TFlop DP on a chip

High Performance Interconnects - InfiniBand<1usec latency, >100Gbps Bandwidth

Tianhe – 2 Titan Stampede Tianhe – 1A

4

Multi-core Processors

HPCAC Spain Conference (Sept '15)

• 259 IB Clusters (51%) in the June 2015 Top500 list

(http://www.top500.org)• Installations in the Top 50 (24 systems):

Large-scale InfiniBand Installations

519,640 cores (Stampede) at TACC (8th) 76,032 cores (Tsubame 2.5) at Japan/GSIC (22nd)

185,344 cores (Pleiades) at NASA/Ames (11th) 194,616 cores (Cascade) at PNNL (25th)

72,800 cores Cray CS-Storm in US (13th) 76,032 cores (Makman-2) at Saudi Aramco (28th)

72,800 cores Cray CS-Storm in US (14th) 110,400 cores (Pangea) in France (29th)

265,440 cores SGI ICE at Tulip Trading Australia (15th) 37,120 cores (Lomonosov-2) at Russia/MSU (31st)

124,200 cores (Topaz) SGI ICE at ERDC DSRC in US (16th) 57,600 cores (SwiftLucy) in US (33rd)

72,000 cores (HPC2) in Italy (17th) 50,544 cores (Occigen) at France/GENCI-CINES (36th)

115,668 cores (Thunder) at AFRL/USA (19th) 76,896 cores (Salomon) SGI ICE in Czech Republic (40th)

147,456 cores (SuperMUC) in Germany (20th) 73,584 cores (Spirit) at AFRL/USA (42nd)

86,016 cores (SuperMUC Phase 2) in Germany (21st) and many more!


http://www.top500.org/

6

• Scientific Computing– Message Passing Interface (MPI), including MPI + OpenMP, is the

Dominant Programming Model – Many discussions towards Partitioned Global Address Space

(PGAS) • UPC, OpenSHMEM, CAF, etc.

– Hybrid Programming: MPI + PGAS (OpenSHMEM, UPC)

• Big Data/Enterprise/Commercial Computing– Focuses on large data and data analysis– Hadoop (HDFS, HBase, MapReduce) – Spark is emerging for in-memory computing– Memcached is also used for Web 2.0

Two Major Categories of Applications


Towards Exascale System (Today and Target)

Systems 2015Tianhe-2

2020-2024 DifferenceToday & Exascale

System peak 55 PFlop/s 1 EFlop/s ~20x

Power 18 MW(3 Gflops/W)

~20 MW(50 Gflops/W)

O(1)~15x

System memory 1.4 PB(1.024PB CPU + 0.384PB CoP)

32 – 64 PB ~50X

Node performance 3.43TF/s(0.4 CPU + 3 CoP)

1.2 or 15 TF O(1)

Node concurrency 24 core CPU + 171 cores CoP

O(1k) or O(10k) ~5x - ~50x

Total node interconnect BW 6.36 GB/s 200 – 400 GB/s ~40x -~60x

System size (nodes) 16,000 O(100,000) or O(1M) ~6x - ~60x

Total concurrency 3.12M12.48M threads (4 /core)

O(billion) for latency hiding

~100x

MTTI Few/day Many/day O(?)

Courtesy: Prof. Jack Dongarra



Parallel Programming Models Overview

P1 P2 P3

Shared Memory

P1 P2 P3

Memory Memory Memory

P1 P2 P3

Memory Memory Memory

Logical shared memory

Shared Memory Model

SHMEM, DSMDistributed Memory Model

MPI (Message Passing Interface)

Partitioned Global Address Space (PGAS)

Global Arrays, UPC, Chapel, X10, CAF, …

• Programming models provide abstract machine models• Models can be mapped on different types of systems

– e.g. Distributed Shared Memory (DSM), MPI within a node, etc.

9

Partitioned Global Address Space (PGAS) Models


• Key features- Simple shared memory abstractions - Light weight one-sided communication - Easier to express irregular communication

• Different approaches to PGAS

- Languages • Unified Parallel C (UPC)• Co-Array Fortran (CAF)• X10• Chapel

- Libraries• OpenSHMEM• Global Arrays

Hybrid (MPI+PGAS) Programming

• Application sub-kernels can be re-written in MPI/PGAS based on communication characteristics

• Benefits:– Best of Distributed Computing Model– Best of Shared Memory Computing Model

• Exascale Roadmap*: – “Hybrid Programming is a practical way to

program exascale systems”

* The International Exascale Software Roadmap, Dongarra, J., Beckman, P. et al., Volume 25, Number 1, 2011, International Journal of High Performance Computer Applications, ISSN 1094-3420

Kernel 1MPI

Kernel 2MPI

Kernel 3MPI

Kernel NMPI

HPC Application

Kernel 2PGAS

Kernel NPGAS


Designing Communication Libraries for Multi-Petaflop and Exaflop Systems: Challenges

Programming ModelsMPI, PGAS (UPC, Global Arrays, OpenSHMEM), CUDA, OpenMP,

OpenACC, Cilk, Hadoop (MapReduce), Spark (RDD, DAG), etc.

Application Kernels/Applications

Networking Technologies(InfiniBand, 40/100GigE,

Aries, and OmniPath)

Multi/Many-coreArchitectures

11

Accelerators(NVIDIA and MIC)

Middleware


Co-Design Opportunities

and Challenges

across Various Layers

PerformanceScalability

Fault-Resilience

Communication Library or Runtime for Programming ModelsPoint-to-point

Communication (two-sided and

one-sided

Collective Communication

Energy-Awareness

Synchronization and Locks

I/O andFile Systems

FaultTolerance

• Scalability for million to billion processors– Support for highly-efficient inter-node and intra-node communication (both two-sided

and one-sided)• Scalable Collective communication

– Offload– Non-blocking– Topology-aware

• Balancing intra-node and inter-node communication for next generation multi-core (128-1024 cores/node)– Multiple end-points per node

• Support for efficient multi-threading• Integrated Support for GPGPUs and Accelerators• Fault-tolerance/resiliency• QoS support for communication and I/O• Support for Hybrid MPI+PGAS programming (MPI + OpenMP, MPI + UPC,

MPI + OpenSHMEM, CAF, …)• Virtualization • Energy-Awareness

Broad Challenges in Designing Communication Libraries for (MPI+X) at Exascale


• Extreme Low Memory Footprint– Memory per core continues to decrease

• D-L-A Framework– Discover

• Overall network topology (fat-tree, 3D, …)• Network topology for processes for a given job• Node architecture• Health of network and node

– Learn• Impact on performance and scalability• Potential for failure

– Adapt• Internal protocols and algorithms• Process mapping• Fault-tolerance solutions

– Low overhead techniques while delivering performance, scalability and fault-tolerance

Additional Challenges for Designing Exascale Software Libraries


14

• High Performance open-source MPI Library for InfiniBand, 10-40Gig/iWARP, and RDMA over Converged Enhanced Ethernet (RoCE)– MVAPICH (MPI-1), MVAPICH2 (MPI-2.2 and MPI-3.0), Available since 2002

– MVAPICH2-X (MPI + PGAS), Available since 2011

– Support for GPGPUs (MVAPICH2-GDR) and MIC (MVAPICH2-MIC), Available since 2014

– Support for Virtualization (MVAPICH2-Virt), Available since 2015

– Support for Energy-Awareness (MVAPICH2-EA), Available since 2015

– Used by more than 2,450 organizations in 76 countries– More than 286,000 downloads from the OSU site directly

– Empowering many TOP500 clusters (June ‘15 ranking)• 8th ranked 519,640-core cluster (Stampede) at TACC

• 11th ranked 185,344-core cluster (Pleiades) at NASA

• 22nd ranked 76,032-core cluster (Tsubame 2.5) at Tokyo Institute of Technology and many others

– Available with software stacks of many vendors and Linux Distros (RedHat and SuSE)– http://mvapich.cse.ohio-state.edu

• Empowering Top500 systems for over a decade– System-X from Virginia Tech (3rd in Nov 2003, 2,200 processors, 12.25 TFlops) ->

– Stampede at TACC (8th in Jun’15, 519,640 cores, 5.168 Plops)

MVAPICH2 Software


http://mvapich.cse.ohio-state.edu/


MVAPICH2 Software Family

Requirements MVAPICH2 Library to use

MPI with IB, iWARP and RoCE MVAPICH2

Advanced MPI, OSU INAM, PGAS and MPI+PGAS with IB and RoCE

MVAPICH2-X

MPI with IB & GPU MVAPICH2-GDR

MPI with IB & MIC MVAPICH2-MIC

HPC Cloud with MPI & IB MVAPICH2-Virt

Energy-aware MPI with IB, iWARP and RoCE MVAPICH2-EA


and one-sided RMA)– Extremely minimal memory footprint

• Collective communication– Hardware-multicast-based– Offload and Non-blocking

• Integrated Support for GPGPUs• Integrated Support for Intel MICs• Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM,

MPI + UPC, CAF, …) • Virtualization• Energy-Awareness • InfiniBand Network Analysis and Monitoring (INAM)

Overview of A Few Challenges being Addressed by MVAPICH2 Project for Exascale



Latency & Bandwidth: MPI over IB with MVAPICH20 4 8 16 32 64 128

256

512 1K

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

2.00Small Message Latency

Message Size (bytes)

Late

ncy

(us)

1.261.19

1.051.15

TrueScale-QDR - 2.8 GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switchConnectX-3-FDR - 2.8 GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switch

ConnectIB-Dual FDR - 2.8 GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switchConnectX-4-EDR - 2.8 GHz Deca-core (IvyBridge) Intel PCI Gen3 Back-to-back

4 16 64256

1024 4K16K

64K256K 1M

0

2000

4000

6000

8000

10000

12000

14000Unidirectional Bandwidth

Band

wid

th (M

Byte

s/se

c)


12465

3387

6356

11497

0 1 2 4 8 16 32 64 128 256 512 1K0

0.10.20.30.40.50.60.70.80.9

1Latency

Intra-Socket Inter-Socket

Message Size (Bytes)

Late

ncy

(us)

MVAPICH2 Two-Sided Intra-Node Performance(Shared memory and Kernel-based Zero-copy Support (LiMIC and CMA))

18

Latest MVAPICH2 2.2a

Intel Ivy-bridge

0.18 us

0.45 us

1 4 16 64256 1K 4K

16K64K

256K 1M 4M0

2000400060008000

10000120001400016000

Bandwidth (Inter-socket)

inter-Socket-CMAinter-Socket-Shmeminter-Socket-LiMIC


Band

wid

th (M

B/s)

1 4 16 64256 1K 4K

16K64K

256K 1M 4M0

2000400060008000

10000120001400016000

Bandwidth (Intra-socket)

intra-Socket-CMAintra-Socket-Shmemintra-Socket-LiMIC


Band

wid

th (M

B/s)

14,250 MB/s 13,749 MB/s



Minimizing Memory Footprint further by DC Transport

Nod

e 0

P1P0

Node 1

P3

P2Node 3

P7

P6

Nod

e 2

P5P4

IBNetwork

• Constant connection cost (One QP for any peer)• Full Feature Set (RDMA, Atomics etc)• Separate objects for send (DC Initiator) and receive (DC

Target)– DC Target identified by “DCT Number”– Messages routed with (DCT Number, LID)– Requires same “DC Key” to enable communication

• Available with MVAPICH2-X 2.2a• DCT support available in Mellanox OFED

160 320 6200

0.20.40.60.8

11.2

NAMD - Apoa1: Large data setRC DC-Pool UD XRC

Number of Processes

Nor

mal

ized

Exec

ution

Ti

me

80 160 320 6400.499999999999999

4.99999999999999

49.9999999999999

499.999999999999

1022

4797

1 1 1

2

10 10 10 10

1 1

3 5

Memory Footprint for AlltoallRC DC-Pool UDXRC

Number of Processes

Conn

ectio

n M

emor

y (K

B)

H. Subramoni, K. Hamidouche, A. Venkatesh, S. Chakraborty and D. K. Panda, Designing MPI Library with Dynamic Connected Transport (DCT) of InfiniBand : Early Experiences. IEEE International Supercomputing Conference (ISC ’14).


and one-sided RMA)– Extremely minimum memory footprint



MPI + UPC, CAF, …)• Virtualization• Energy-Awareness• InfiniBand Network Analysis and Monitoring (INAM)

Overview of A Few Challenges being Addressed by MVAPICH2/MVAPICH2-X for Exascale



Hardware Multicast-aware MPI_Bcast on Stampede

2 4 8 16 32 64 128 256 512 1K05

10152025303540

Small Messages (102,400 Cores)DefaultMulticast


Late

ncy

(us)

ConnectX-3-FDR (54 Gbps): 2.7 GHz Dual Octa-core (SandyBridge) Intel PCI Gen3 with Mellanox IB FDR switch

2K 4K 8K 16K 32K 64K 128K0

100

200

300

400

500Large Messages (102,400 Cores)

DefaultMulticast


Late

ncy

(us)

16 32 64128

256512 1K 2K 4K 6K

05

1015202530 16 Byte Message

DefaultMulticast

Number of Nodes

Late

ncy

(us)

16 32 64128

256512 1K 2K 4K 6K

0

50

100

150

200 32 KByte Message

DefaultMulticast

Number of Nodes

Late

ncy

(us)

512 600 720 8000

1

2

3

4

5

Appl

icati

on R

un-T

ime

(s)

Data Size

64 128 256 51205

1015

PCG-Default Modified-PCG-Offload

Number of Processes

Run-

Tim

e (s

)Co-Design with MPI-3 Non-Blocking Collectives and Collective Offload Co-Direct Hardware (Available with MVAPICH2-X 2.2a)

22

Modified P3DFFT with Offload-Alltoall does up to 17% better than default version (128 Processes)

K. Kandalla, et. al.. High-Performance and Scalable Non-Blocking All-to-All with Collective Offload on InfiniBand Clusters: A Study with Parallel 3D FFT, ISC 2011


17%

0

0.5

1

1.5HPL-Offload HPL-1ring HPL-Host

Nor

mal

ized

Perf

orm

ance

HPL Problem Size (N) as % of Total Memory

4.5%

Modified HPL with Offload-Bcast does up to 4.5% better than default version (512 Processes)

Modified Pre-Conjugate Gradient Solver with Offload-Allreduce does up to 21.8% better than default version

K. Kandalla, et. al, Designing Non-blocking Broadcast with Collective Offload on InfiniBand Clusters: A Case Study with HPL, HotI 2011

K. Kandalla, et. al., Designing Non-blocking Allreduce with Collective Offload on InfiniBand Clusters: A Case Study with Conjugate Gradient Solvers, IPDPS ’12

21.8%

Can Network-Offload based Non-Blocking Neighborhood MPI Collectives Improve Communication Overheads of Irregular Graph Algorithms? K. Kandalla, A. Buluc, H. Subramoni, K. Tomko, J. Vienne, L. Oliker, and D. K. Panda, IWPAPS’ 12




• Integrated Support for GPGPUs• Integrated Support for Intel MICs• MPI-T Interface• Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM,

MPI + UPC, CAF, …)• Virtualization• Energy-Awareness • InfiniBand Network Analysis and Monitoring (INAM)



24

PCIe

GPU

CPU

NIC

Switch

At Sender: cudaMemcpy(s_hostbuf, s_devbuf, . . .); MPI_Send(s_hostbuf, size, . . .);

At Receiver: MPI_Recv(r_hostbuf, size, . . .); cudaMemcpy(r_devbuf, r_hostbuf, . . .);

• Data movement in applications with standard MPI and CUDA interfaces

High Productivity and Low Performance


MPI + CUDA - Naive

25

PCIe

GPU

CPU

NIC

Switch

At Sender: for (j = 0; j < pipeline_len; j++) cudaMemcpyAsync(s_hostbuf + j * blk, s_devbuf + j *

blksz, …);for (j = 0; j < pipeline_len; j++) { while (result != cudaSucess) { result = cudaStreamQuery(…); if(j > 0) MPI_Test(…); } MPI_Isend(s_hostbuf + j * block_sz, blksz . . .); }MPI_Waitall();

<<Similar at receiver>>

• Pipelining at user level with non-blocking MPI and CUDA interfaces

Low Productivity and High Performance


MPI + CUDA - Advanced

26

At Sender:

At Receiver: MPI_Recv(r_devbuf, size, …);

insideMVAPICH2

• Standard MPI interfaces used for unified data movement• Takes advantage of Unified Virtual Addressing (>= CUDA 4.0) • Overlaps data movement from GPU with RDMA transfers

High Performance and High Productivity

MPI_Send(s_devbuf, size, …);


GPU-Aware MPI Library: MVAPICH2-GPU


CUDA-Aware MPI: MVAPICH2 1.8-2.2 Releases

• Support for MPI communication from NVIDIA GPU device memory

• High performance RDMA-based inter-node point-to-point communication (GPU-GPU, GPU-Host and Host-GPU)

• High performance intra-node point-to-point communication for multi-GPU adapters/node (GPU-GPU, GPU-Host and Host-GPU)

• Taking advantage of CUDA IPC (available since CUDA 4.1) in intra-node communication for multiple GPU adapters/node

• Optimized and tuned collectives for GPU device buffers• MPI datatype support for point-to-point and collective

communication from GPU device buffers

• OFED with support for GPUDirect RDMA is developed by NVIDIA and Mellanox

• OSU has a design of MVAPICH2 using GPUDirect RDMA– Hybrid design using GPU-Direct RDMA

• GPUDirect RDMA and Host-based pipelining• Alleviates P2P bandwidth bottlenecks on

SandyBridge and IvyBridge

– Support for communication using multi-rail– Support for Mellanox Connect-IB and ConnectX

VPI adapters– Support for RoCE with Mellanox ConnectX VPI

adapters


GPU-Direct RDMA (GDR) with CUDA

IB Adapter

SystemMemory

GPUMemory

GPU

CPU

Chipset

P2P write: 5.2 GB/sP2P read: < 1.0 GB/s

SNB E5-2670

P2P write: 6.4 GB/sP2P read: 3.5 GB/s

IVB E5-2680V2

SNB E5-2670 /

IVB E5-2680V2

29

Performance of MVAPICH2-GDR with GPU-Direct-RDMA


MVAPICH2-GDR-2.1RC2Intel Ivy Bridge (E5-2680 v2) node - 20 cores

NVIDIA Tesla K40c GPUMellanox Connect-IB Dual-FDR HCA

CUDA 7Mellanox OFED 2.4 with GPU-Direct-RDMA

0 1 2 4 8 16 32 64 128

256

512

1K 2K 4K0

5

10

15

20

25

30MV2-GDR2.1RC2MV2-GDR2.0bMV2 w/o GDR

GPU-GPU Internode Small Message Latency


Late

ncy

(us)

3.5X 9.3X

2.15 usec

1 2 4 8 16 32 64 128

256

512

1K 2K 4K0

500

1000

1500

2000

2500

3000

3500MV2-GDR2.1RC2MV2-GDR2.0bMV2 w/o GDR

GPU-GPU Internode MPI Uni-Directional Band-width


Band

wid

th (M

B/s)

11x

2X

1 2 4 8 16 32 64 128

256

512

1K 2K 4K0

50010001500200025003000350040004500

MV2-GDR2.1RC2MV2-GDR2.0bMV2 w/o GDR

GPU-GPU Internode Bi-directional Bandwidth


Bi-B

andw

idth

(MB/

s)

11x

2x


Application-Level Evaluation (HOOMD-blue)

• Platform: Wilkes (Intel Ivy Bridge + NVIDIA Tesla K20c + Mellanox Connect-IB)• HoomdBlue Version 1.0.5

• GDRCOPY enabled: MV2_USE_CUDA=1 MV2_IBA_HCA=mlx5_0 MV2_IBA_EAGER_THRESHOLD=32768 MV2_VBUF_TOTAL_SIZE=32768 MV2_USE_GPUDIRECT_LOOPBACK_LIMIT=32768 MV2_USE_GPUDIRECT_GDRCOPY=1 MV2_USE_GPUDIRECT_GDRCOPY_LIMIT=16384

• MVAPICH2-GDR 2.1RC2 with GDR support can be downloaded from https://mvapich.cse.ohio-state.edu/download

• System software requirements• Mellanox OFED 2.1 or later• NVIDIA Driver 331.20 or later• NVIDIA CUDA Toolkit 6.0 or later• Plugin for GPUDirect RDMA– http://www.mellanox.com/page/products_dyn?product_family=116– Strongly Recommended : use the new GDRCOPY module from NVIDIA

• https://github.com/NVIDIA/gdrcopy

• Has optimized designs for point-to-point communication using GDR• Contact MVAPICH help list with any questions related to the package

[email protected]

Using MVAPICH2-GDR Version

31HPCAC Brazil Conference (Aug ‘15)

https://mvapich.cse.ohio-state.edu/download

http://www.mellanox.com/page/products_dyn?product_family=116

mailto:[email protected]








MPI Applications on MIC Clusters

Xeon Xeon Phi

Multi-core Centric

Many-core Centric

MPI Program

MPI Program

Offloaded Computation

MPI Program

MPI Program

MPI Program

Host-only

Offload (/reverse Offload)

Symmetric

Coprocessor-only

• Flexibility in launching MPI jobs on clusters with Xeon Phi


34

MVAPICH2-MIC 2.0 Design for Clusters with IB and MIC• Offload Mode

• Intranode Communication

• Coprocessor-only and Symmetric Mode

• Internode Communication

• Coprocessors-only and Symmetric Mode

• Multi-MIC Node Configurations

• Running on three major systems

• Stampede, Blueridge (Virginia Tech) and Beacon (UTK)


MIC-Remote-MIC P2P Communication with Proxy-based Communication


Bandwidth

Better Bette

rBe

tter

Latency (Large Messages)

8K 32K

128K

512K 2M

010002000300040005000


Late

ncy

(use

c)

1 8 64 512 4K 32

K25

6K 2M0

2000

4000

6000


Band

wid

th

(MB/

sec)

5236

Intra-socket P2P

Inter-socket P2P

8K 32K

128K

512K 2M

0

5000

10000

15000


Late

ncy

(use

c)

Latency (Large Messages)

1 8 64 512 4K 32

K25

6K 2M0

2000

4000

6000


Band

wid

th

(MB/

sec)Better

5594

Bandwidth

36

Optimized MPI Collectives for MIC Clusters (Allgather & Alltoall)


A. Venkatesh, S. Potluri, R. Rajachandrasekar, M. Luo, K. Hamidouche and D. K. Panda - High Performance Alltoall and Allgather designs for InfiniBand MIC Clusters; IPDPS’14, May 2014

1 2 4 8 16 32 64 128256512 1K0

5000

10000

15000

20000

25000 32-Node-Allgather (16H + 16 M)Small Message Latency

MV2-MIC

MV2-MIC-Opt


Late

ncy

(use

cs)

8K 16K 32K 64K 128K256K512K 1M0

200000

400000

600000

800000

1000000

1200000

140000032-Node-Allgather (8H + 8 M)

Large Message Latency

MV2-MIC

MV2-MIC-Opt


Late

ncy

(use

cs)

4K 8K 16K 32K 64K 128K 256K 512K0

100000200000300000400000500000600000700000800000 32-Node-Alltoall (8H + 8 M)

Large Message Latency

MV2-MIC

MV2-MIC-Opt


Late

ncy

(use

cs)

MV2-MIC-Opt MV2-MIC05

1015202530354045 P3DFFT Performance

Communication Computation

32 Nodes (8H + 8M), Size = 2K*2K*1K

Exec

ution

Tim

e (s

ecs)

76%58%

55%








MVAPICH2-X for Advanced MPI and Hybrid MPI + PGAS Applications


MPI, OpenSHMEM, UPC, CAF or Hybrid (MPI + PGAS) Applications

Unified MVAPICH2-X Runtime

InfiniBand, RoCE, iWARP

OpenSHMEM Calls MPI CallsUPC Calls

• Unified communication runtime for MPI, UPC, OpenSHMEM, CAF available with MVAPICH2-X 1.9 (2012) onwards! – http://mvapich.cse.ohio-state.edu

• Feature Highlights– Supports MPI(+OpenMP), OpenSHMEM, UPC, CAF, MPI(+OpenMP) + OpenSHMEM,

MPI(+OpenMP) + UPC – MPI-3 compliant, OpenSHMEM v1.0 standard compliant, UPC v1.2 standard

compliant (with initial support for UPC 1.3), CAF 2008 standard (OpenUH)– Scalable Inter-node and intra-node communication – point-to-point and collectives

CAF Calls

38

http://mvapich.cse.ohio-state.edu/overview/mvapich2x



Application Level Performance with Graph500 and SortGraph500 Execution Time

J. Jose, S. Potluri, K. Tomko and D. K. Panda, Designing Scalable Graph500 Benchmark with Hybrid MPI+OpenSHMEM Programming Models, International Supercomputing Conference (ISC’13), June 2013J. Jose, K. Kandalla, M. Luo and D. K. Panda, Supporting Hybrid MPI and OpenSHMEM over InfiniBand: Design and Performance Evaluation, Int'l Conference on Parallel Processing (ICPP '12), September 2012

4K 8K 16K05

101520253035

MPI-SimpleMPI-CSCMPI-CSRHybrid (MPI+OpenSHMEM)

No. of Processes

Tim

e (s

)

13X

7.6X

• Performance of Hybrid (MPI+ OpenSHMEM) Graph500 Design

• 8,192 processes- 2.4X improvement over MPI-

CSR- 7.6X improvement over MPI-

Simple• 16,384 processes

- 1.5X improvement over MPI-CSR

- 13X improvement over MPI-Simple

J. Jose, K. Kandalla, S. Potluri, J. Zhang and D. K. Panda, Optimizing Collective Communication in OpenSHMEM, Int'l Conference on Partitioned Global Address Space Programming Models (PGAS '13), October 2013.

Sort Execution Time

500GB-512

1TB-1K 2TB-2K 4TB-4K0

50010001500200025003000

MPI Hybrid

Input Data - No. of Processes

Tim

e (s

econ

ds)

51%

• Performance of Hybrid (MPI+OpenSHMEM) Sort Application

• 4,096 processes, 4 TB Input Size- MPI – 2408 sec; 0.16 TB/min- Hybrid – 1172 sec; 0.36 TB/min- 51% improvement over MPI-

design









• Virtualization has many benefits– Job migration– Compaction

• Not very popular in HPC due to overhead associated with Virtualization

• New SR-IOV (Single Root – IO Virtualization) support available with Mellanox InfiniBand adapters

• Enhanced MVAPICH2 support for SR-IOV• Publicly available as MVAPICH2-Virt library

Can HPC and Virtualization be Combined?


J. Zhang, X. Lu, J. Jose, R. Shi and D. K. Panda, Can Inter-VM Shmem Benefit MPI Applications on SR-IOV based Virtualized InfiniBand Clusters? EuroPar'14

J. Zhang, X. Lu, J. Jose, M. Li, R. Shi and D.K. Panda, High Performance MPI Libray over SR-IOV enabled InfiniBand Clysters, HiPC’14 J. Zhang, X .Lu, M. Arnold and D. K. Panda, MVAPICH2 Over OpenStack with SR-IOV: an Efficient Approach to build HPC Clouds, CCGrid’15

20,10 20,16 20,20 22,10 22,16 22,200

50

100

150

200

250

300

350

400

450

MV2-SR-IOV-Def

MV2-SR-IOV-Opt

MV2-Native

Problem Size (Scale, Edgefactor)Ex

ecuti

on T

ime

(us)

4%

9%

FT-64-C EP-64-C LU-64-C BT-64-C0

5

10

15

20

25

30

35

MV2-SR-IOV-Def

MV2-SR-IOV-Opt

MV2-Native

NAS Class C

Exec

ution

Tim

e (s

)

1%

9%

• Compared to Native, 1-9% overhead for NAS• Compared to Native, 4-9% overhead for Graph500


Application-Level Performance (8 VM * 8 Core/VM)

NAS Graph500


NSF Chameleon Cloud: A Powerful and Flexible Experimental Instrument

• Large-scale instrument– Targeting Big Data, Big Compute, Big Instrument research– ~650 nodes (~14,500 cores), 5 PB disk over two sites, 2 sites connected with 100G network

• Reconfigurable instrument– Bare metal reconfiguration, operated as single instrument, graduated approach for ease-of-

use

• Connected instrument– Workload and Trace Archive– Partnerships with production clouds: CERN, OSDC, Rackspace, Google, and others– Partnerships with users

• Complementary instrument– Complementing GENI, Grid’5000, and other testbeds

• Sustainable instrument– Industry connections http://www.chameleoncloud.org/

43

http://www.chameleoncloud.org/










• MVAPICH2-EA (Energy-Aware)• A white-box approach• New Energy-Efficient communication protocols for pt-pt and

collective operations• Intelligently apply the appropriate Energy saving techniques• Application oblivious energy saving

• OEMT• A library utility to measure energy consumption for MPI applications• Works with all MPI runtimes• PRELOAD option for precompiled applications • Does not require ROOT permission:

• A safe kernel module to read only a subset of MSRs

45

Energy-Aware MVAPICH2 & OSU Energy Management Tool (OEMT)


• An energy efficient runtime that provides energy savings without application knowledge

• Uses automatically and transparently the best energy lever

• Provides guarantees on maximum degradation with 5-41% savings at <= 5% degradation

• Pessimistic MPI applies energy reduction lever to each MPI call

46

MV2-EA : Application Oblivious Energy-Aware-MPI (EAM)

A Case for Application-Oblivious Energy-Efficient MPI Runtime A. Venkatesh , A. Vishnu , K. Hamidouche , N. Tallent ,

D. K. Panda , D. Kerbyson , and A. Hoise - Supercomputing ‘15, Nov 2015 [Best Student Paper Finalist]


1









OSU InfiniBand Network Analysis Monitoring Tool (INAM) – Network Level View

• Show network topology of large clusters• Visualize traffic pattern on different links• Quickly identify congested links/links in error state• See the history unfold – play back historical state of the network

Full Network (152 nodes) Zoomed-in View of the Network


Upcoming OSU INAM Tool – Job and Node Level Views

Visualizing a Job (5 Nodes) Finding Routes Between Nodes

• Job level view• Show different network metrics (load, error, etc.) for any live job• Play back historical data for completed jobs to identify bottlenecks

• Node level view provides details per process or per node• CPU utilization for each rank/node• Bytes sent/received for MPI operations (pt-to-pt, collective, RMA)• Network metrics (e.g. XmitDiscard, RcvError) per rank/node

• Performance and Memory scalability toward 500K-1M cores– Dynamically Connected Transport (DCT) service with Connect-IB

• Hybrid programming (MPI + OpenSHMEM, MPI + UPC, MPI + CAF …)• Enhanced Optimization for GPU Support and Accelerators• Taking advantage of advanced features

– User Mode Memory Registration (UMR)– On-demand Paging

• Enhanced Inter-node and Intra-node communication schemes for upcoming OmniPath enabled Knights Landing architectures

• Extended RMA support (as in MPI 3.0)• Extended topology-aware collectives• Energy-aware point-to-point (one-sided and two-sided) and collectives• Extended Support for MPI Tools Interface (as in MPI 3.0)• Extended Checkpoint-Restart and migration support with SCR

MVAPICH2 – Plans for Exascale


51

• Scientific Computing– Message Passing Interface (MPI), including MPI + OpenMP, is the

Dominant Programming Model – Many discussions towards Partitioned Global Address Space

(PGAS) • UPC, OpenSHMEM, CAF, etc.

– Hybrid Programming: MPI + PGAS (OpenSHMEM, UPC)

• Big Data/Enterprise/Commercial Computing– Focuses on large data and data analysis– Hadoop (HDFS, HBase, MapReduce) – Spark is emerging for in-memory computing– Memcached is also used for Web 2.0

Two Major Categories of Applications


Can High-Performance Interconnects Benefit Big Data Computing? • Most of the current Big Data systems use Ethernet

Infrastructure with Sockets• Concerns for performance and scalability• Usage of High-Performance Networks is beginning to draw

interest• What are the challenges?• Where do the bottlenecks lie?• Can these bottlenecks be alleviated with new designs (similar

to the designs adopted for MPI)?• Can HPC Clusters with High-Performance networks be used

for Big Data applications using Hadoop and Memcached?


Big Data Middleware(HDFS, MapReduce, HBase, Spark and Memcached)

Networking Technologies(InfiniBand, 1/10/40GigE

and Intelligent NICs)

Storage Technologies(HDD and SSD)

Programming Models(Sockets)

Applications

Commodity Computing System Architectures

(Multi- and Many-core architectures and accelerators)

Other Protocols?

Communication and I/O Library

Point-to-PointCommunication

QoS

Threaded Modelsand Synchronization

Fault-ToleranceI/O and File Systems

Virtualization

Benchmarks

RDMA Protocol

Designing Communication and I/O Libraries for Big Data Systems: Solved a Few Initial Challenges


Upper level Changes?

53

Design Overview of HDFS with RDMA

• Enables high performance RDMA communication, while supporting traditional socket interface

• JNI Layer bridges Java based HDFS with communication library written in native code

HDFS

Verbs

RDMA Capable Networks(IB, 10GE/ iWARP, RoCE ..)

Applications

1/10 GigE, IPoIB Network

Java Socket Interface

Java Native Interface (JNI)

WriteOthers

OSU Design

• Design Features– RDMA-based HDFS

write– RDMA-based HDFS

replication– Parallel replication

support– On-demand connection

setup– InfiniBand/RoCE

support


Communication Times in HDFS

• Cluster with HDD DataNodes– 30% improvement in communication time over IPoIB (QDR)– 56% improvement in communication time over 10GigE

• Similar improvements are obtained for SSD DataNodes

Reduced by 30%


2GB 4GB 6GB 8GB 10GB0

5

10

15

20

25

10GigE IPoIB (QDR) OSU-IB (QDR)

File Size (GB)

Com

mun

icati

on T

ime

(s)

55

N. S. Islam, M. W. Rahman, J. Jose, R. Rajachandrasekar, H. Wang, H. Subramoni, C. Murthy and D. K. Panda , High Performance RDMA-Based Design of HDFS over InfiniBand , Supercomputing (SC), Nov 2012N. Islam, X. Lu, W. Rahman, and D. K. Panda, SOR-HDFS: A SEDA-based Approach to Maximize Overlapping in RDMA-Enhanced HDFS, HPDC '14, June 2014

Triple-H

Heterogeneous Storage

• Design Features– Three modes

• Default (HHH)• In-Memory (HHH-M)• Lustre-Integrated (HHH-L)

– Policies to efficiently utilize the heterogeneous storage devices

• RAM, SSD, HDD, Lustre

– Eviction/Promotion based on data usage pattern

– Hybrid Replication– Lustre-Integrated mode:

• Lustre-based fault-tolerance

Enhanced HDFS with In-memory and Heterogeneous Storage

Hybrid Replication

Data Placement Policies

Eviction/Promotion

RAM Disk SSD HDD

Lustre

N. Islam, X. Lu, M. W. Rahman, D. Shankar, and D. K. Panda, Triple-H: A Hybrid Approach to Accelerate HDFS on HPC Clusters with Heterogeneous Storage Architecture, CCGrid ’15, May 2015

Applications


• For 160GB TestDFSIO in 32 nodes– Write Throughput: 7x improvement

over IPoIB (FDR)– Read Throughput: 2x improvement

over IPoIB (FDR)

Performance Improvement on TACC Stampede (HHH)

• For 120GB RandomWriter in 32 nodes– 3x improvement over IPoIB (QDR)

write read0

1000

2000

3000

4000

5000

6000IPoIB (FDR) OSU-IB (FDR)

Tota

l Thr

ough

put (

MBp

s)

TestDFSIO

8:30 16:60 32:1200

50

100

150

200

250

300IPoIB (FDR) OSU-IB (FDR)

Cluster Size:Data Size

Exec

ution

Tim

e (s

)

RandomWriter


Increased by 7x

Increased by 2xReduced by 3x

57

• For 200GB TeraGen on 32 nodes– Spark-TeraGen: HHH has 2.1x improvement over HDFS-IPoIB (QDR)– Spark-TeraSort: HHH has 16% improvement over HDFS-IPoIB (QDR)

58

Evaluation with Spark on SDSC Gordon (HHH)

8:50 16:100 32:2000

50

100

150

200

250IPoIB (QDR) OSU-IB (QDR)

Cluster Size : Data Size (GB)

Exec

ution

Tim

e (s

)

8:50 16:100 32:2000

100

200

300

400

500

600IPoIB (QDR) OSU-IB (QDR)

Cluster Size : Data Size (GB)

Exec

ution

Tim

e (s

)TeraGen TeraSort

Reduced by 16%Reduced by 2.1x


N. Islam, M. W. Rahman, X. Lu, D. Shankar, and D. K. Panda, Performance Characterization and Acceleration of In-Memory File Systems for Hadoop and Spark Applications on HPC Clusters, IEEE BigData ’15, October 2015

Design Overview of MapReduce with RDMA

MapReduce

Verbs

RDMA Capable Networks(IB, 10GE/ iWARP, RoCE ..)

OSU Design

Applications

1/10 GigE, IPoIB Network

Java Socket Interface

Java Native Interface (JNI)

JobTracker

TaskTracker

Map

Reduce


• Enables high performance RDMA communication, while supporting traditional socket interface• JNI Layer bridges Java based MapReduce with communication library written in native code

• Design Features– RDMA-based shuffle– Prefetching and caching map

output– Efficient Shuffle Algorithms– In-memory merge– On-demand Shuffle Adjustment– Advanced overlapping

• map, shuffle, and merge• shuffle, merge, and reduce

– On-demand connection setup– InfiniBand/RoCE support

59

• For 240GB Sort in 64 nodes (512 cores)– 40% improvement over IPoIB (QDR)

with HDD used for HDFS

Performance Evaluation of Sort and TeraSort


Data Size: 60 GB Data Size: 120 GB

Data Size: 240 GB

Cluster Size: 16 Cluster Size: 32 Cluster Size: 64

0

200

400

600

800

1000

1200

IPoIB (QDR) UDA-IB (QDR) OSU-IB (QDR)

Job

Exec

ution

Tim

e (s

ec)

Sort in OSU Cluster

Data Size: 80 GB Data Size: 160 GB

Data Size: 320 GB

Cluster Size: 16 Cluster Size: 32 Cluster Size: 64

0

100

200

300

400

500

600

700IPoIB (FDR) UDA-IB (FDR) OSU-IB (FDR)

Job

Exec

ution

Tim

e (s

ec)

TeraSort in TACC Stampede

• For 320GB TeraSort in 64 nodes (1K cores)– 38% improvement over IPoIB

(FDR) with HDD used for HDFS60

Intermediate Data Directory

Design Overview of Shuffle Strategies for MapReduce over Lustre


• Design Features– Two shuffle approaches

• Lustre read based shuffle• RDMA based shuffle

– Hybrid shuffle algorithm to take benefit from both shuffle approaches

– Dynamically adapts to the better shuffle approach for each shuffle request based on profiling values for each Lustre read operation

– In-memory merge and overlapping of different phases are kept similar to RDMA-enhanced MapReduce design

Map 1 Map 2 Map 3

Lustre

Reduce 1 Reduce 2

Lustre Read / RDMA

In-memory merge/sort

reduce

M. W. Rahman, X. Lu, N. S. Islam, R. Rajachandrasekar, and D. K. Panda, High Performance Design of YARN MapReduce on Modern HPC Clusters with Lustre and RDMA, IPDPS, May 2015.

In-memory merge/sort

reduce

61

• For 500GB Sort in 64 nodes– 44% improvement over IPoIB (FDR)

Performance Improvement of MapReduce over Lustre on TACC-Stampede


• For 640GB Sort in 128 nodes– 48% improvement over IPoIB (FDR)

300 400 5000

200

400

600

800

1000

1200

IPoIB (FDR)OSU-IB (FDR)

Data Size (GB)

Job

Exec

ution

Tim

e (s

ec)

20 GB 40 GB 80 GB 160 GB 320 GB 640 GBCluster: 4 Cluster: 8 Cluster: 16 Cluster: 32 Cluster: 64 Cluster: 128

0

50

100

150

200

250

300

350

400

450

500

IPoIB (FDR) OSU-IB (FDR)

Job

Exec

ution

Tim

e (s

ec)

M. W. Rahman, X. Lu, N. S. Islam, R. Rajachandrasekar, and D. K. Panda, MapReduce over Lustre: Can RDMA-based Approach Benefit?, Euro-Par, August 2014.

• Local disk is used as the intermediate data directoryReduced by 48%Reduced by 44%

62

Design Overview of Spark with RDMA

• Design Features– RDMA based shuffle– SEDA-based plugins– Dynamic connection

management and sharing– Non-blocking and out-of-

order data transfer– Off-JVM-heap buffer

management– InfiniBand/RoCE support


• Enables high performance RDMA communication, while supporting traditional socket interface

• JNI Layer bridges Scala based Spark with communication library written in native code

X. Lu, M. W. Rahman, N. Islam, D. Shankar, and D. K. Panda, Accelerating Spark with RDMA for Big Data Processing: Early Experiences, Int'l Symposium on High Performance Interconnects (HotI'14), August 2014

63

Performance Evaluation on TACC Stampede - SortByTest

• Intel SandyBridge + FDR, 16 Worker Nodes, 256 Cores, (256M 256R)• RDMA-based design for Spark 1.4.0 • RDMA vs. IPoIB with 256 concurrent tasks, single disk per node and

RamDisk. For SortByKey Test:– Shuffle time reduced by up to 77% over IPoIB (56Gbps) – Total time reduced by up to 58% over IPoIB (56Gbps)

16 Worker Nodes, SortByTest Shuffle Time 16 Worker Nodes, SortByTest Total Time


16 32 640

5

10

15

20

25

30

35

40IPoIB RDMA

Data Size (GB)

Tim

e (s

ec)

16 32 640

5

10

15

20

25

30

35

40IPoIB RDMA

Data Size (GB)

Tim

e (s

ec)

77%

58%

Memcached-RDMA Design

• Server and client perform a negotiation protocol– Master thread assigns clients to appropriate worker thread– Once a client is assigned a verbs worker thread, it can communicate directly and is “bound” to that thread

• Memcached Server can serve both socket and verbs clients simultaneously– All other Memcached data structures are shared among RDMA and Sockets worker threads

• Memcached applications need not be modified; uses verbs interface if available• High performance design of SSD-Assisted Hybrid Memory

SocketsClient

RDMAClient

MasterThread

SocketsWorker Thread

VerbsWorker Thread

SocketsWorker Thread

VerbsWorker Thread

SharedData

Memory&

SSDSlabsItems

…

1

1

2

2


J. Jose, H. Subramoni, M. Luo, M. Zhang, J. Huang, M. W. Rahman, N. Islam, X. Ouyang, H. Wang, S. Sur and D. K. Panda, Memcached Design on High Performance RDMA Capable Interconnects, ICPP’11

J. Jose, H. Subramoni, K. Kandalla, M. W. Rahman, H. Wang, S. Narravula, and D. K. Panda, Scalable Memcached design for InfiniBand Clusters using Hybrid Transport, CCGrid’12

D. Shankar, X. Lu, J. Jose, M. W. Rahman, N. Islam, and D. K. Panda, Can RDMA Benefit On-Line Data Processing Workloads with Memcached and MySQL, ISPASS’15

• ohb_memlat & ohb_memthr latency & throughput micro-benchmarks• Memcached-RDMA can

- improve query latency by up to 70% over IPoIB (32Gbps)- improve throughput by up to 2X over IPoIB (32Gbps)- No overhead in using hybrid mode with SSD when all data can fit in memory

Performance Benefits on SDSC-Gordon – OHB Latency & Throughput Micro-Benchmarks

64 128 256 512 10240123456789

10 IPoIB (32Gbps)RDMA-Mem (32Gbps)RDMA-Hybrid (32Gbps)

No. of Clients

Thro

ughp

ut (m

illio

n tr

ans/

sec)

1 4 16 64256

10244096

1638465536

2621440

50100150200250300350400450500

IPoIB (32Gbps)RDMA-Mem (32Gbps)RDMA-Hyb (32Gbps)


Aver

age

late

ncy

(us)

2X

66

D. Shankar, X. Lu, M. W. Rahman, N. Islam, and D. K. Panda, Benchmarking Key-Value Stores on High-Performance Storage and Interconnects for Web-Scale Workloads, IEEE BigData ‘15.


• RDMA for Apache Hadoop 2.x (RDMA-Hadoop-2.x)

• RDMA for Apache Hadoop 1.x (RDMA-Hadoop)

• RDMA for Memcached (RDMA-Memcached)

• OSU HiBD-Benchmarks (OHB)– HDFS and Memcached Micro-benchmarks

• http://hibd.cse.ohio-state.edu• Users Base: 125 organizations from 20 countries

• More than 13,000 downloads from the project site

• RDMA for Apache HBase and Spark

The High-Performance Big Data (HiBD) Project


http://hibd.cse.ohio-state.edu/

• Upcoming Releases of RDMA-enhanced Packages will support– Spark

– HBase

• Upcoming Releases of OSU HiBD Micro-Benchmarks (OHB) will support– MapReduce

– RPC

• Advanced designs with upper-level changes and optimizations• E.g. MEM-HDFS


Future Plans of OSU High Performance Big Data (HiBD) Project

68

• Exascale systems will be constrained by– Power– Memory per core– Data movement cost– Faults

• Programming Models and Runtimes for HPC and BigData need to be designed for– Scalability– Performance– Fault-resilience– Energy-awareness– Programmability– Productivity

• Highlighted some of the issues and challenges• Need continuous innovation on all these fronts

Looking into the Future ….



Funding Acknowledgments

Funding Support by

Equipment Support by

70

Personnel AcknowledgmentsCurrent Students

– A. Augustine (M.S.)– A. Awan (Ph.D.)– A. Bhat (M.S.)– S. Chakraborthy (Ph.D.)– C.-H. Chu (Ph.D.)– N. Islam (Ph.D.)

Past Students – P. Balaji (Ph.D.)– D. Buntinas (Ph.D.)– S. Bhagvat (M.S.)– L. Chai (Ph.D.)– B. Chandrasekharan (M.S.)– N. Dandapanthula (M.S.)– V. Dhanraj (M.S.)– T. Gangadharappa (M.S.)– K. Gopalakrishnan (M.S.)

– G. Santhanaraman (Ph.D.)– A. Singh (Ph.D.)– J. Sridhar (M.S.)– S. Sur (Ph.D.)– H. Subramoni (Ph.D.)– K. Vaidyanathan (Ph.D.)– A. Vishnu (Ph.D.)– J. Wu (Ph.D.)– W. Yu (Ph.D.)

Past Research Scientist– S. Sur

Current Post-Doc– J. Lin– D. Shankar

Current Programmer– J. Perkins

Past Post-Docs– H. Wang– X. Besseron– H.-W. Jin– M. Luo

– W. Huang (Ph.D.)– W. Jiang (M.S.)– J. Jose (Ph.D.)– S. Kini (M.S.)– M. Koop (Ph.D.)– R. Kumar (M.S.)– S. Krishnamoorthy (M.S.)– K. Kandalla (Ph.D.)– P. Lai (M.S.)– J. Liu (Ph.D.)

– M. Luo (Ph.D.)– A. Mamidala (Ph.D.)– G. Marsh (M.S.)– V. Meshram (M.S.)– A. Moody (M.S.)– S. Naravula (Ph.D.)– R. Noronha (Ph.D.)– X. Ouyang (Ph.D.)– S. Pai (M.S.)– S. Potluri (Ph.D.) – R. Rajachandrasekar (Ph.D.)

– K. Kulkarni (M.S.)– M. Li (Ph.D.)– M. Rahman (Ph.D.)– D. Shankar (Ph.D.)– A. Venkatesh (Ph.D.)– J. Zhang (Ph.D.)

– E. Mancini– S. Marcarelli– J. Vienne

Current Senior Research Associates– K. Hamidouche– X. Lu

Past Programmers– D. Bureddy

– H. Subramoni

Current Research Specialist– M. Arnold


[email protected]


Thank You!

The High-Performance Big Data Projecthttp://hibd.cse.ohio-state.edu/

72

Network-Based Computing Laboratoryhttp://nowlab.cse.ohio-state.edu/

The MVAPICH2 Projecthttp://mvapich.cse.ohio-state.edu/

http://nowlab.cse.ohio-state.edu/

http://nowlab.cse.ohio-state.edu/

73

Call For Participation

International Workshop on Extreme Scale Programming Models and Middleware

(ESPM2 2015)In conjunction with Supercomputing Conference

(SC 2015)Austin, USA, November 15th, 2015

http://web.cse.ohio-state.edu/~hamidouc/ESPM2/





• Looking for Bright and Enthusiastic Personnel to join as – Post-Doctoral Researchers

– PhD Students

– Hadoop/Big Data Programmer/Software Engineer

– MPI Programmer/Software Engineer

• If interested, please contact me at this conference and/or send an e-mail to [email protected]

74

Multiple Positions Available in My Group
