Contents Section Page Title & Contents (this page) 1 Notes & Gate Identification 2 Block Diagram 3 Timing 4 Keyboard and Control (part 1) 5 Control (part 2) 6 Control (part 3) 7 Registers 8 Arithmetic 9 Decimal Point Management 10 Display 11 Power Supply 12 Timing Diagram 13 IC Pinouts 14 IC Notes & Gate Construction 15 Connectors 16 Commodore DAC-612 Calculator Commodore DAC-612 Calculator Section: Title and Contents Page: 1 Rendition: 2014 Mar 7 This schematic has been derived through reverse engineering. This is not the manufacturer’s schematic, nor is it based on the manufacturer’s schematic.
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Contents Section Page
Title & Contents (this page) 1Notes & Gate Identification 2Block Diagram 3Timing 4Keyboard and Control (part 1) 5Control (part 2) 6Control (part 3) 7Registers 8Arithmetic 9Decimal Point Management 10Display 11Power Supply 12Timing Diagram 13IC Pinouts 14IC Notes & Gate Construction 15Connectors 16
Commodore DAC-612Calculator
Commodore DAC-612 CalculatorSection: Title and Contents
Page: 1 Rendition: 2014 Mar 7
This schematic has been derived through reverse engineering.This is not the manufacturer’s schematic, nor is it based on the manufacturer’s schematic.
Notes
♦ Gate symbols and signal names are presented in accordance with: logic 0 = GND (0V) logic 1 = V–24
♦ A lowercase “n” in a signal name indicates the logical NOT operation.
♦ The symbol Ncpp denotes a physical connector pin where c=connector, and pp=pin. Solid black end is the male side of the connector. White end is the female side of the connector.
♦ connection between different sections. connection limited to same section. Arrows indicate direction of signal or energy flow.
♦ The symbol denotes V–24.
♦ Resistance in ohms unless otherwise indicated.
♦ Capacitance in microfarads unless otherwise indicated.
♦ These drawings based on unit with Serial No. 209040.
♦ SC1772 ICs of Unit 209040 stamped with 6921 and 6945.
♦ Drawn Jan. to Feb. 2000 by bhilpert. See www.cs.ubc.ca/~hilpert/eec for additional information.
Gate Identification
Gates and logic elements are identified by a symbol of the form:b g n
whereb = board (A, B or C)g = gate type identifier (1 or 2 characters, see table below)n = number
andboard A = lower boardboard B = upper boardboard C = display board
See “Connectors” page for more about board identification.
Gate Type ID Description A discrete AND gateO discrete OR gateS 12–bit shift register in µPD11 ICU 2–input OR gate in µPD101C ICV 3–input OR gate in µPD102C ICY 48–bit shift register in SC1772 IC1D 2 or 3–input OR gate in HD3106 IC1E flip-flop in HD3107 IC1L inverter in µPD13C IC1M serial BCD adder in HD3112 IC1R 48–bit shift register in µPD106 IC2C flip–flop in µPD10(C) IC2D 4–input OR gate in µPD15C IC2E switch in µPD110C IC
See “IC Pinouts and Gate Construction” page for more about the integrated circuits.
♦ Based on supply voltage, circuit impedances and logic density, IC technology are presumed to be early MOS.
♦ Outputs are open-collector, except SC1772.
♦ These diagrams presented in accordance with:• Logic FALSE or 0 is considered to be GND.• Logic TRUE or 1 is considered to be –24V.
♦ Some ICs in the µPD family came in two packages: TO-100/101 cans and 14-pin DIPs. The C suffix indicates the DIP package.
♦ Inferred for µPD110C:The 4 elements are not standard logic elements. They appear to be MOS transistors. They function as a bidirectional switch, or as a 2–input OR gate with one input inverted.
switch is closed when logicalcontrol input b is TRUE (–24V) equivalent
Care is taken in the logic design to ensure another “wire-ANDed” output does not feed back through the element to affect the state of the signal driving the non-inverted input.
♦ Inferred for flip-flops:The flip-flops in this logic family appear to be Master/Slave D-type flip-flops with the clocks for the master and slave sections kept separate. This permits a system design where data capture is done in accordance with the requirements of the logic while all outputs are changed synchronously by a single clock signal.
The state of the D input is captured when ØC is TRUE (–24V).The Q output is set in accordance with the captured state when ØT goes TRUE.
♦ Inferred for HD3112:This device appears to be a full-blown Serial BCD Adder, performing serial addition, bit carry, tens carry, correction for digit sums greater than 9, negation, etc.
Commodore DAC-612 CalculatorSection: IC Notes and Gate Construction
Page: 15 Rendition: 2014 Mar 7
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Discrete Gate Construction
Most AND gates are constructed from discrete diodes and resistors. Most OR gates and complex logic elements are contained in integrated circuits. The internal construction of discrete gates is shown in the following diagrams. A wire-AND or wire-OR construction is indicated by the input line traversing the width of the gate.
All gate outputs ,except the few discrete OR gates and the Philco SC1772 shift registers, require external load resistors (R) connected from the output to V–24. To reduce clutter these resistors are indicated in the schematic by one of the following symbols near the output.
Discrete Modular 30K
100K220K
All discrete OR gates are loaded by a 5.6K resistor to ground.