Combined

Contents × i

Handbook of Experiments

in

Electronics and Communication

Engineering

ii Ø Contents

Contents × iii

Handbook of Experiments

in

Electronics and Communication

Engineering

S Poornachandra RaoAssistant Professor

SSN College of Engineering, Chennai

B SasikalaSenior Lecturer

Crescent Engineering College, Chennai

vikas publishing house pvt ltd

iv Ø Contents

Contents × v

To our loving daughters

Niveditha & Nanditha

vi Ø Contents

Contents × vii

PREFACE

This lab manual has been primarily designed to cater to the practical requirements of the students

of Electronics and Communication Engineering of various universities globally. Students of other

engineering branches such as EEE, EIE, CSE, IT, ICE and ME may also find it useful. It may

also serve as a reference for polytechnic and science students.

The experiments have been organised in 8 chapters.

Chapter 1 deals with network experiments.

Chapter 2 deals with device characteristics.

Chapter 3 deals with electronic circuit designs.

Chapter 4 deals with op-amp and IC 555 experiments.

Chapter 5 deals with digital design experiments.

Chapter 6 deals with communication experiments.

Chapter 7 deals with microwave communication.

Chapter 8 deals with assembly language programming using 8085 kit.

Each experiment explains the aim, essential theory and statements, equipment required,

procedure, complete circuit diagram, tabulation, model graphs and result.

We welcome suggestions for the improvement in the future editions of the book.

Authors

viii Ø Contents

Contents × ix

ACKNOWLEDGEMENTS

We take this opportunity to acknowledge all those who were associated with us in this endeavour.

The management, staff and students of Crescent Engineering College and SSN College of

Engineering for their cooperation and support.

Our parents for our blessings and constant encouragement.

And finally Mr. P.K. Madhavan, members of Vijay Nicole Imprints, and Vikas Publishing

House for publishing this book.

Authors

CONTENTS

Preface vii

Acknowledgements ix

1. BASIC NETWORK 1.1

Kirchhoff’s Voltage Law 1.16

Superposition Theorem 1.17

Maximum Power Transfer Theorem 1.19

Thevenin’s Theorem 1.20

Norton’s Theorem 1.23

Reciprocity Theorem 1.25

Transient Response 1.26

Series Resonance 1.28

Parallel Resonance 1.31

Differentiator 1.34

Integrator 1.35

Constant-k LPF 1.38

Constant-k HPF 1.40

Constant-k Band Pass Filter 1.42

Constant-k Band Elimination Filter 1.43

m-Derived LPF 1.45

m-Derived HPF 1.47

Twin-T Filter 1.48

Equalizer 1. 50

Attenuator 1.51

2. DEVICE CHARACTERISTICS 2.1

Diode Characteristics 2.2

Rectifier 2.4

Clipping Circuits 2.7

Clamper Circuits 2.9

Transistor (CE - Configuration) Characteristics 2.10

Transistor (CC - Configuration) Characteristics 2.13

xii Ø Contents

Transistor (CB - Configuration) Characteristics 2.16

Transistor Switch 2.18

Field-effect Transistor 2.20

Unijunction Transistor 2.22

Silicon Controlled Rectifier 2.23

DIAC 2.25

Photo-detector 2.27

Voltage Regulator 2.29

Thermistor 2.32

3. AMPLIFIER CIRCUIT DESIGN 3.1

RC Coupled Amplifier 3.2

Two Stage RC – Coupled Amplifier 3.5

Emitter Follower (Common Collector Amplifier) 3.9

Darlington Pair (Common Collector Amplifier) 3. 12

Cascode Amplifier 3.15

Field Effect Transistor 3.18

Differential Amplifier 3.21

Class-A Power Amplifier: Resistive Load 3.24

Class-A Power Amplifier: Inductive Load (Design) 3.26

Class-A Power Amplifier—Inductive Load (Efficiency) 3.29

Class-A Power Amplifier with Transformer Coupled Load 3.31

Class-B Power Amplifier 3.33

Class-C Power Amplifier (Efficiency) 3.36

Class-C Power Amplifier (Design) 3.39

Current-series Feedback Amplifier 3.40

Voltage-Series Feedback Amplifier 3.44

Current-shunt Feedback Amplifier 3.49

Voltage-shunt Feedback Amplifier 3.54

Wein Bridge Oscillator 3.60

RC Phase Shift Oscillator 3.63

Hartley and Colpitt Oscillator 3.68

Voltage Sweep Generator 3.71

RF Amplifier 3.72

Single Tuned Amplifier 3.75

Bi-stable Multivibrator 3.78

Monostable Multivibrator 3.79

Astable Multivibrator 3.81

Contents × xiii

4. OPERATIONAL AMPLIFIER (OP-AMP) 4.1

Characteristics of op-amp 4.1

Linear Applications of Op-amp 4.4

Non-linear Applications: Comparators 4.7

Pulse Detector and Window Comparator 4. 9

Instrumentation Amplifier 4.11

Non-linear Applications: Waveform Generators 4.12

Schmitt Trigger 4.16

Precision Rectifier 4.18

Study of V-I & I-V Converter Using Op-amp 4.19

Voltage to Frequency Converter 4.21

Study of Active Filters Using Op-amp 4.22

Digital to Analog Converter 4.25

Study of Digital to Analog Converter 4.26

Analog to Digital Converter 4.27

Study of Analog to Digital Converter 4.28

Study of Application of 555 Timer 4.30

Phase Locked Loop 4.33

5. DIGITAL ELECTRONICS 5.1

Logic Gates 5.4

Simplification of a Boolean Expression and Its Realisation Using Logic Gates 5.6

Adders 5.10

Subtractor 5.13

Parity Generation and Checking 5.14

Multiplexer 5.16

Demultiplexer 5.17

Encoders 5.18

Decoders 5.19

Study of Flip-flop 5.23

Study of Shift Registers 5.26

Asynchronous Counter 5.30

Synchronous Counter 5.35

Synchronous Sequential Circuit (Design) 5.37

Synchronous Sequential Circuit (State Diagram) 5.39

xiv Ø Contents

6. COMMUNICATION CIRCUITS 6.1

Amplitude Modulation 6.1

Amplitude Demodulation 6.3

Frequency Modulation 6.4

Frequency Demodulation 6.6

Pulse Position Modulator 6.7

Pulse Amplitude Modulation 6.9

Pulse Width Modulation 6.11

Pulse Width Modulation & Pulse Position Modulation 6.12

Amplitude Shift Keying Modulator 6.15

Amplitude Shift Keying Demodulator 6.16

Pseudo Random Binary Sequence Generator 6.17

Frequency Shift Keying Modulator 6.18

Frequency Shift Keying Demodulator 6.20

Pre-Emphasis 6.21

De-Emphasis 6.23

Digital Phase Detector 6.24

Mixer (Using Discrete Component) 6.26

Mixer (Using IC) 6.27

Auto Ranging 6.28

Frequency Counter 6.30

Cross Over Network 6.31

Directional Characteristics of Loud Speaker and Microphone 6.33

Linear Variable Differential Transformer 6.34

AC and DC Measurement Using PMMC 6.36

Squelch Circuit 6.37

Blocking Oscillator 6.39

Frequency Multiplier 6.40

Frequency Synthesizer 6.41

Automatic Gain Control 6.43

7. MICROWAVE COMMUNICATION CIRCUITS 7.1

Voltage Standing Wave Ratio 7.1

Horn Antenna 7.2

Impedance Measurement 7.4

Directional Coupler 7.6

Shunt TEE and Series TEE 7.7

Contents × xv

RF Mixer 7.9

Dielectric Measurement 7.10

Directional Characteristics of Microphone 7.13

Performance of Circulator 7.15

Performance of Faraday’s Rotation Spectrometer 7.16

Measure of Attenuation 7.17

DC Characteristics of LED and PIN Photodiode 7.19

Gunn Oscillator Characteristics 7.20

Reflex Klystron Repeller Mode Characteristics 7.22

Relation Between Frequency and Wavelength in Free Space 7.24

8. MICROPROCESSOR 8085 8.1

Standard Programs 8.9

1. Program to interchange the data byte between two locations 8.9

2. Program to exchange the data byte stored in register-D with register-H and data

byte stored in register-E with register-L 8.10

3. Program to exchange the data byte stored in register-D with register-H and data

byte stored in register E with register-L. 8.10

4. Program to add two 8 bit binary number (overflow considered) 8.11

5. Program to add N 8 bit binary numbers (overflow considered) 8.11

6. Program to add two 16-bit binary numbers 8.12

7. Program to add two 8-bit BCD numbers 8.12

8. Subtraction of two 8-bit numbers 8.13

9. Program to subtract two BCD numbers 8.13

10. Program to subtract two 16-bit numbers 8.14

11. Program to multiply two 8-bit binary numbers 8.15

12. Program to multiply two 8-bit binary numbers (Shifting and adding) 8.15

13. Program to perform multiplication of two 16-bit binary number. 8.16

14. Program to perform division of two 8-bit binary numbers 8.17

15. Program to find number of 1’s and 0’s in a given 8 bit binary number 8.18

16. Program to find the smallest to N 8-bit binary number 8.19

17. Program to obtain the descending order of N 8-bit binary numbers 8.20

18. Program to convert 8-bit binary number to gray code 8.21

19. Program to convert gray code to 8-bit binary number 8.21

20. Program to convert ASCII hex number into its binary equivalent 8.22

xvi Ø Contents

21. Program to convert binary number into its ASCII equivalent 8.23

22. Program to convert 2 digit BCD to its binary equivalent 8.24

23. Program to convert binary numbers to its equivalent BCD 8.25

24. Program to reverse a string 8.26

25. (a) Program for generating Fibonacci series (upto (FF)H 8.26

(b) Program to generate Fibonacci series maximum [FFFF]H 8.27

26. Program to solve the given Boolean expression ZYXZYXZYXF ++= 8.28

27. Program to find the factorial of a number. 8.30

28. Program to find the square root of a number. 8.30

29. Program to find the square of a number 8.31

30. Program to find the square of a number 8.32

31. Program to find cube root of a number 8.33

32. Program to decimal count from 00 to 99 (using DAA) 8.34

33. Port address 8.35

Hardware Experiments 8.35

Waveform Generation using DAC 8.35

Square wave generation 8.35

Triangular wave generation 8.36

Sawtooth waveform generation 8.37

Staircase wave generation 8.37

Trapezoidal waveform generation 8.38

Sinewave generation 8.38

Matrix Type Keyboard Interface 8.39

Control of Stepper Motor 8.40

Basic Network × 1.1

C h a p t e r 1

BASIC NETWORK

UNITS AND ITS RELATIONS

Admittance (mho, Ω) = 1/impedance (ohm, Ω) Displacement = charge × length (coulomb-m)

Boltzmann’s constant (k) = 1.381 × 10-23 J/ 0 k Electronic charge = 1.602 × 10-19 C

Capacitance (Farad, F) = charge/potential Electronic mass = 9.109 × 10-31kg

Charge (Coulomb, C) = current × time Energy density = energy/volume (joule/m3)

Charge density (ρ) = charge/volume (coulomb/m3) Permeability of free space (µ0) = 1.257 × 10-6 H/m

Conductance (G) = 1/resistance Permittivity of free space (ε0) = 8.854 × 10-12 F/m

Current (Ampere, A) = charge/time Planck’s constant (h) = 6.626 × 10–31 J-sec

Current density (J) = current/area (A/m2) Velocity of light (c) = 3 × 10+8 m/sec

Unit System

The international system of units (SI) is based on fundamental units.

Quantity Unit Abbreviation

Length

Mass

Time

Luminous intensity

Temperature

Charge

Current

Energy

Force

Potential

Power

Frequency

Capacitance

Inductance

Resistance

meter

kilogram

second

candela

kelvin

coulomb

ampere

joule

newton

volt

watt

hertz

farad

henry

ohm

m

kg

sec

Cd

K

C

A

J

N

V

W

Hz

F

H

Ω

Prefix Symbol Multiplier

Tera

Giga

Mega

Kilo

Centi

Milli

Micro

Nano

Pico

T

G

M

K

c

m

µ

n

p

1012

109

106

103

10-2

10-3

10-6

10-9

10-12

BASIC DEFINITIONS

Average Value

The average value of a waveform, which swings symmetrically across the zero reference, will be zero for a

complete full-cycle.

Multiples

1.2 Ø Handbook of Experiments in Electronics and Communication Engineering

RMS Value

The RMS value of an alternating voltage or current is the value, which would produce the same heat in a

resistance as a direct voltage or current of the same magnitude.

Peak Value (Vm)

The amplitude of a waveform is a measure of the extent of its voltage or current excursion from the zero

reference.

Peak-to-peak value = 2 × peak value

VPP

= 2Vm

RESISTOR COLOR CODE

Color coding is used for identifying the value of the given resistor. There are two methods of color coding in

use, namely

1. Four colored band

2. Five colored band

Four Colored Band

Example

Brown; Black; Red; Gold

1 0 102

±5%

Value is 1000 ± 5% Ω

Five Colored Band

Example

Red; Yellow; Black; Black; Red

2 4 0 100 ±2%

Actual value = 240 ± 2% Ω

Color Band Color Multiplier Color Tolerance

Black 0

Brown 1

Red 2

Orange 3

Yellow 4

Green 5

Blue 6

Violet 7

Grey 8

White 9

Silver 10-2

Gold 10-1

Black 100=1

Brown 101=10

Red 102

Orange 103

Yellow 104

Green 105

Blue 106

Brown ±1%

Red ±2%

Gold ±5%

Silver ±10%

No color ±20%

Color Band Color Multiplier Color Tolerance

Black 0

Brown 1

Red 2

Orange 3

Yellow 4

Green 5

Blue 6

Violet 7

Grey 8

White 9

Silver 10-2

Gold 10-1

Black 100=1

Brown 101=10

Red 102

Orange 103

Yellow 104

Green 105

Blue 106

Red ±2%

Gold ±5%

Silver ±10%

No color ±20%


COMPONENTS, DEVICES AND THEIR SYMBOLS

Grounding/ Earthing AC voltage source (sinusoidal) V

Fixed DC power supply V

+

–

AC voltage source (pulsating) V

Variable DC power supply V

+

–

Current source

+

–

I

Components Fixed Variable

Resistor

Capacitor

Inductor

Transformer

Switches


DIODES AND THEIR SYMBOLS


Power Supply

230V AC (± 10%), 50 Hz.

Precaution

The cover can be taken off after unplugging the power cord’s trip contact connector. The case, chassis and all

measuring terminals are to be connected to the protective earth contact of the inlet. The mains plug shall only

be inserted in a socket outlet when it connected to a protective earth contact. The protective action must not

be negated by the use of an extension cord without a protective conductor.


WARNING: Any interruptions of the protection conductors inside or outside the instruments or

disconnection of the protective earth terminals are likely to make the instruments dangerous. The

mains plug should be inserted before connections are made to test circuits.

Under certain conditions, 50 Hz hum voltage can occur in the circuit due to instrumentation with other

mains powered equipment or instrument. This can be avoided by using an insulation transformer between the

mains outlet and power plug of the instrument.

It should be noted that generators always deliver an output but never take an input and hence care should

be taken that no input is given in any form to the output ports. If condensed water exists in the instrument, it

should be acclimatized before switching on. The instruments should be kept in a clean and dry room and must

not be operated in explosive, corrosive, dusty or moist environments. The ventilation holes must not be covered.

Maintenance of Devices

The exterior of the instruments should be dusted with brushes. Dirt can be removed with moist cloth, spirit or

washing with benzene. The display can only be cleaned with water or washing with benzene (not with spirit).

BASIC LAB INSTRUMENTS

Ammeter

Ammeters are connected in series with the circuit whose current is to be measured. Therefore they should have

a low electrical resistance. This is essential in order that they cause a small voltage drop and consequently

absorb small power.

Voltmeter

Voltmeters are connected in parallel with the circuit whose voltage is to be measured. They should have a high

electrical resistance. This is essential in order that the current drawn by them is small and consequently the

power absorbed is also small.

Ohmmeter

They are used for measurement of resistance. They incorporate a source of emf and a current measuring device.

TYPES OF INSTRUMENTS USED AS AMMETERS AND VOLTMETERS

Permanent Magnet Moving Coil (PMMC)

This type can be used for DC measurements only. This is a more accurate type for DC measurement.

Moving Iron and Moving Coil

Both these types depend upon the magnetic effect of current. It can be used for either DC or AC measurements.

Electrodynamics Meter

These types of instruments are used both for AC and DC measurement. The calibration for both DC and AC is

the same and hence they are very useful as “transfer instruments”.

Induction Type

These types of instruments are used for AC measurement alone. The induction principles are generally used for

watt-hour meter than for ammeters and voltmeters owing to the comparative high cost.


Electrostatic Type

As voltmeters, they have an advantage that their power consumption is exceedingly small. They can be made

to cover a large range of voltage. Their main disadvantage is that the electrostatic principle is only directly

applicable to voltage measurements.

CATHODE RAY OSCILLOSCOPE (CRO)

The cathode ray oscilloscope is the most versatile measuring instrument available. We can measure the following

parameters using the CRO.

1. AC or DC voltage

2. Time

=

ft

1

3. Phase relationship

4. Waveform evaluation: Rise time, Fall time, ON-time, OFF-time, Distortion, etc.

We can also measure non-electrical physical quantities like pressure, strain, temperature, acceleration, etc.

by converting them into electrical quantity using suitable transducer.

Fig. 1.1 Cathode Ray Oscilloscope


Major Blocks in a CRO

1. Cathode ray tube (CRT)

2. Vertical amplifier

3. Horizontal amplifier

4. Sweep generator

5. Trigger circuit

6. Associated power supply

A Practical CRO

CRO consists of a Cathode Ray Tube (CRT) and additional control knobs. The main parts of a CRT are

1. Electron gun assembly

2. Deflection plate assembly

3. Fluorescent screen

Electron Gun Assembly

The electron gun assembly produces a sharp beam of electrons, which are accelerated to high velocity. This

focussed beam of electrons strikes the fluorescent screen with sufficient energy to cause a luminous spot on

the screen.

Deflection Plate Assembly

This part consists of two parallel plates in which one pair of plates is placed horizontally and other pair placed

vertically. The signal under test is applied to vertical deflecting plates. The horizontal deflection plates are

connected to a built-in ramp generator which moves the luminous spot periodically in a horizontal direction

from left to right over the screen. These two deflection plates give the actual waveform. The rate at which it

traces the waveform gives stationary appearance to the waveform on the screen. CRO operates on voltage

since the deflection of the electron beam is directly proportional to the deflecting voltage. This means that the

CRT may be used as a linear measuring device.

The voltage being measured is applied to the vertical plates through an iterative network, whose propagation

time corresponds to the velocity of electrons, thereby the voltage applied to the vertical plates is made to

synchronize with the velocity of the beam.

Synchronization of Input Signal

The sweep generator produces a sawtooth waveform, which is used to synchronize the applied signal to obtain

a stationary-applied signal. This requires that the time base be operated at a submultiple frequency of the signal

under measurement. If synchronization is not done, the pattern is not stationary, but appears to drift across the

screen in a random fashion.

Internal synchronization This trigger is obtained from the time-base generator to synchronize with the

signal.

External synchronization An external trigger source can also be used to synchronize the signal being

measured.


Auto Triggering Mode

The time-base used in this case is in a self-oscillating condition, i.e. it gives an output even in the absence of

any Y-input. The advantage of this mode is that the beam is visible on the screen under all conditions including

the zero input. When the input exceeds a certain magnitude, the internal free-running oscillator locks on to the

frequency of the input signal and provides a stable synchronized display. This is so for all frequencies of the

input higher than the free running frequency of the time-base generator in the auto mode. When the frequency

of the Y-input is less than this, synchronization is not assured and the “AC trigger” mode has to be used. In the

AC trigger mode, the time-base generator is controlled by a monostable, which in turn is triggered by a set level

obtained from the Y-amplifier output. In HF trigger mode, triggering amplifier is bypassed internally, to avoid

failure of triggering due to delays arising from the triggering amplifier. In this mode, the repetition rate of time

base is higher as compared to that in the auto mode.

The bombarding electrons, striking the screen, release secondary emission electrons. These secondary

electrons are collected by an aqueous solution of graphite.

The bandwidth of an oscilloscope normally refers to the 3dB bandwidth of the vertical amplifier in the

normal sensitivity range.

Position Control

Applying small independent internal DC voltage to the deflecting plates does the positioning of the trace and

control with the help of a potentiometer.

Focus Control

The focussing electrode acts like a lens whose focal length can be changed using a potentiometer. These will

align the beam without spreading outward.

Intensity Control

Varying the potentiometer connected to the grid voltage can vary the intensity of the beam. Intensity basically

refers to the number of electrons ejected (depending upon the filament heating) from the plate of the electron

gun.

Z-modulation

The voltage applied to the grid of the CRT in this case can be controlled by an external signal connected to the

Z-mode input. This is used for brightening the display.

Calibration Circuit

Square wave amplitude and frequency is calibrated to a definite value (say 0.2 V at 1 kHz) for calibration as well

as testing purpose.


INTRODUCTION TO NETWORKS

An electrical network is a combination of electrical elements

like resistors, capacitors, inductors, etc. Network analysis

deals with the analysis of the response of the network for a

given excitation.

If the relationship of response to excitation is linear i.e. change in input results in a corresponding change

in output, then electrical network is called linear.

ACTIVE AND PASSIVE ELEMENTS

Active Elements

An active element is one which is capable of generating energy on its own.

Example: Transistor, FET, etc.

Passive Elements

A passive element is one which is incapable of generating energy on its own. But it is capable of storing and

dissipating energy. It always needs some external source of power.

Example: Resistor, Capacitor, Inductor, etc.

NETWORK ELEMENTS

ResistorR

A resistor is a passive circuit element, which consumes energy. All electrical devices, which consume energy,

must have resistance in their circuit model. The power consumed by a resistor is given by

P = I2 R

where I = current flowing through the resistor.

I = DC current

i = AC current

Resistance can be defined by Ohm’s law i.e. at a constant temperature, the voltage drop between ends of

a conductor is directly proportional to the current flowing through it.

VR

VkI

VI

1==

α

where k = constant of proportionality =

R

1

R = resistance of the conductor (ohm, Ω)

V = I R

Inductor

L

An inductor is a circuit element which is capable of storing energy in the form of current for some period and

delivers the same after this time. The average power for inductor is zero. Inductor plays a vital role in electric

motor, transformer, etc.

Network

Input

(Excitation) (Response)

Output

Fig. 1.2 Two Port Network


They are usually made of many turns of fine wires wound in a coil form. For an ideal inductance, the voltage

is proportional to the rate of change of current i.e.

dt

diLtv

dt

ditv

=)(

)( α

where L = inductance (Henry, H).

The current in the inductance can be found out by integrating the above equation with respect to time.

Therefore,

∫= dttvL

ti )(1

)(

The energy stored in an inductor is given by

2

2

1CVP =

Capacitor

C

A capacitor is a circuit element, which is capable of storing energy in the form of voltage, during some period

and returns during other time. Thus the average power for capacitor is zero.

For an ideal capacitor, the voltage is proportional to the integral of current, i.e.

∫= dtiC

tv1

)( (i)

where C = capacitor (Farad, F)

The voltage is proportional to the change in charge to the change in capacitance.

dC

dQtv =)(

(ii)

The current in the capacitance can be found out by differentiating equation (i) with respect to time, i.e.

dt

dvCi =

The energy stored in a capacitor is given by

2

2

1LIP =

ENERGY SOURCE

Ideal Current Source

The ideal current source is one which produces a constant current irrespective

of voltage across it. The current source can be represented symbolically by

Fig. 1.3

It is necessary to connect the current source to some external circuit to

complete the path of the current. An ideal current source must be capable of

supplying infinite power. Fig. 1.3 Ideal Current Source


Ideal Voltage Source

The ideal voltage source is one which produces constant voltage irrespective of current through it. The

voltage source can be symbolically represented by

V DC Voltage

+

–

+ –

I

V(t) AC Voltage

i

Fig. 1.4a DC Voltage Source Fig. 1.4b AC Voltage Source

When the voltage source becomes open-circuited, it should not draw any current and hence power is zero.

If the voltage source is short-circuited, then infinite amount of current flows through it and hence power is

infinity.

Dependent and Independent Sources

Ideal current and voltage sources are examples of independent sources. In the case of dependent sources, the

source voltage or current is not constant, but it depends on a voltage or current of some other source. They are

broadly divided into the following types.

1. Current controlled current source

2. Current controlled voltage source

3. Voltage controlled current source

4. Voltage controlled voltage source

Mutual Inductance

Mutual inductance is due to mutual interaction of the

magnetic field created by the inductance. Thus,

magnetic field produced by changing current in one

inductor induces a voltage in another inductor.

The above principle is obtained from the Faraday’s

law. According to this law, a coil containing N turns,

with magnitude of flux φ linking each turn, has an

induced emf

dt

dNe

φ−=

A negative sign is frequently included in this equation to signal that the voltage polarity is established

according to Lenz’s law.

By definition of self-inductance, the voltage is given by,

Fig. 1.5 Mutual Inductance


id

dNL

dt

dN

dt

diL

φ

φ

=

=

where φ = flux (weber, Wb).

Coupling Coefficient

The total flux f, resulting from current i1 through N

1 consist of

leakage flux f11

and coupling flux f12

. The induced emf in coupled

coils is given by

Therefore,

1

122

122

id

dNM

dt

dN

dt

diMe

φ

φ

=

==

where M = mutual inductance.

As the coupling is bilateral,

2

211

id

dNM

φ=

The coupling coefficient k, is defined as the ratio of linking flux to the total flux.

[ ]102

21

1

12≤≤== kk

φ

φ

φ

φ

Therefore, M = k

21 LL

If k = 1, then all the flux from one coil is transferred to the other without any leakage in flux (close coupling).

For k = 0, no flux from one coil induces a voltage in the other.

Transformer

An ideal transformer is a hypothetical transformer in which there are no losses and the core has infinite

permeability, resulting in perfect coupling with no leakage flux. In large power transformer, the losses are small

relative to the power transferred.

PASSIVE ELEMENT CONFIGURATION

Resistors in Series

When resistors (R1, R

2, R

3) are connected in series, the

total voltage (VT) across two terminals (1 and 2) is equal

to the algebraic sum of individual voltages (V1, V

2, V

3)

across each resistance. The current (iT) flowing through

all resistors is same. Therefore

321 RRRReq ++=

When resistors are connected in series, the equivalent resistance is the addition of all resistors connected

in series.

Fig. 1.6 Flux Linkage in a Transformer

Fig. 1.7a Resistors in Series


Resistors in Parallel

When resistors (R1, R

2, R

3) are connected in parallel,

the total current (iT) is equal to the algebraic sum of

individual currents (i1, i

2, i

3) flowing through their

resistor. The voltage (VT) across each resistor is same

(all are connected in parallel with source). Therefore

321

1111

RRRReq

++=

Inductors in Series

When inductors (L1, L

2, L

3) are connected in series, the total

voltage (VT) across two terminals (1 and 2) is equal to the algebraic

sum of individual voltages (V1, V

2, V

3) across each inductor. The

current (iT) flowing through all inductors is same. Therefore,

321 LLLLeq ++=

When inductors are connected in series, the equivalent inductance is the addition of all inductors connected

in series.

Inductors in Parallel

If inductors (L1, L

2, L

3) are connected in parallel, the

total currents (it) is equal to the algebraic sum of

individual currents (i1, i

2, i

3) flowing through

individual inductor. The voltage (VT) drop across

each inductor remains same. Therefore,

321

1111

LLLLeq

++=

Capacitors in Series

When capacitors (C1, C

2, C

3) are connected in

series, the total voltage (VT) across two terminals

(1 and 2) is equal to the algebraic sum of individual

voltages (V1, V

2, V

3) across each capacitor. The

current (iT) flowing through all capacitors is same.

Therefore,

321

1111

CCCCeq

++=

Fig. 1.7b Resistors in Parallel

Fig. 1.8a Inductors in Series

Fig. 1.8b Inductors in Parallel

Fig. 1.9a Capacitors in Series


Capacitors in Parallel

When capacitors (C1, C

2, C

3) are connected in

parallel the total current (iT) is equal to the algebraic

sum of individual currents (i1, i

2, i

3) flowing

through individual capacitor. The voltage drop (VT)

across each capacitor remains same. Therefore,

321 CCCCeq ++=

When capacitors are connected in parallel, the equivalent capacitance is the addition of all parallel connected

capacitors.

NETWORK SIMPLIFICATION

Delta (∆∆∆∆∆) to Star (Y)

Z1 = Z

A Z

B / (Z

A + Z

B + Z

C)

Z2 = Z

B Z

C / (Z

A + Z

B + Z

C)

Z3 = Z

C Z

A / (Z

A + Z

B + Z

C)

Star (Y) to Delta (∆∆∆∆∆)

ZA = (Z

1 Z

2 + Z

2 Z

3+ Z

3 Z

1) / Z

2

ZB = (Z

1 Z

2 + Z

2 Z

3+ Z

3 Z

1) / Z

3

ZC = (Z

1 Z

2 + Z

2 Z

3+ Z

3 Z

1) / Z

1

OHM’S LAW

At a constant temperature, the current flowing through a conductor is directly proportional to the voltage

difference across the conductor. The proportionality constant is given by 1/R.

IR

V

IV

=

∝

1

where R = Resistance of the conductor (ohm, Ω).

KIRCHHOFF’S LAW

Kirchhoff’s Current Law (KCL)

It states that at any node, the sum of the currents entering a node is

equal to the sum of the current leaving. The connection of two or

more circuit elements (branches) creates a junction called a Node.

Current entering a node (N): IA, I

B

Current leaving a node (N): IC, I

D, I

E

According to KCL, IA

+ IB

= IC + I

D + I

E

Fig. 1.9b Capacitors in Parallel

Fig. 1.10 Star to Delta Conversion, Delta to

Star Conversion

A

B

C

D

N

E

IB

IA

IE

ID

IC

Fig. 1.11 Kirchhoff’s Current Law


Kirchhoff’s Voltage Law (KVL)

For any closed path in any network, the al-

gebraic sum of the emfs is equal to the alge-

braic sum of the IR drops.

Emfs are V1 and V

2

IR drops are VR1

= I R1; V

R2= I R

2;

VR3

= I R3.

According to KVL,

V1 + (–V

2) = I R

1 + I R

2 + I R

3

Experiment 1.1

Kirchhoff’s Voltage Law

Aim To verify the Kirchhoff’s voltage law.

Equipment Required

Equipment Range Quantity

Power supply

Voltmeter

Ammeter

(0–30) V

(0–30) V

(0–10) mA

2

3

1

Circuit Diagram

Procedure

1. Connect the circuit as per the circuit diagram.

2. Switch on the power supplies (10 V and 5 V) and note down the readings in the ammeter and

voltmeters.

3. Calculate the IR drop across each resistor.

4. Verify V1 + (–V

2) = IR

1 + IR

2 + IR

3

Fig. 1.12 Kirchhoff’s Voltage Law


Experiment 1.2

Superposition Theorem

Statement In a linear bilateral network containing more than one generator, the current flowing through any

branch is the algebraic sum of currents flowing through that branch when generators are considered one at a

time and replacing other generator by their internal impedance.

Aim To verify the superposition theorem.

Equipment Required


Power supply

Ammeter

(0–30) V

(0–10) mA

2

1

Circuit Diagram

(a)

(b)


(c)

Procedure

1. Connect the circuit as per the circuit diagram [figure (a)].

2. Switch on the DC power supplies (10 V and 5 V) and note down the corresponding ammeter readings

(say I A).

3. Replace the second power supply by its internal resistance [figure (b)].

4. Switch on the power supply (10 V) and note down the corresponding ammeter reading (say I1).

5. Connect back the second power supply (5 V) and replace the first power supply by its internal

resistance [figure (c)].

6. Switch on the power supply (5 V) and note down the corresponding ammeter reading (say I2).

7. Verify the following condition: I = I1 + I

2

Tabular Column

I1 (mA) I2 (mA) I1 + I2 (mA) I (mA)

Exercise

1. Repeat the above-mentioned procedure for asymmetrical network and compare with the symmetrical

network.

V1

+ –

R1

V2

+ – R

3

R2

where R1 ≠ R

2

≠

R3

2. Verify superposition theorem for π-network.


Experiment 1.3

Maximum Power Transfer Theorem

Statement Maximum power will be delivered by a network to the load, if the impedance of the network (ZN) is

a complex conjugate of load impedance (ZL) and vice versa.

If we make XL

= –XN and R

L = R

N, maximum power will be transformed from the network to load. For

maximum power transfer, load impedance (ZL) should be complex conjugate of the network impedance (Z

N).

The maximum power transferred is given by

watts4

2

LR

VP = Aim To verify maximum power transfer theorem.

Circuit Diagram

DRB = Decade Resistance Box, DIB = Decade Inductor Box, DCB = Decade capacitor Box

Procedure


2. Set the input signal (say 1 V, 1 kHz).

3. Set the network DRB and DIB at some random value (say 1 kΩ & 1 mH).

4. Set the load DRB to the value equal to network DRB (1 kΩ) and vary the DCB of the load in regular

steps.

5. Note down the corresponding voltmeter and ammeter readings.


6. Plot the graph: Power vs Capacitance reactance.

7. Now set the load reactance equal to the network reactance.

8. Vary the DRB of the load in regular steps.

9. Note down the corresponding voltmeter and ammeter readings.

10. Plot the graph: Power vs Load resistance.

11. Compare the peak power in both the cases.

Tabular Column

Case (A): RL = R

N = 1 kΩ

XC ( ) V (Volts) I (mA) P = V I

Case (B): XL

= –XC = 1 mH/1 mF

RL (ΩΩΩΩ) V (Volts) I (mA) P = V I

Model Graphs

Exercise

Give some practical examples for maximum power transfer theorem.

Experiment 1.4

Thevenin’s Theorem

Statement Any linear bilateral network containing one or more voltage sources can be replaced by a single

voltage source whose value is equal to the open circuit voltage at output terminal with a series Thevenin’s

resistance. The Thevenin’s resistance is equal to the effective resistance looking back from the output terminal

by removing the load resistance.

Aim To verifiy Thevenin’s theorem.


Equipment Required


Power supply

Voltmeter

(0–30) V

(0–30) V

1

1

Circuit Diagram

(a)

Thevenin’s Voltage Experimental Setup

(b)

Thevenin’s Resistance Experimental Setup

(c)


Circuit Diagram

Series Resonance

The frequency of the series resonance is given by,

( )fLC

f πω

π

2Hz2

10 ==

The current at any instant in a series resonance circuit is given by,

22 1

−+

=

CLR

VI

ω

ω

At resonance,

R

VI =0

Quality Factor

Let us consider the following circuits.

(a) (b)

For RL combination [figure (a)],

RfLQ

f

RI

LI

Q

/2

2

222

max

max2

π

π

=

=


For RC combination [figure (b)].

f

RI

CV

Q2

max

max2

2

22

= π

But, C

Vω

1max =

Therefore,fRCCR

Qπω 2

11==

Since in series resonance, capacitive reactance is equal to inductive reactance (XC = X

L), the Q-factor of a

series resonance circuit is defined as the ratio of the voltage across inductor or capacitor to the applied voltage.

Therefore,

CRQ

CRR

LQ

11

1

0

0

=

==

ω

ω

Bandwidth

Bandwidth of a series resonance circuit is defined as the difference between the upper and lower half-power

frequencies.

The bandwidth is given by,

Bandwidth Q

ff 012 )(

ω=−=

where 21 ωωω =n and Q = Quality factor.

Selectivity

0

0

0

1200

1ySelectivitTherefore,

factorBut,

ySelectivit

)(ySelectivit

Q

R

LQ

L

R

fffL

R

=

=−

=

−=∆=∆

=

ω

ω

ωω

ω

Procedure

1. Set up the circuit as per the circuit diagram given for plotting resonance curve.

2. Set input voltage, Vi = 5V using signal generator and vary the frequency from (0–1) MHz in regular

steps.

3. Note down the corresponding output voltage and current.


4. Plot the following graph:

a) Current vs Frequency

b) Voltage vs Frequency

To measure the Resonance Frequency

1. Plot the graph: Current vs Frequency.

2. Draw a horizontal line which intersects the curve at 2

1 times the maximum current reading.

3. Lower intersected point and upper intersected point are respectively called lower cut off frequency and

upper cut off frequency on frequency-axis.

Tabular Column

Frequency (Hz) VR VL VC iT

Model Graph

Experiment 1.9

Parallel Resonance

A parallel AC circuit is said to be in resonance when its susceptance is zero. At parallel resonance, the applied

voltage and resulting current will be in phase.

Let us consider a general parallel circuit.


The frequency of parallel resonance is given by,

2

2

02

1

C

L

RC

L

RC

L

LCf

−

−

=

π

Current at resonance, I0 = Y

0 V

+

+

+

=22220

CC

C

LL

L

XR

R

XR

RVI

Aim To plot the resonance curve for a parallel resonance.

Equipment Required


Signal generator

Voltmeter

Ammeter

(0–1) MHz

(0–10) V

(0–10) mA

1

1

3

Circuit Diagram

(a)


Quality Factor

L

CR

L

RQ ===

00

Reactance

Resistance

ω

Bandwidth and Selectivity

In a parallel resonance circuit, the specified points are the ones at which normalized impedance falls to 2

1

of its value at resonance.

Bandwidth, BW = f2 – f

1

Selectivity = Bandwidth/f0 = (f

2 – f

1)/f

0

Procedure

1. Rig up the circuit as per the circuit diagram (figure (a)).

2. Set input voltage, Vi = 5 V using signal generator and vary the frequency from 10 Hz to 1 MHz in regular

steps.

3. Note down the corresponding output voltage and current.

4. Calculate the impedance by the formula, Z = VT/i

5. Plot the graph: Impedance vs Frequency.

To Measure the Resonance Frequency

1. Plot the graph: Impedance vs Frequency.

2. Draw a horizontal line, which intersects the curve at 2

1 times the impedance reading.

3. Lower intersected point and upper intersected point are respectively called lower cut-off frequency and

upper cut-off frequency on frequency-axis.

Tabular Column

Frequency (Hz) iR iL i Vt Z = VT / i

Model Graph

(b)


Experiment 1.10

Differentiator

A differentiator is a simple RC network. If the time constant (RC) is very small (RC<< τ ) in comparison with the

time required for the input signal to make an appropriate change, then the circuit results in a differentiated

output.

A differentiator circuit is as shown below.

V0

Aim To study the given differentiator at different time constants.

Equipment Required


Signal generator

CRO

(0–1) MHz

(0–20) MHz

1

1

Circuit Diagram

Design

Ω===

×==

====

−

k10then10If

101

msec11

kHz;1For

3

CRF,.C

RC

fTf;T

τµ

τ

τ


Ω<<>

Ω>><

k10then,For

k10then,For

CRT

CRT

ττ

ττ

Procedure


2. Set input voltage, Vi = 5V using pulse generator and vary the frequency from (0–1) MHz in regular steps.

3. Observe the output waveform using CRO.

4. Change the value of R as per the design and observe the output waveform using CRO.

Model Waveform

Experiment 1.11

Integrator

An integrator is a simple RC network. If the time constant (RC) is very large (RC>> τ ) in comparison with the

time required for the input signal to make an appropriate change, the circuit results in an integrated output.


V0

Aim To study the given integrator time constant.

Equipment Required


Signal generator

CRO

(0–1) MHz

(0–20) MHz

1

1

Circuit Diagram

Design

Ω==µ=

×==

====

−

kC

RC

RC

fTfT

10thenF,10.If

101

msec11

kHz;1;For

3

τ

τ

τ

For T < ,τ then R >

C

τ

> 10 kΩ

For T >

,τ

then R <

C

τ

< 10 kΩ

Procedure


2. Set input voltage, Vi = 5 V using pulse generator and vary the frequency from (0–1) MHz in regular steps.

3. Observe the output waveform using CRO.

4. Change the value of R as per the design and observe the output waveform using CRO.


Model Waveform

PASSIVE FILTERS

G.A.Campbell and O.I. Lobel of the Bell Telephone Laboratories invented wave filters. A filter is a reactive

network, which passes the desired frequencies only. Ideally, filters should produce no attenuation in the

desired band, called pass band, and should attenuate fully in other frequency region, called attenuation band.

The frequency, which separates the pass band and attenuation band, is termed as cut-off frequency of the wave

filter (fc).

Filter finds its application in many fields like data communication, instrumentation, signal processing, etc.

Filters are broadly divided into 4 groups

1. Low pass filter (LPF)

2. High pass filter (HPF)

3. Band pass filter (BPF)

4. Band elimination filter (BEF)

Low Pass Filter

A LPF is one which passes all frequencies up to its

designed/desired cut-off frequency, fc, and

attenuates all other frequencies greater than the

cut-off frequency.

Ideal waveform


High Pass Filter

A HPF is one, which passes all frequencies above

designed/desired cut off frequency, fc and attenuates

all other frequencies below cut off frequency.

Band Pass Filter

A BPF is one which passes frequencies between two

designed/desired cut-off frequencies (fl = lower cut

off frequency, fh = upper cut off frequency) and

attenuates all other frequencies.

Band Elimination Filter

A BEF is one which attenuates frequencies between

two designed/desired cut-off frequencies (fl = lower

cut off frequency, fh = upper cut off frequency) and

passes all other frequencies.

Filters are made of symmetrical T or L or π

network. A study of any filter requires the following

parameters.

1. Propagation constant, γ

2. Attenuation constant, α

3. Phase constant, β

4. Characteristic impedance, Z0

where Propagation constant, γ = α + jβ

Experiment 1.12

Constant-k LPF

Aim To design and test a constant-k LPF and measure its cut-off frequency.

Equipment Required

Equipment

Signal generator

CRO

Ideal waveform

Ideal waveform

Ideal waveform


Circuit Diagram

Design

inductor)(series;capacitor)(shunt1

680,kHz2,680Given

Cf

RL

RfC

RRR

RfR

k

kC

ksL

sCL

ππ

==

==

Ω==Ω=

Procedure


2. Set input voltage, Vi = 5V using signal generator and vary the frequency from 10 Hz in regular steps up to

1MHz.

3. Note down the corresponding output voltage (VO

).

4. Plot the following graph: Gain vs Frequency.

Tabular Column

Frequency (Hz) Output Voltage (volts) Gain

Model Graph


Result

Theoretical Practical

Cut-off

frequency

Exercise

Design a π-section constant-k LPF and compare the result with T-section constant-k LPF.

Experiment 1.13

Constant-k HPF

Aim To design and test a constant-k HPF and measure its cut off frequency.

Equipment Required


Signal generator

CRO

(0–1) MHz

(0–20) MHz

1

1

Circuit Diagram

Design

inductor)(shunt4

;capacitor)(series2

1

680,kHz2,680Given

C

k

kC

ksL

sCL

f

RL

RfC

RRR

RfR

ππ

==

==

Ω==Ω=

Procedure


2. Set input voltage, Vi = 5 V using signal generator and vary the frequency from 10 Hz in regular steps up to

1 MHz.


3. Note down the corresponding output voltage (V0).


Tabular Column


Model Graph

Result

Theoretical PracticalCut-off

frequency

Exercise

Design a π-section constant-k HPF and compare the result with T-section constant-k HPF.

(a) (b)


Experiment 1.14

Constant-k Band Pass Filter

Aim To design and test a constant-k BPF and measure its cut-off frequency.

Equipment Required


Signal generator

CRO

(0–1) MHz

(0–20) MHz

1

1

Circuit Diagram

Design

To evaluate the values for the series arm, consider the equations,

( )

( )121

21

121 ;

4 ff

RL

ffR

ffC k

k −

=−

=

ππ

To evaluate the values for the shunt arm, consider the equations,

( )

( )122

21

122

1;

4 ffRC

ff

ffRL

k

k

−

=−

=

ππ

Procedure


2. Set input voltage, vi = 5V using signal generator and vary the frequency from 10 Hz in regular steps upto

1 MHz.




Tabular Column


Model Graph

Result


Lower cut-off

frequency

Upper cut-off

frequency

Experiment 1.15

Constant-k Band Elimination Filter

Aim To design and test a constant-k BEF and measure its cut-off frequency.

Equipment Required


Signal generator

CRO

(0–1) MHz

(0–20) MHz

1

1


Circuit Diagram

Design

To evaluate the values for the shunt arm, consider the equations,

( )

( )122

21

122

4;

ff

RL

ffR

ffC k

k −

=−

=

ππ

To evaluate the values for the series arm, consider the equations,

( )

( )12

221

21

12221

4

1/;

ffRRLC

ff

ffRRCL

kk

kk

−

==−

==

ππ

Procedure


2. Set input voltage, Vi = 5V using signal generator and vary the frequency from 10 Hz in regular steps up to

1 MHz.



Tabular Column



Model Graph

Result


Lower cut-off

frequency

Upper cut-off

frequency

Experiment 1.16

m-Derived LPF

Aim To design and test a m-derived LPF and measure its cut-off frequency.

Equipment Required


Signal generator

CRO

(0–1) MHz

(0–20) MHz

1

1

Circuit Diagram


Design

0 < m < 1 (m = 0.5, say); f = 2 kHz

Assume C = 0.01µF

?;

1;

)1(

1

2==

−

= LLC

f

mLC

f rrππ

Procedure


2. Set input voltage, Vi = 5V using signal generator and vary the frequency from 10Hz in regular steps upto

1MHz.


).


Tabular Column


Model Graph

Result


Cut-off

frequency

Exercise

1. Design a π-section m-derived LPF and calculate its parameter. Compare the result with T-section m-derived

LPF.

2. Explain the characteristic difference between constant-k LPF over m-derived LPF.


Experiment 1.17

m-Derived HPF

Aim To design and test a m-derived HPF and measure its cut-off frequency.

Equipment Required


Signal generator

CRO

(0–1) MHz

(0–20) MHz

1

1

Circuit Diagram

Design

0 < m <1 (m = 0.5, say); f = 2 kHz

Assume C = 0.01µ F

?;4

1;

4

1. 2

=−

==∞

LLC

mf

LCfr

ππ

Procedure


2. Set input voltage, Vi = 5V using signal generator and vary the frequency from 10 Hz in a regular steps upto

1MHz.


).


Tabular Column



Model Graph

Result


Cut-off

frequency

Exercise

1. Design a π-section m-derived HPF and calculate its parameter. Compare the result with T-section

m-derived HPF.

2. Explain the characteristic difference between constant-k HPF over m-derived HPF.

Experiment 1.18

Twin-T Filter

Aim To design twin-T filter for the given frequency and to obtain its frequency response.

Equipment Required


Power supply

Functional generator

(0–30) MHz

(0–1) MHz

1

1

Components Required

Components Value Quantity

Resistor

Capacitor−

0.1 µF

3

3


Circuit diagram

Design

RCf

)2(2

10

π

=

Assume C = 0.1µF : f0 = 5 kHz; R = ?

Procedure

1. Connections are made as per the circuit diagram.

2. Set the input signal (say 1V at 5 kHz) using function generator.

3. Vary the frequency of the signal using function generator in regular steps and note down the

corresponding output voltage (VO

).

4. Plot the graph: Output Voltage (volts) vs Frequency (Hz).

Tabular Column

Vi = 1 V

Frequency (Hz) Output voltage (Volt)

Model Graph


Experiment 1.19

Equalizer

Aim To design equalizers and study their characteristics.

Equipment


CRO

Signal generator

(0–20) MHz

(0–1) MHz

1

1

Components Required


Resistor

DCB

DIB

680 Ω

−

−

2

2

2

Circuit Diagram

(a) (b)

Design

For inverse impedance, 210 ZZR =

1Therefore

1poweroutput

powerinput

1

](b)Fig[ofinversebewill;:1Case

1

0

21

20

2

1

20

21

2021

1211

−=

+==

=

=

=

=

MR

L

R

XM

RC

L

RL

L

RXX

XXLX

o

ω

ω

ω

ω


ω

ω

o

o

R

ML

RC

L

aX

XL

X

1

)](Fig[

ofinversebewill;1

:2Case

2

2

1

2

1

21

1

−=

=

=

Procedure

1. Connections are made as per the circuit diagram

2. Set the input signal say 1 V at 1 kHz using function generator.

3. Vary the signal frequency from 1 Hz to 1 kHz and note down the corresponding output voltage (VO

)

4. Plot the graph: VO

(volts) vs Frequency.

Tabular Column

Vl = 1 V

Frequency (Hz) Vo (Volt)

Model Graph

Experiment 1.20

Attenuator

An attenuator is a two-port network (purely resistance) and is used to reduce the signal level to a designed/

desired level. It will introduce a loss without affecting the impedance matching between source and the

terminating load. Attenuators can be symmetrical or asymmetrical, and also can be fixed or variable.


Attenuation (dB) = 10 log10

2

1

P

P

where P1 = input power and P

2 = output power

Aim To design a π-attenuator, which attenuates given signal to the desired level.

Equipment Required


Signal generator

CRO

(0–1) MHz

(0–20) MHz

1

1

Circuit Diagram

Design

Given D = 2 dB; Rs = R

L = 680Ω = R

0

=

−

+=

−=

20antilog;

1

1;

2

)1(02

2

01dBD

NN

NRR

N

NRR

Procedure


2. Set input voltage, Vi = 5V using signal generator and vary the frequency from 10 Hz in regular steps upto

1 MHz.


).

4. Plot the graph: Output voltage vs Frequency.

Tabular Column

Frequency (Hz) Output Voltage (volts)


Model Graph

Result

Attenuation (D) Theoretical Practical

Exercise

Repeat the procedure for other types of attenuators.

(a) T- type attenuator

(b) Bridge T-type attenuator

(c) Lattice attenuator

Device Characteristics × 2.1

C h a p t e r 2

DEVICE CHARACTERISTICS

TESTING OF ELECTRONIC DEVICES

Diode

1. Connect a multimeter (in resistance mode) across the diode.

2. Observe the resistance of the diode in that position. If it shows lower resistance value, diode is in

forward bias. Then, the terminal connected to the positive terminal of the multimeter is p-junction

and other terminal is n-junction.

3. Now, reverse the multimeter position and observe the resistance value. If it shows high resistance

then the given diode is good.

Transistor

1. Transistor follows the same rules as that of a diode.

2. For an npn transistor, connect the multimeter positive terminal to base terminal of the transistor and

negative terminal to the emitter terminal of the transistor.

3. Follow the procedure given for diode. If it is successful, then given transistor’s base-emitter junction

is good.

4. Now, shift the negative terminal of the multimeter to the collector terminal of the transistor by

maintaining the positive terminal same.

5. Follow the procedure given for diode. If it is successful, then the given transistor’s base-collector

junction is good.

6. Observe the collector to emitter resistance of the given transistor. It should be a high resistance in

both the directions.

7. Above said procedure can be executed for pnp transistor. Here, multimeter positions should be

interchanged. Remaining procedure remaining same.

Unijunction Transistor

1. In the case of UJT, emitter to base1

(configuration-1) and emitter to base2 (configuration-2) should

exhibit a typical diode characteristic except the diode resistance in forward and reverse case is different

for two configurations.

2. The resistance across base1 to base

2 should be a fixed resistance in either direction.

Field Effect Transistor

1. In the case of FET, drain to source should be fixed resistance in either direction.

2. Gate to drain or gate to source should be an open circuit or very high resistance.


Experiment 2.1

Diode Characteristics

Aim To study the diode characteristics under forward and reverse bias condition using.

1. Junction diode

2. Zener diode

Equipment Required


Power supply

Ammeter

Voltmeter

(0–30) V

(0–30) mA

(0–250) µA

(0–1) V

(0–20) V

1

1

1

1

1

Circuit Diagram

Forward bias Reverse bias

Procedure

Forward biasing


2. Vary the power supply voltage in such a way that readings should be taken in steps of 0.1 V in the

voltmeter till the power supply shows 20 V.

3. Note down the corresponding ammeter readings.

4. Plot the graph: V against I

5. Find the dynamic resistance, I

Vr

∆

∆=

Reverse biasing


2. Vary the power supply voltage in steps of 1V till the power supply shows 15V.

3. Note down the corresponding ammeter readings.


4. Plot the graph: V against I.

5. Find the dynamic resistance,I

Vr

∆

∆=

Follow the above-mentioned procedure for other diodes (say zener diode, point-contact diode, etc.)

Result

Forward and reverse bias characteristics of junction and zener diodes are plotted and their dynamic resistance

is as follows:

Dynamic Resistance r Junction Diode Zener Diode

Forward bias

Reverse bias

Note: Connect an ammeter (0–10) mA in reverse bias circuit configuration for zener diode experiment only.

Model Graph

Junction diode


Zener Diode

Experiment 2.2

Rectifier

Aim To study the following rectifiers with and without capacitor filter.

1. Half-wave rectifier

2. Full-wave rectifier

3. Bridge rectifier

To find its

1. Percentage regulation

2. Ripple factor

3. Transformer utilisation factor

4. Efficiency

Equipment Required


CRO

Multimeter

(0–20) MHz 1

1


Circuit Diagram

Half-wave rectifier

Full-wave Rectifier

Bridge Rectifier


Procedure

Without capacitor filter

1. Test your transformer. Give 230 V, 50 Hz source to the primary coil of the transformer and observe AC

waveform of rated value without any distortion at the secondary of the transformer.

2. Connect your circuit to the secondary terminals of the transformer.

3. Connect your CRO across the load.

4. Keep the CRO switch in ground-mode, observe the horizontal line and adjust it to the X-axis.

5. Switch the CRO into DC mode and observe the waveform. Note down its amplitude, Vm

and frequency

from the screen along with its multiplication factor.

6. Calculate Vdc

using the relation: π

mdc

VV = or directly from the multimeter in DC mode.

7. Switch the CRO into AC mode and observe the waveform. Note down its amplitude, Vm

and frequency

from the screen along with its multiplication factor.

8. Calculate Vac

using the relation: V2rms

= V2ac

+ V2dc

2

mrms

VV =

or directly from the multimeter in AC mode.

9. Calculate the ripple factor from the given formula:dc

ac

V

V=γ

.

10. Remove the load and measure the output AC voltage (AC-mode) and calculate the percentage of voltage

regulation using the formula:

Percentage regulation %V

VV

load

loadloadno100×

−

=

11. To measure ratio of rectification, observe the power (DC and AC) using wattmeter across the load. The

ratio of rectification is given by ac

dc

P

P.

With capacitor filter

1. Calculate the value of R by assuming C = 1000 µF and f = 50 Hz using the formula:

for HWR, the ripple factor, fRC32

1=γ (Assume γ as 0.002 or any small value).

for FWR, the ripple factor,

4=γ

(Assume γ as 0.002 or any small value)

2. Connect the capacitor across the load resistance (with polarity of the capacitor as shown in circuit diagram).

3. Switch the CRO in DC-mode. Measure the peak amplitude with respect to ground reference. Let us call

the voltage Vdc

.

4. Switch the CRO in AC-mode. Measure the peak-to-peak voltage of the signal. Let us call the AC voltage

mV =

5. The practical ripple factor can be calculated by the formula, .dc

ac

V

V=γ


Result

Parameters Half-wave Full-wave Bridge

Ripple factor with filter : theoretical

practical

0.002 0.002 0.002

Ripple factor without filter : theoretical

practical

1.21 0.48 0.48

Percentage regulation : theoretical

practical

Experiment 2.3

Clipping Circuits

Aim To observe the clipping waveform in different clipping configurations.

Equipment Required


Signal generator

CRO

Power supply

(0–1) MHz

(0–20) MHz

(0–30) V

1

1

1

Circuit Diagram

1.


2.


Procedure


2. Set input signal voltage (say 5 V, 1 kHz) using signal generator.

3. Observe the output waveform using CRO (DC-mode).

4. Sketch the observed waveform on the graph sheet.

Experiment 2.4

Clamper Circuits

Aim To study the clamping circuits

a) positive clamping circuit

b) negative clamping circuit

Equipment Required


Signal generator

CRO

Power supply

(0–1) MHz

(0–20) MHz

(0–30) V

1

1

1


Circuit Diagram

Design

Given f = 1 kHz,

RCf

T =×===− sec101

1 3τ

Assume, C = 0.1 µF

Then, R = 10 kΩ

Procedure


2. Set input signal voltage (say 5 V, 1 kHz) using signal generator.

3. Observe the output waveform using CRO (DC-mode).

4. Sketch the observed waveform on the graph sheet.

Experiment 2.5

Transistor (CE - Configuration) Characteristics

Aim To plot the transistor characteristic of common-emitter configuration and to find the h-parameters for the

same.


Equipment Required


Power supply

Ammeter

Voltmeter

(0–30) V

(0–100) µA

(0–10) mA

(0–1) V

2

1

1

Circuit Diagram

Procedure

Input characteristic


2. Set VCE

= 5 V (say), vary VBB

in steps of 1 V to 20 V and note down the corresponding IB and V

BE. Repeat

the above procedure for 10 V, 15 V, etc.

3. Plot the graph: VBE

vs IB for a constant V

CE.

4. Find the h-parameters:

a) hie

: input impedance

=

−

−

⇒

∆

∆= constant

12

12

CEBB

BEBE

CEB

BEie V

II

VVV

I

Vh

b) hre

: reverse voltage gain

=

−

−

⇒

∆

∆= constant

12

12

BCECE

BEBE

BCE

BEre I

VV

VVI

V

Vh

Output Characteristic


2. Set IB = 20µA (say), vary V

CC in steps of 1V and note down the corresponding I

C and V

CE. Repeat the

above procedure for 40µA, 60µA, 80µA.

3. Plot the graph: VCE

vs IC for a constant I

B.



a) hfe

: forward current gain

=

−

−⇒

∆

∆= constant

22

12CE

BB

ccCE

B

cfe V

II

IIV

I

Ih

b) hoe

: output admittance

=

−

−

⇒

∆

∆= constant

12

12

BCECE

cc

BCE

coe I

VV

III

V

Ih

Tabular Column

Input characteristics—VCE

constant

VBE (volts) IB (µµµµA)

Output characteristics—IB constant

VCE (volts) IC (mA)

Result

Parameters Practical Readings

hfe

hie

hre

hoe

Model Graph

Input characteristics


Output characteristics

Experiment 2.6

Transistor (CC - Configuration) Characteristics

Aim To plot the transistor characteristic of common-collector configuration and to find the h-parameters for

the same.

Equipment Required


Power supply

Ammeter

Voltmeter

(0–30) V

(0–10) mA

(0–100) µA

(0–30) V

2

1

1

1

Circuit Diagram


Procedure

Input characteristic


2. Set VEC

= 5 V (say), vary VBB

insteps of 0.1 V up to 20 V and note down the corresponding IB and V

BC.

Repeat the above procedure for VEC

10 V, 15 V, etc.

3. Plot the graph: VBC

vs IB for a constant V

EC.


a) hrc

: reverse voltage gain

=

−

−⇒

∆

∆= Constant

12

12B

ECEC

EBEBB

EC

EBrc I

VI

VVI

V

Vh

b) hic

: input impedance

=

−

−⇒

∆

∆= Constant

12

12BC

BB

BEBECE

B

BEic V

II

VVV

I

Vh

Output Characteristic


2. Set IB = 20 µA (say), vary V

EE in steps of 1V upto 20 V and note down the corresponding I

E and V

CE.

Repeat the above procedure for IB 40 mA, 80 mA, etc.

3. Plot the graph: VCE

vs IC for a constant I

B.


a) hoc

: output admittance Constant12

12=

−

−⇒

∆

∆= B

ECEC

EEB

EC

Eoc I

VV

III

V

Ih

b) hfc

: forward current gain Constant12

12=

−

−⇒

∆

∆= CE

BB

EECE

B

Efc V

II

IIV

I

Ih

Model Graph

Input Characteristics

Amplifier Circuit Design × 3.1

C h a p t e r 3

AMPLIFIER CIRCUIT DESIGN

TEST FOR ACTIVE REGION

1. According to our design, VCC

= IC

RC

+ VCE

+ IE

RE (RC - coupled amplifier design).

2. Since VCE

= VCC

/2 (to set transistor in active region), after applying biasing voltage (VCC

), the drop

across collector to emitter should be half of biasing voltage (VCC

).

3. If it is not satisfied, connect a potentiometer in series with RB2

whose value should be ± 10 kΩ with

respect to RB2

.

4. Vary the potentiometer in such a way that the voltage drop across emitter collector VCE

of the transistor

is half of the biasing voltage.

5. If any non-linearity occurs in your output waveform, introduce a negative feedback in the circuit. This

can be done by connecting a potentiometer in the emitter side whose value is above the designed

value. (top terminal of the potentiometer should be connected to the emitter terminal of the transistor,

centre terminal should be connected to the positive terminal of the capacitor and the lower terminal

should be connected to the ground of the circuit.)


6. On the other hand, by reducing the amplifier gain, we can reduce the non-linearity in the output

waveform. This can be done by replacing the fixed collector resistor (RC) by a potentiometer of the

same order and varying it in the opposite direction.

GENERAL PROCEDURE OF CALCULATION

1. Input Impedance

a) Connect a Decade Resistance Box (DRB) between input voltage source and the base of the transistor

(series connection).

b) Connect ac voltmeter (0–100 mV) across the biasing resistor R2.

c) Vary the value of DRB such that the ac voltmeter reads the voltage half of the input signal.

d) Note down the resistance of the DRB, which is the input impedance.

2. Output Impedance

a) Measure the output voltage when the amplifier is operating in the mid-band frequency with load

resistance connected (Vload

).

b) Measure the output voltage when the amplifier is operating in the mid-band frequency without load

resistance connected (Vno-load

).

c) Substitute these values in the formula,

%1000 ×−

=−

load

loadnoload

V

VVZ

3. Bandwidth

a) Plot the frequency response.

b) Identify the maximum gain region.

c) Drop a horizontal line by –3dB.

d) The –3dB line intersects the frequency response plot at two points.

e) The lower intersecting point of –3dB line with the frequency response plot gives the lower cut-off

frequency.

f) The upper intersecting point of –3dB line with the frequency response plot gives the upper cut-off

frequency.

g) The difference between upper cut-off frequency and lower cut-off frequency is called Bandwidth.

Thus, Bandwidth = fh – f

l

Experiment 3.1

RC Coupled Amplifier

Aim To design and implement the RC coupled amplifier circuit and to find:

1. Cut-off frequencies

2. Bandwidth

3. Mid-band gain

4. Input/Output impedance


Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1

Circuit Diagram

Design

Given: VCC

= 15 V; IC = 1 mA; A

V = 50; f

L = 500 Hz; Stability factor = [2–10].

Gain formula is given by,

ie

LefffeV

h

RhA

−

=

Assume, 10

;condition)(Active2

CCE

CCCE

VV

VV ==

Effective load resistance is given by RLeff

= RC || R

L

Internal emitter resistance is given by E

eI

rmV26

=

hie

= βre

where re is internal emitter resistance of the transistor.

hie

= hfe

re

On applying KVL to output loop, we get

VCC

= IC

RC + V

CE + I

E R

E

where VE = I

E R

E

RC = ?


The emitter current is given by the equation IE = I

B + I

C

Since IB is very small when compared with I

C,

?==

≈

E

EE

EC

I

VR

II

The voltage at the base of the transistor is given by

VB = V

BE + V

E

From voltage divider rule, the voltage at the base of the transistor is given by

21

2

BB

BCCB

RR

RVV

+

= (i)

The equation for stability factor is given by

E

B

R

RS += 1

Find RB

RB = R

B1 || R

B2(ii)

From equations (i) and (ii), solve for RB1

, and RB2

Input coupling capacitor is given by,

( )

?

2

1

10

||

=

=

=

i

iCi

BieCi

C

CfX

RhX

π

Output coupling capacitor is given by

?

2

1

10

||

0

00

0

=

=

=

C

CfX

RRX

C

LCC

π

By-pass capacitor is given by,10

ECE

RX

′

=

where, ( )

+=′

fe

ieBEE

h

hRRR ||

?

2

1

=

=

E

E

CE

C

CfX

π


Procedure


2. Set VS = 50 mV (say) using the signal generator.

3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular steps of 10 and note

down the corresponding output voltage.

4. Plot the frequency response: Gain (dB) vs Frequency (Hz).

5. Find the input and output impedance.

6. Calculate the bandwidth from the graph.

7. Note down the phase angle, bandwidth, input and output impedance.

Tabular Column

Vi = 50 mV

Frequency V0 (volts) Gain = V0/Vi Gain (dB) = 20 log(V0/Vi)

Model Graph: (Frequency Response)

Result


Input impedance

Output impedance

Gain(Mid-band)

Bandwidth

Experiment 3.2

Two Stage RC – Coupled Amplifier

Aim To design and test a two stage RC coupled amplifier circuit and to find:

1. Bandwidth

2. Mid-band gain

3. Input / Output impedance


Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1

Circuit Diagram

Design

Given data: AV2

=10; AV1

= 20; fL

= 50 Hz; IE2

= 1.2 mA; IE1

= 1.5 mA; VCC

= 12 V

2

22

ie

LefffeV

h

RhA

−

=

RLeff

= R2 || R

L

hfe2

= 200 (from multimeter)

re2

= 26 × 10–3/ IE2

= ?

hie2

= hfe2

re2

From DC bias analysis, on applying Kirchhoff’s voltage law to the output loop, we get

VCC

= IC2

RC2

+ VCE2

+ VE2

VCE2

= VCC

/2; VE2

= VCC

/10;

Since IB2

is very small when compared with IC2

IC2

≈ IE2

Find RC2

The equation for the voltage gain is given by

2

22

ie

Lefffev

h

RhA

−

=


Find, RL || R

C2 from above equation.

Since, RC2

is known, calculate RL

The emitter current is given by,

?==

=

E

EE

EEE

I

VR

RIV

The stability factor is given by

?

1

2

2

2

=

+=

B

E

B

R

R

RS

The base resistance of II stage is the parallel combination of biasing resistors R3 and R

4

RB2

= R3 || R

4(i)

From voltage divider rule, the voltage at the base of BJT is given by

43

42

RR

RVV CCB

+

= (ii)

The base voltage of BJT is sum of voltage drop across base-emitter and emitter voltage, which is given by

VB2

= VBE2

+ VE2

on solving (i) and (ii),

R3 = ?

Therefore, find R4.

Zi2

= hie2

|| RB2

Zi2

= ?

RLeff1

= Zi2

|| RC1

Find RLeff1

from the gain formula given above

?

1

111

=

−

=

Leff

ie

Lefffe

v

R

h

RhA

On applying KVL to the first stage, we get

VCC

= IC1

RC1

+ VCE1

+ VE1

Since IC1

≈ IE1

RC1

= ?

The emitter resistance, 1

11

E

EE

I

VR =

RE1

= ?

The equation for stability is given by,

?

1

1

1

1

=

+=

B

E

B

R

R

RS


The base resistance of I stage is parallel combination of biasing resistors R1 and R

2

RB1

= R1 || R

2(iii)

From voltage divider rule, the base voltage is given by

21

21

RR

RVV CCB

+

= (iv)

The base voltage is sum of VBE

drop and emitter resistor drop, which is given by

VB1

= VBE2

+ VE2

on solving (iii) and (iv),

Find R1

Therefore, find R2.

Gain (including source resistance) is given by,

?

|| 111

1

1

=

=

+

=

VS

Biei

Si

iVIVS

A

RhZ

RR

RAA

Total gain including source resistance is given by,

AVT

= AVS

× AV2

The input coupling capacitor can be obtained from

( )

?

2

1

10

|| 11

=

=

=

i

iCi

BieCi

C

fCX

RhX

π

The output coupling capacitor can be obtained from

?

2

1

10

||

0

0

2

=

=

=

C

fCX

RRX

CO

LeffCCO

π

The by-pass capacitor can be obtained from

?

2

1

||where

10

2

2

2

2222

22

=

=

+=′

′

=

E

ECE

fe

ieBEE

ECE

C

fCX

h

hRRR

RX

π

Similar calculation can be incorporated to find the value of CE1


Procedure


2. Set Vi = 50 mV (say), using the signal generator.

3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular steps and note down

the corresponding output voltage.

4. Plot the graph: Gain (dB) vs Frequency (Hz).

5. Find the input and output impedance


7. Note down the phase angle, bandwidth, input and output.

Tabular Column

Vi = 50 mV


Model Graph (Frequency Response)

Result


Input impedance

Output impedance

Gain (Mid-band)

Bandwidth

Experiment 3.3

Emitter Follower (Common Collector Amplifier)

Aim To design and test a common collector current amplifier and to find the following parameters:

1. Current gain

2. Voltage gain


3. Bandwidth

4. Input and output impedance

Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1

Circuit Diagram

Design

Given: VCC

= 12 V; fL

= 50 Hz; IE = 1 mA; S = [1–10]; β = h

fe

efeie

E

e

rhh

Ir

=

=mV26

where re is internal resistance of the transistor.

The voltage gain is given by,

eE

EV

rR

RA

+

=≤ 1

The current gain is given by,

eE

EfeI

rR

RhA

+

=


VCC

= VCE

+ VE; V

CE = V

CC/2

VE = I

E R

E

RE = ?


The stability is given by,

E

B

R

RS += 1

RB

= ?

The base resistance is the parallel combination of biasing resistors R1 and R

2

RB = R

1 || R

2(i)

From voltage divider rule, the base voltage is given by,

21

2

RR

RVV CCB

+

= (ii)

The base voltage is equal to sum of VBE

drop and emitter resistance drop, which is given by

VB = V

BE + V

E

on solving (i) and (ii).

Find R2

Therefore, R1 = ?

( )

( )

?

2

1

10

?

2

1

10

?

1

||||

||

?

)1()(

0

0

0

=

=

=

=

=

=

=

+

+=

=

=

++=

E

E

CE

CE

i

i

Ci

ieff

Ci

eff

fe

ieBSE

BBiLeff

feEiei

C

CfX

ZX

C

CfX

ZX

Z

h

hRRRZ

RZZ

Z

hRhZ

π

π

Procedure


2. Set Vi = 1 V (say), using the signal generator.








Tabular Column

Vi = 1V



Result


Input impedance

Output impedance

Gain (Mid-band)

Bandwidth

Experiment 3.4

Darlington Pair (Common Collector Amplifier)

Aim To design and test a Darlington current amplifier and to find the following parameters:

1. Current gain

2. Voltage gain

3. Bandwidth


Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1


Circuit Diagram

Design

Given: VCC

= 12 V; fL = 50 Hz; I

E = 1 mA; S = [1–10]; h

fe1 = h

fe2

AV

≤ 1, AI = A

I1 ×

A

I2

Since hfe1

= h

fe2; A

I = (h

fe)2


VCC

= VCE

+ VE; V

CE=V

CC/2

VE = I

E R

E

RE = ?

The stability factor is given by,

E

B

R

RS += 1

RB

= ?

The base resistance is the parallel combination of biasing resistors R1 and R

2, which is given by

RB = R

1 || R

2(i)

The base voltage can be calculated by applying the voltage divider rule to base, which is given by

21

2

RR

RVV CCB

+

= (ii)

The base voltage is the sum of VBE

drop and emitter resistance drop, which is given by

VB = V

BE + V

E

on solving (i) and (ii),

R2 = ?


Therefore, find R1

Zi = (h

fe1 × h

fe1) R

E

Zi = ?

Zieff

= Zi || R

BB

( )

( )

+

+=

201

2||||

fe

ieBSE

h

hRRRZ

Z0eff

= ?

i

Ci

ieff

Ci

fCX

ZX

π2

1

10

=

=

Ci = ?

ECE

CE

fCX

ZX

π2

1

10

0

=

=

CE = ?

Procedure


2. Set Vi = 1 V (say), using the signal generator.







Tabular Column

Vi = 1 V

Frequency V0 (volts) Gain = V0/Vi Gain (dB) = 200 log (V0/Vi)



Result


Input impedance

Output impedance

Gain (Mid-band)

Bandwidth

Experiment 3.5

Cascode Amplifier

Aim To design and test the cascode amplifier for the given specification and find the following parameters:

1. Mid-band gain


Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1


Circuit Diagram

Design

Given VCC

= 15 V; IE1

= IE2

= 1 mA; AV = 100; f

L = 50 Hz; R

L = 4.7 kΩ; h

fe1 = h

fe2, Stability factor = [2–10]

Assume, VCE1

= VCC

/3 (transistor Active); VCE2

= VCC/3

Effective load resistance is given by, RLeff

= RC || R

L

Emitter resistance is given by, E

eI

rmV26

=

hie1

= β1 r

e1

Since β1 = β

2; I

E1 = I

E2;

re1

= re2

Gain is given by AV1

= V01

/Vi ≈ –R

L / r

e1

With RL = r

e2 = h

ib2 of transistor-2 and A

V1 = – r

e2 / r

e1 = –1

AV2

= RLeff

/ re2

= ?

Total gain is given by,

AV1

AV2

= 100 (given)

RLeff

= AV2

re2

.

Calculate RC from R

Leff = R

C || R

L.

On applying KVL to output loop, we get

VCC

= IC

RC

+ VCE2

+ VCE1

+ IER

E

where, VE = I

E R

E

RE = ?


then 2

22

1

11

1

;

mA1Let

fe

CB

fe

CB

h

II

h

II

I

==

=

?

?

?

1

11

223

112

=−

=

=−=

=−=

I

VVR

III

III

BCC

B

B

ECEBEB VVVV ++= 121where

?2

212 =

−=

I

VVR BB

EBEB VVV += 22where

?3

23 ==

I

VR B

Input coupling capacitor is given by,

iCi

ieC

fCX

RRhX

π2

1

10

|||| 3222

=

=

Ci = ?

Output coupling capacitor is given by,

?

2

1

10

||

0

00

0

=

=

=

C

fCX

RRX

C

LCC

π

By-pass capacitor is given by, XCE

= RE/10

?

2

1

=

=

E

E

CE

C

fCX

π

Procedure










Tabular Column

Vi = 50 mV

Frequency V0 (volts) Gain = V0/Vi Gain (dB) = 20 log (V0/Vi)


Result


Input impedance

Output impedance

Gain (Mid-band)

Bandwidth

Experiment 3.6

Field Effect Transistor

Aim To determine the parameters of the single-stage JFET amplifier (common-drain amplifier)

1. Bandwidth

2. Midband gain


Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1


Circuit Diagram

Design

Given IDSS

= 10 mA; VP

= –4V; fL

= 50 Hz; VDD

= 12 V

From the DC bias condition,

?2

==DSS

D

II

For which ID

= IDSS

[1 – (VGS

/VP)]2

VGS

= ?

VD

= 2

DSSV (Assume)

Therefore, VDD

= ID

RD

+ VD

RD

= (VDD

– VD

) / ID

= ?

?||

20 ==

P

DDm

V

Ig

The value of gm

at the bias voltage is given by

gm

= gm0

[1–(VGS

/VP)]

Find gm

rm

= 1/ gm

rm

= ?

With RS completely by-passed, the largest amplifier gain is given by

AV = – R

D / r

m

AV = ?

RS = V

GS/ I

D = ?

RG1

= open and RGS

= 100 MΩ


Input coupling capacitor is given by

?

2

1

10

=

=

=

i

iCi

GSCi

C

fCX

RX

π

Output coupling capacitor is given by

?

2

1

10

||

0

00

0

=

=

=

C

fCX

RRX

C

LDC

π

By-pass capacitor is given by

?

2

1

10

=

=

=

S

SCS

SCS

C

fCX

RX

π

Procedure








7. Note down the phase angle, Bandwidth, input and output impedance.

Tabular Column

Vi = 50 mV




Result


Input impedance

Output impedance

Gain (Mid-band)

Bandwidth

Experiment 3.7

Differential Amplifier

Aim To construct a differential amplifier for dual input balanced output and unbalanced output in the common

mode and differential mode configuration and to study the output waveform and find common-mode rejection

ratio (CMRR).

Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1

Circuit Diagram

Dual Input Unbalanced Output

Design Dual input unbalanced output differential amplifier

Given mA;2.1);multimeterfrom(;1.0;150 === EfeCd IhAA differential gain is given by,


e

Cd

r

RA

2=

where E

eI

rmV26

=

RC = ?

Common-mode Rejection Ratio is given by,

C

d

A

ACMRR =

Common-mode gain is given by,

Ee

CC

Rr

RA

2+

=

RE = ?

Dual Input Balanced Output

Design Dual input balanced output differential amplifier

Given mA2.1);multimeterfrom(;1.0;150 === EfeCd IhAA

Differential gain is given by

e

Cd

r

RA

2=

where E

eI

rmV26

=

RC = ?

Common-mode Rejection Ratio is given by,

C

d

A

ACMRR =

Common-mode gain is given by


Ee

CC

Rr

RA

2

2

+

=

RE = ?

Procedure

1. Connect the circuit as per the circuit diagram (Common-mode configuration).








Tabular Column

Vi = 50 mV



Result


Input impedance

Output impedance

Gain (Mid-band)

Bandwidth


Experiment 3.8

Class-A Power Amplifier: Resistive Load

Aim To calculate efficiency of a class-A power amplifier operated with resistive load.

Equipment Required


DC power supply

Function generator

CRO

Ammeter

(0–30) MHz

(0–1) MHz

(0–20) MHz

(0–30) mA

1

1

1

1

Components Required


BJT (Power series)

Resistor

Capacitor

SL100

47 kΩ(pot)

220Ω

33 kΩ

47µF

1

1

2

1

2

Circuit Diagram


Design

mW500;220Given =Ω= oL PR

L

CCo

R

VP

8by,givenispowerOutput

2

=

?2

?

==

=

CCCE

CC

VV

V

loopoutputtoKVLApply

?=−

=

+=

C

CECCC

CECCCE

R

VVI

VRIV

by,givenispowerCollector

?== CCCCC IVP

Maximum output power is given by

L

oo

R

VP

2

max, =

Note: Maximum output voltage can be obtained from the experiment result.

?,Efficiencymax,

==

c

o

P

Pη

circuit.theofimpedanceinput

where2

=

=

i

i

iin

Z

Z

VP

Procedure


2. Set the function generator (say 0.2 V, at 1 KHz).

3. Vary the frequency from 10 Hz to 1 MHz in a regular steps and note down the corresponding output

voltage.

4. Calculate the gain (dB) = 20log10

(Vo/V

i)

5. Plot the graph : Gain (dB) vs Frequency (Hz)

: V0 (volts) vs Frequency (Hz)

Tabular Column

Frequency (Hz) Output voltage (Volts) Gain = Vo/Vi Gain (dB) = 20 log (Vo/Vi)


Model Graph

Experiment 3.9

Class-A Power Amplifier: Inductive Load

Aim To design and construct a class-A power amplifier and to determine its efficiency

Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1

Circuit Diagram


Design

Given P0max

= 0.4 W; RL

= 470 Ω; fL = 50 Hz

For a DC, since there is no drop across L, VCE

= VCC

(neglecting ammeter drop)

Current across emitter and collector = ICQ

+ IC sin ωt

Therefore, VC = (–I

C sin ωt)R

L + V

CC

At maximum ICQ,

VC = 0V; ωt = π/2;

ICQ

= VCC

/RL

Output power is given by

P0max

= I2CQ

RL/2 = V2

CC/2R

L

VCC

= ?

Since collector current is given by

ICQ

= VCC

/RL

ICQ

= ?

)(

max,efficiency

DCin

o

P

P=η

L

CCDCin

L

CCo

R

VP

R

VP

2

)(

2

max ;2

where ==

in

o

P

P=gainPower

ie

in

i

inin

Lo

h

V

Z

VP

R

VP

2220 ;where ===

Ceefeie

Irrhh

mV26; ==

Input coupling capacitor is given by

XCi

= hie

/10

iCi

fCX

π2

1=

Ci = ?

Output coupling capacitor is given by, XC0

= RL/10

00

2

1

fCXC

π

=

C0 = ?

Choose a transistor satisfying the following specifications:

PD max

= 2 P0 max

VCE

= 2 VCC

IC max

= 2 ICQ


Procedure



3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in regular steps and note down


4. Plot the graph: Gain (dB) vs Frequency (Hz)



7. Note down the phase angle, Bandwidth, input and output impedance.

8. Calculate the efficiency, η = P0/P

in

9. Plot the graph; Output power vs load resistance.

Tabular Column

Vi = 50 mV

Frequency V0 (volts) Gain = V0/Vi Gain (dB) = 20 log (V0/Vi) ηηηη


Result


Input impedance

Output impedance

Gain (Mid-band)

Bandwidth

Tabular Column

Vi = 50mV

Output power (watt)

(P0)

Load resistance

(RL)


Load Characteristic

Experiment 3.10

Class-A Power Amplifier—Inductive Load

Aim To calculate efficiency of class -A power amplifier with inductive load and hence determine maximum

efficiency.

Equipment Required


CRO

Signal generator

Power supply

DC Ammeter

(0–20) M Hz

(0–1) MHz

(0–30) V

(0–30) mA

1

1

1

1

Components Required


BJT (Power series)

Inductor

Resistor

Capacitor

SL100

1H

47 kΩ (pot)

220 Ω

47µF

1

1

2

1

2


Circuit Diagram

Design

Given PL, max

= 500mW; RL = 200 Ω

Output power is given by;

L

cco

R

VP

2

2

=

?

?

==

=

L

ccc

cc

R

VI

V

Collector power is given by,

cccc IVP =

Maximum output power is given by,

oP

Maximum output voltage can be obtained from the tabulation

input power is given by,

i

inin

Z

VP

2

=

where Zi = input impedance of the circuit

efficiency is given by ?==

c

oP

Pη

power given = ?=

in

o

P

P


Procedure


2. Set the signal (say 0.2V at 1 kHz) using function generator.

3. Vary the frequency from 0 to 1 MHz at regular steps and note down the respective output voltage.

4. Calculate gain (dB) = 20 log10

(Vo/V

i)

5. Plot the graphs: Gain(dB) vs Frequency (Hz)

Tabular Column

Frequency (Hz) Output voltage (Volts) Gain = Vo/Vi Gain (dB)

Model Graph

Experiment 3.11

Class-A Power Amplifier with Transformer Coupled Load

Aim To calculate efficiency of class - A power amplifier with transformer coupled load and also obtain the

power gain.

Equipment Required


CRO

Function generator

Power supply

DC Ammeter

(0–20) MHz

(0–1) MHz

(0–30) V

(0–30) mA

1

1

1

1


Components Required


Transformer

BJT (Power series)

Resistor

Capacitor

N:1

SL100

47 kΩ(pot)

220 Ω

47µF

1

1

1

2

1

Circuit Diagram

Design

Given VCC

= 15V; RC = 220 Ω

12

1 Nx

N

N==

Therefore LL RxR

2=′

Collector power is given by,

?2

=

′

=

L

CCc

R

VP

Maximum output power is given by

?2

2

max, =

′

=

L

oo

R

VP

Input power is given by,

i

inin

Z

VP

2

=

where Zi = input impedance of the circuit

power efficiency,


?==

c

o

P

Pη

Power gain is given by, ?==

in

o

P

P

Procedure


2. Set the signal (say 0.2V at 1kHz) using function generator.

3. Vary the frequency of the function generator from 0 to 1MHz and notedown the corresponding output

voltage.


Tabular Column

Vi = 0.2V

Frequency (Hz) Output voltage (Volts) Gain = Vo/Vi Gain(dB)

Model Graph

Experiment 3.12

Class-B Power Amplifier

Aim To design and construct a class-B (complementary symmetry) power amplifier and to determine its

efficiency

Equipment Required


Power supply

CRO

Function generator

(0–30) V

(0–20) MHz

(0–1) MHz

1

1

1


Circuit Diagram

Design

Given VCC

= 15 V; RL

= 470 Ω; fL = 50 Hz

Output voltage is same as the input voltage since two transistors is in CC-mode. Therefore, load voltage

is given by

VL

(ac) = 15 V

Output power, P0 (ac) = V2

L (ac) /2R

L = ?

IL(ac) = V

L(ac)/R

L = ?

The DC current is given by,

?π

II

L(ac)

dc ==

2

Therefore, the power supplied to the circuit is

Pi (dc) = V

CC Idc

= ?

Circuit efficiency, η = P0 (ac)/ P

i (dc) = ?

Power dissipation by each transistor is given by

PQ

= [P0(ac) – P

i (dc)]/2 = ?

At DC biasing condition:

VCE1

= VCE2

= VCC

/2 = ?

VB1

= VBE1

+ VCE2

= ?

R1 = [V

CC – V

B1]/I

1

If I1is assumed (say 5 mA), find R

1 =?

R2(V

CC/2)/(R

1 + R

2) =V

CC/2 + V

BE2

R1 = ?


RB1

= (S–1) RE1

= ?

RB1

= R1 || R

2

find R1 and R

2

Input impedance is given by

Zi1

= RB1

|| [hie1

+ (1 + hfe1

) Rf1

]

Output impedance is given by

Zo1

= RC1

The feedback factor β is given by

21

1

ff

f

RR

R

+

=β

where, Rf2

>> Rf1

assume Rf2

= 10 kΩ; find Rf1

overall voltage gain is given by

21 VVV AAA ×=

Parameter Analysis with Feedback

The desensitive factor, D = 1 + βAV

Output impedance with feedback is given by

D

ZZ o

of2

=

Input impedance with feedback is given by

DZZ iif ×= 1

The gain with feedback is given by

D

AA V

Vf =

The output capacitor is given by

10

20

oC

ZX =

where 0

02

1

fCXC

π

=

C0 = ?

The input capacitor is given by,

10

1iCi

ZX =

where Ci

Cif

Xπ2

1=

Ci = ?

OP-AMP × 4.1

C h a p t e r 4

OPERATIONAL AMPLIFIER (OP-AMP)

Experiment 4.1

Characteristics of OP-AMP

Aim To determine the following characteristics of an op-amp:

1. Input off-set voltage

2. Slew rate

3. Common mode rejection ratio

4. Bandwidth

5. Input bias current

Equipment Required


Signal generator

CRO

Regulated power supply

Dual power supply

(0–1) MHz

(0–20) MHz

(0–30) V

(12–0–12) V

1

1

1

1

Procedure

Input Off-Set Voltage



2. Switch on the dual power supply and note down the output voltage from the CRO.

3. Calculate the input offset voltage from the given formula,

+

=

12

10

RR

RVV

Slew Rate


2. Give a sinusoidal input of 1 Vpp

.

3. Switch on the dual power supply.

4. Vary the input frequency and observe the output.

5. Note down the value of the input frequency at which the output gets distorted.

6. Determine the slew rate from the given formula,

Slew Rate sVf m

µπ

/V10

26−

=

7. Repeat the above procedure by giving square wave input.

8. Increase the frequency till the output becomes a triangular wave.

9. Find the slew rate from the given formula,

t

V

∆

∆=

0SR

Common Mode Rejection Ratio



.


OP-AMP × 4.3

4. Note down the output voltage from the CRO.

5. Determine the CMRR by the following procedure.

Common Mode Gain = 1

0

V

VAC =

Differential Mode Gain = 1

2

R

RAd =

CMRR = 20 log

C

d

A

A

Bandwidth



.


4. Increase the frequency until the output voltage reduces to 0.7 times the input voltage.

5. Note down the frequency at this point and this gives the bandwidth of the op-amp at unity gain.

Input Bias Current

Inverting Mode Non-inverting Mode



3. Note down the output voltage from the CRO.


4. Calculate the input bias current in the inverting mode from the following formula,

R

VI 0

0 =−

5. Repeat the above procedure in the non-inverting mode and calculate the current from the following

formula,

R

VI 0

0 =+

Result

The characteristics of the op-amp were studied and the results are tabulated below,

Parameters Readings

Input off-set voltage

Slew rate

CMRR

Bandwidth

Input bias current – Inverting

– Non–inverting

Exercise

1. Discuss any two methods of measuring the input off-set voltage.

2. How is frequency compensation done in an op-amp ?

3. Define CMRR, PSRR and the maximum output voltage swing of an op-amp.

Experiment 4.2

Linear Applications of OP-AMP

Aim To study the following applications of op-amp using ICLM 741.

1. Voltage Follower.

2. Inverting Amplifier.

3. Non-inverting Amplifier.

4. Variable Voltage Gain Amplifier.

5. Adder.

6. Subtractor.

7. Differential Amplifier.

8. Integrator.

9. Differentiator.

OP-AMP × 4.5

Equipment Required


Dual power supply

Signal generator


CRO

(15–0–15) V

(1 Hz – 1 MHz)

(0–30) V

(0–100) KHz

1

1

2

1

Voltage Follower

Inverting Amplifier

Non-inverting Amplifier

Adder


Subtractor

Differentiator

Integrator

Differential Amplifier

OP-AMP × 4.7

Procedure

1. Connect the circuit as shown in the circuit diagram.

2. Give the input signal as specified.


4. Note down the outputs from the CRO.

5. Draw the necessary waveforms on the graph sheet.

6. Repeat the procedure for all the circuits.

Result

The applications of the LM1 741 were studied.

Exercise

1. Explain the difference between differentiators and integrators and give one application for each.

2. Explain why integrators are preferred over differentiators in an analog computer.

3. Draw a practical differentiator circuit that overcomes the drawbacks of an ordinary differentiator circuit.

4. Design an adder circuit to get the following output

[ ]3210 1010 VVV.V ++−=

Experiment 4.3

Non-linear Applications: Comparators

Aim To design a comparator circuit and to study the non-linear applications of op-amp.

Equipment Required


Dual power supply

Signal generator


CRO

(15–0–15) V

(0–1)M Hz

(0–30) V

(0–20) MHz

1

1

1

1

Circuit Diagram

Comparator: Zero Crossing Detector

0when,

0when,

sat0

sat0

>−=

<+=

i

i

VVV

VVV


Positive Comparator

refi

refi

VVVV

VVVV

>−=

<+=

when,

when,

sat0

sat0

Negative Comparator

refi

refi

VVVV

VVVV

>−=

<+=

when,

when,

sat0

sat0

Comparator with zener diode at the output

Zero crossing comparator (non-inverting mode)

Negative non-inverting comparator

OP-AMP × 4.9

Positive non-inverting comparator

Procedure

Comparator


2. Give a sinusoidal input of 4 VPP

to the inverting terminal.

3. For a zero crossing detector, connect the non-inverting terminal to ground.


5. Observe the output waveform on a CRO.

6. For a positive and negative comparator give a reference voltage of ±1VDC respectively to the non-

inverting input.

7. Observe the output waveform on a CRO.

8. Draw the output and input waveforms for all the three circuits on a graph sheet.

Result

Using op-amps the comparator were studied and waveforms were verified.

Experiment 4.4

Pulse Detector and Window Comparator

Aim To study the operation of a

1. Pulse Detector

2. Window comparator

Equipment Required


Signal generator

CRO

Dual power supply

(0–1) MHz

(0–20) MHz

(12-0-12) V

1

1

1


Circuit Diagram

Pulse Detector

Window Comparator

Procedure


2. Setup the input signal from the signal generator.

3. Observe the input of the squarewave, the differentiated output and then pulses of the diode in the case of

pulse detector

4. Set the voltages accordingly and observe the LED glow (for ckt (2)).

5. Plot the graph for the pulse detector (for ckt (1))

1. Comparator output

2. Differentiator output

3. Pulse output (also with diode reversed)

Tabular Column (Window Comparator)

Input Voltage (Vi) LED 1 LED 2 LED 3

Vi < 5V

5V < VI < 10 V

Vi > 10 V

ON

OFF

OFF

OFF

ON

OFF

OFF

OFF

ON

OP-AMP × 4.11

Result

The operation of pulse detector and window comparator were studied.

Experiment 4.5

Instrumentation Amplifier

Aim To study the performance of an instrumentation amplifier.

Equipment Required


Signal generator

CRO

Dual power supply

(0–1) MHz

(0–20) MHz

(12–0–12) V

1

1

1

Circuit Diagram

′

==

R

R

R

RA

21Gain,

1

2

Procedure


2. Set the inputs E1 and E

2 at different values but at the same frequency.

3. Adjust R1 to a particular value.


5. Calculate the theoretical gain from the given formula and verify with the practical values.

6. Repeat the above procedure for different values of R1.


Experiment 4.6

Non-linear Applications: Waveform Generators

Aim To design a circuit and study the non-linear applications of op-amp.

1. Sine wave generator.

2. Square wave generator.

3. Triangular wave generator.

4. Sawtooth wave generator.

Equipment Required


Dual power supply

Signal generator


CRO

(15–0–15) V

(0–1) MHz

(0–30) V

(0–20) MHz

1

1

1

1

Circuit Diagram

Sinewave Generator

To produce sustained oscillation, gain should be equal to 3 i.e., ifi

fRR.

R

R2Then31 ==+

Square Wave Generator

OP-AMP × 4.13

Asymmetric square wave generator

Triangular Wave Generator


Sawtooth wave generator

Design

Sine Wave Generator

?

1001.0102/1

F01.0,Choose

2

1

kHz1,Let

2/1,knowWe

63

=

×××=

µ=

=

=

=

−π

π

π

R

C

fCR

f

RCf


Ω=

Ω=

=

Ω=

×××=

µ=

=

=

−

k6.11Then,

k10If,

16.1,Choose

k10

1005.0102/1

F05.0,Choose

kHz1,Let

2

1,knowWe

1

2

21

63

0

0

R

R

RR

R

R

C

f

RCf

π

Chose 10 k Ω in series with a 10 k

Ω

potentiometer.


Design for the square wave generator is given above. Design for the integrator circuit as follows,

If,

Let,

R

R

OP-AMP × 4.15

?

1001.0101002/1Then,

F01.0Choose,

,100Given,

2

1

M1Then,

630

2

3

230

4

=

××××=

µ=

Ω=

=

Ω=

−π

π

f

C

kR

CRf

R

Procedure

Sine Wave Generator


2. Switch on the dual power supply and observe the output waveform on a CRO.

3. Adjust the potentiometer to get an undistorted waveform.

4. Calculate the time period and determine the frequency.

5. Verify it with the theoretical frequency calculated by using the formula,

f =1 / 2π RC

Repeat the above procedure for different values of R and C.



2. Switch on the dual power supply and observe the output on a CRO.

3. Adjust the potentiometer to obtain an undistorted output.

4. Calculate the output frequency and verify it with the theoretical frequency obtained from the formula,

RCf

π2

1=


1. Connect the output of the square wave generator to an integrator circuit.

2. Observe the output waveform on a CRO and determine the frequency.

Sawtooth Wave Generator

1. Connect the circuit as shown in the

2. Adjust the potentiometer and observe the circuit diagram output for applied negative voltage.

3. Adjust the potentiometer in the opposite direction and observe the output for applied positive voltage.

Result

The non-linear applications of the op-amp were studied.

Exercise

1. Design a circuit to convert a square wave into a series of positive pulses.

2. What is a window detector?

3. What is the difference between a sawtooth wave and a triangular wave?

4. How do you recognize that positive feedback is being used in an op-amp oscillator circuit ?


Experiment 4.7

Schmitt Trigger

Aim To design and test the schmitt trigger for the given UTP and LTP.

Equipment Required


Signal generator

CRO

Dual Power supply

(0–1) MHz

(0–20) MHz

(12–0–12) V

1

1

1

Circuit Diagram

Schmitt trigger with zero-reference

Schmitt trigger with positive reference

OP-AMP × 4.17

Schmitt trigger with negative reference

Design

Given, VR = 0 and ± V

sat =

±

12 V.

Assume, Vb1

= Vb2

+

==

+

+==

21

SAT12

21

SAT11

RR

-VRLTPV

RR

VRUTPV

b

b

Procedure


2. Set input signal (say 1V, 1kHz) using signal generator.

3. Observe the input and output waveforms on the CRO

4. Plot the graphs: Vi vs Time

V0

vs Time

Model Graph


Result

Parameter Theoretical Practical

Experiment 4.8

Precision Rectifier

Aim To design a precision rectifier and study its operation using IC 741.

Equipment Required


Dual power supply

Signal generator

CRO

(15–0–15) V

1 MHz

15 MHz

1

1

1

Circuit Diagram: Half-wave rectifier

+

−

+

+

211

211

RR

VRLTP

RR

VRUTP

Sat

Sat

OP-AMP × 4.19

Full-wave rectifier

Procedure


2. Give a sinusoidal input of Vpp

, 1 kHz from a signal generator.

3. Switch on the dual power supply and note down the output from the CRO.

4. Repeat the above procedure by reversing the diodes.

Result

The operation of the precision rectifier is studied using IC 741.

Exercise

1. What is virtual ground?

2. What is the significance of a precision rectifier ?

3. Explain the operation of a precision full wave rectifier.

Experiment 4.9

Study of V-I & I-V Converter Using OP-AMP

Aim To design a voltage to current (V/I) and current to voltage converter (I/V) and study their operation using

IC 741.

Equipment Required


Dual power supply


Signal generator

CRO

Ammeter

(15–0–15) V

(0–30) V

(0–1) MHz

(0–15) MHz

(0–30) µ A

1

1

1

1

1


Circuit Diagram

Voltage to Current Converter

Current to Voltage Converter

Procedure

Voltage to Current Converter


2. Set the ac input to any desired value.

3. Switch on the dual power supply and note down the reading from an ammeter.

4. Repeat the above procedure for varying input voltages.

5. Tabulate the readings in the given tabular column.

Current to Voltage Converter


2. Connect the dc bulb to a regulated power supply and give a dc voltage less than 6V to it.

3. Focus the dc bulb on the photo-diode.

4. Switch on the dual power supply and note down the voltage at the output.

5. Vary the regulated power supply voltage so that it would vary the intensity of the bulb.

6. Measure the diode current and the corresponding output voltage.

7. Tabulate the readings in the given tabular column.

Digital Electronics × 5.1

C h a p t e r 5

DIGITAL ELECTRONICS

Digital signal consists of only 2 values, ‘0’ and ‘1’. These two values are logical, i.e. ‘1’ represents the existence

of a particular condition and ‘0’ represents the absence of that condition.

Boolean Algebra

It is a technique of mathematical manipulation, it uses two binary numbers, ‘0’ and ‘1’. There are several laws

in boolean algebra and are used in digital circuits.

Boolean Postulates

X = 0

X = 1

0 × 0 = 0

1 × 1 = 1

1 + 1 = 1

1 × 0 = 0 × 1 = 0

1 + 0 = 0 + 1 = 1

1 = 0 and 0 = 1

Theorems of Boolean Algebra

Boolean algebra deals with logical relations between the Boolean variables. A fundamental rule relating Boolean

variable is called a Boolean theorem. The following are some of the Boolean theorems,

1. Commutative law:

X + Y = Y + X

Its dual, X × Y = Y × X

2. Associative law:

(X + Y) + Z = X + (Y + Z)

Its dual, (X × Y) × Z = X × (Y × Z)

3. Distributive law:

X × (Y+Z) = X × Y + X × Z

Its dual, X + (Y × Z) = (X + Y) × (X + Z)

4. Negative law:

Complement of

XX

XX

=

=


5. Identity law: 8. 1 + X = 1

X + X = X Its dual, 0 × X = 0

Its dual, X × X = X

6. Redundance law: 9. 1XX =+

X + X × Y = X Its dual,

XX ×

Its dual, X × (X + Y) = X

7. 0 + X = X 10. YXYXX +=×+

Its dual, 1 × X = X Its dual, X ×

X

+ Y = X × Y

De Morgan’s Theorem

Statement: Complementary of the product is equal to sum of the complements and complement of the sum is

equal to product of the complements.

YX

YX

+

×

Both are dual of each other.

Realisation of Basic Gates Using Universal Gates

NOT equivalent of NAND GATE

AND equivalent of NAND GATE

OR equivalent of NAND GATE

NOR equivalent of NAND GATE


EX-OR equivalent of NAND GATE

EX-NOR equivalent of NAND GATE

NOT equivalent of NOR GATE

OR equivalent of NOR GATE

AND equivalent of NOR GATE

NOR equivalent of NOR GATE


EX-OR equivalent of NOR GATE

EX-NOR equivalent of NOR GATE

Experiment 5.1

Logic Gates

Aim To realise the logic gates using diodes and transistor.

Circuit Diagram


Procedure


2. Low level refers to 0 V; High level refers to +5 V.

3. Switch on the input according to the truth table condition.

4. Verify the output and compare it with truth table result.

5. Continue the above procedure for all other gates.

Truth Tables

OR GATE

Input

A

Input

B

Output

Y

LOW

HIGH

LOW

HIGH

LOW

LOW

HIGH

HIGH

LOW

HIGH

HIGH

HIGH

AND GATE

Input

A

Input

B

Output

Y

LOW

HIGH

LOW

HIGH

LOW

LOW

HIGH

HIGH

LOW

LOW

LOW

HIGH

NOT GATE

Input

A

Output

Y

LOW

HIGH

HIGH

LOW

NOR GATE

Input

A

Input

B

Output

Y

LOW

HIGH

LOW

HIGH

LOW

LOW

HIGH

HIGH

HIGH

LOW

LOW

LOW


NAND GATE

Input

A

Input

B

Output

Y

LOW

HIGH

LOW

HIGH

LOW

LOW

HIGH

HIGH

HIGH

HIGH

HIGH

LOW

EX-OR GATE

Input

A

Input

B

Output

Y

LOW

LOW

HIGH

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

HIGH

LOW

EX-NOR GATE

Input

A

Input

B

Output

Y

LOW

LOW

HIGH

HIGH

LOW

HIGH

LOW

HIGH

HIGH

LOW

LOW

HIGH

Experiment 5.2

Simplification of a Boolean Expression and

Its Realisation Using Logic Gates

Aim To simplify the given boolean expression and realise the resultant expression using

a) Basic gates

b) Universal gates

Equipment Required

Equipment Quantity

Digital IC trainer kit

Patch cords

1

20


Components Required

IC Name Quantity

IC 74LS00

IC 74LS02

IC 74LS04

IC 74LS08

IC 74LS32

1

1

1

1

1

Circuit Diagram

Sum of Products

ABCCBACBAY ++=

Logic Implementation Using “NAND” Gates


Logic Implementation Using “NOR” Gates

Product of sums

)()()( CBCABAY +++=

Logic Implementation Using Basic Gates

Logic Implementation Using “NOR” Gates


Logic Implementation Using NAND Gates

Procedure

1. Connect the circuit and pin configurations of the IC, as per the circuit diagram.

2. Switch on the supply and note down the outputs for all the possible combination of inputs.

3. Repeat the same using Universal gates.

E.g.

XZXY

]YY[XZXY

ZYXXYZXY

+

++

++

This equation can be realised using NAND gates. On converting equation into product of sum form, we

get ).ZX()YX( ++ This equation can be realised using NOR gates.

Observation and Tabulations

1

1

0

0

0

1

0

1

0

0

0

0

0

1

0

1

1

1

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

0

0

0

1

1

1

1

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

1

1

0

0

0

0

X ZXXYZXXYZZYX +


)ZX()YX( ++

0

0

1

1

1

0

1

0

1

1

1

1

1

0

1

0

0

0

1

1

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

1

1

0

0

0

0

Z)(X)YX(ZXYXYXZYX ++++

Result

The given boolean expressions were simplified and realised using logic gates.

Exercise

1. Write the logic, boolean expression and truth table of an EX-OR gate.

2. Realise the EX-OR gate using NOR gates.

3. Justify the statement UNIVERSAL gates.

Experiment 5.3

Adders

Aim To construct and verify the operation of a half-adder and a full-adder using logic gates.

Equipment Required

Equipment Quantity


Patch cords

1

20

Components Required

Name of the Component Quantity

IC 74LS08

IC 74LS32

IC 74LS86

1

1

1


Circuit Diagram

Using Basic Gates

Using NAND Gates

Using NOR Gates

Using EX-OR Gate


Full-adder

Block Diagram of Full-adder Using Two Half-adders

Procedure


2. Give logical inputs as per the respective truth table.

3. Observe the logical output and verify with your truth table.

Truth Table

Half-adder

A B Sum (S) Carry (CY)

0

0

1

1

0

1

0

1

0

1

1

0

0

0

0

1

Full-adder

A B C Sum (S) Carry (CY)

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1

Result

The operation of a half-adder and full-adder were studied.


Experiment 5.4

Subtractor

Aim To design of half-subtractor and full-subtractor.

Half-subtractor

Truth Table

X YBorrow

(B)

Output

(D)

0

0

1

1

0

1

0

1

0

1

0

0

0

0

1

0

YXB

YXYXYXD

=

⊕=+=

Using Basic Gates

Using NAND Gate

Using NOR Gate


Full-subtractor

Truth Table

A B CBorrow

(B)

Output

(D)

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

1

0

0

0

1

0

1

1

0

1

0

0

1

YZZXYXB

XYZXZYYZXZYXD

++=

+++=

Note: Try your circuit and implement it.

Procedure




Experiment 5.5

Parity Generation and Checking

Aim To design even parity generator and checker.

Equipment Required


Power supply (0–5) V 1

Even Parity Generator

Truth Table

X Y Z Parity Bit (P)

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1


ZYXXYZXZYYZXZYXP ⊕⊕=+++=

Even Parity Checker

Truth Table

X Y Z Parity (P) Parity Error Checker (C)

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

0

0

0

0

1

1

1

1

1

0

0

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

1

0

1

0

0

0

1

1

0

0

1

0

1

1

0

0

C = X ⊕ Y ⊕ Z ⊕ P

Procedure

1. Set up the circuit as per the circuit diagram.

2. Give logical inputs as per their respective truth table.

3. Observe the logical output and verify that with your truth table.


Experiment 5.6

Multiplexer

Aim To design and implement a 4:1 multiplexer using logic gates.

Equipment Required



Circuit Diagram

Truth Table

Input Output

X Y

0

0

1

1

0

1

0

1

D1

D2

D3

D4

Procedure




Exercise

Obtain EX-OR operation on a multiplexer.


Experiment 5.7

Demultiplexer

Aim To design and implement a 4:1 demultiplexer using logic gates.

Equipment Required



Circuit Diagram

Truth Table

Input Output

A B Y0 Y1 Y2 Y3

0

0

1

1

0

1

0

1

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1

Procedure





Experiment 5.8

Encoders

Aim To design and implement encoders using logic gates.

Equipment Required



Circuit Diagram

Truth Table

Inputs Outputs

D0 D1 D3 D4 X Y

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

1

1

0

1

0

1

Procedure




Exercise

1. Compare an encoder with a multiplexer.

2. Explain the operation of a priority encoder.

3. Design a decimal to BCD encoder using universal gates.

4. Conduct the decimal to BCD encoder using IC 74147.


Experiment 5.9

Decoders

Aim To design and implement decoders using logic gates.

Equipment Required



Circuit Diagram

Truth Table

Input Output

X Y D0 D1 D2 D3

0

0

1

1

0

1

0

1

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1

Decimal BCD Code 7-segment OP-code

D C B A a b c d e f g

0

1

2

3

4

5

6

7

8

9

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

1

1

1

0

0

1

1

1

1

1

0

1

1

1

1

1

1

1

1

0

1

1

0

1

1

0

1

0

1

0

1

0

0

0

1

0

1

0

1

0

0

0

1

1

1

0

1

1

0

0

1

1

1

1

1

0

1

1


Procedure


2. Give logical inputs as per their respective truth tables.


Exercise

1. Conduct the BCD to Decimal encoder using IC 7445.

2. Design a BCD to Excess-3 decoder using logic gates.

3. Compare a decoder and a demultiplexer.

4. Discuss the operation of a BCD/7 segment decoder.

5. Discuss about a strobe signal.

Note: Decoders permits one of the ‘n’ outputs to be selected, depending on the address on the select lines or

control lines. Any of the demultiplexers can be used as a binary decoder by providing a constant, continuous

‘1’ (or removing permanently the input signal channel) on the signal input line.

BCD To 7 Segment Display Decoder

This circuit facilitates the operation of 7 segment devices such as incandescent lamps, LED and LCD. The

output of the decoder is designed in such a way that segments of the corresponding decimal digit is enabled.

For example, consider the segments of the display i.e. ‘a’-‘g’. The segments other than g should glow if the

digit is 0. The inputs A, B, C, D will be 0 and the decoder outputs to the segments ‘a-f ’ should be high and to

the segment ‘g’ should be low for the digit 0 to glow. Similar analysis can be done for the other digits also as

given below.

DIGITAL LOGIC FAMILIES

Digital Integrated Circuits

In electronic digital circuits, 0 and 1 are always represented as low and high values. Many functions are being

preferred with these two inputs and are realised by using logic gates. A logic gate is an electronic circuit, which

can take in one or more inputs and give a single output. A logic circuit can be operated in two logics namely:

1. Positive logic

2. Negative logic

Positive logic In positive logic convention, logic 1 is assigned the more positive value of the two voltage

levels and logic 0 is assigned the less positive value.

Negative logic In this, logic 0 is assigned the more positive value and logic 1 is assigned the less positive

value. Digital ICs are circuits, which perform logic functions using these inputs. It is basically classified as

bipolar ICs and MOS ICs. The digital ICs are classified into different logic families depending on the components

and logic used. RTL, DTL, TTL, ECL, HTL, etc. are a few logic families commonly used.

CHARACTERISTICS OF DIGITAL ICs

1. Logic flexibility

2. Operating speed

3. Availability of complex functions

4. Power dissipation


5. Supply voltage

6. Noise immunity

7. Noise generation

8. Fan-in /Fan-out

9. Cost

10. Operating temperature range

Logic Flexibility

This is a measure of the utility of the IC in meeting the needs of the system.

Wired logic capability Connecting the gate output together or using them directly to perform additional

logic functions without any external hardware.

Complementary outputs If the IC has complementary output facility, then the requirement of extra inverters

can be avoided.

Driving non-standard loads Non-standard loads like long lines electromagnetic relays have to be driven

so that the need for the coupling elements can be avoided.

I/O facilities The number of inputs of the gate, the input impedance and the output impedance at both logic

0 and 1 determines the I/O capacity of the IC.

Ability to drive other logic forms This character avoids the necessity of external interfacing circuits and

hence reduces the space and system cost.

Types of gates The logic family should have many types so that when used in a system, interconnections

and power supply requirements can be simplified.

Operating Speed

The operating speed of an IC should be very high, as it reduces the operating and execution time. When high

speed ICs are available, then system can be designed to operate in the serial mode rather than in a parallel

mode, as this would reduce the system cost.

Speed of an IC is limited by the following factors

Propagation delay This is due to the finite operating speed of the active devices and RC time constants of

the associated circuitry. Since the delay from logic 1 to logic 0 is different from the delay of logic 0 to

logic 1, the average of both is taken as the propagation delay.

Pair delay This is a measure of the propagation delay through two inverters.

Complex Functions

Grouping of basic gates in a single packaged chip is termed as complexity of the IC. The chip size, number of

pins per gate and the overall number of input/output pins per package are important factors of consideration.

With increase in complexity, the number of input/output terminals for the IC increases but at a decreased rate,

and the reliability and assembling cost of the IC is increased.

Power Dissipation

This factor should be low as it reduces cooling, power supply and distribution cost. With decrease in power

dissipation of a gate f of the active device decreases and RC time constants increases. This increases the

propagation delay. Hence a decrease in power dissipation is achieved at the cost of increase in propagation

delay.


Supply Voltage

A standard supply voltage is used for every logic family. A +5 V supply is usually used.

Noise Immunity

An IC should have a high noise immunity. This is a characteristic term of noise voltage and pulse width that can

be tolerated by the circuit or the total noise energy required to cause a false output at the logic gate. This noise

immunity depends on the following factors.

Parameters of a gate are:

1. Supply voltage

2. Fan-in

3. Fan-out

4. Stray inductance

5. Stray capacitance

6. Source of noise

7. Shape of the noise source

To specify the noise immunity of an IC the following definitions are considered.

dc noise immunity This is specified in terms of noise margin. The dc noise margin is defined as the

difference between the guaranteed logic state voltage limits of a driving gate and the voltage requirements of

a driven gate.

ac noise immunity This considers the amplitude and pulse width of the noise signal. If the pulse width is

more, noise immunity is less. But if it is less than the propagation delay, the noise immunity is high.

Noise Generation

External noise Noise radiated into the system due to the make and break contacts, which are present near

the IC accounts for the external noise.

Power line noise This noise is generated due to ac or dc power distribution system.

Cross talk This is due to interference from adjacent signal lines.

Signal current noise Noise from unterminated or mismatched transmission lines.

Current Spikes There are many causes for this type of noise

1. Unequal currents drawn from the supply under logic 0 and 1 conditions.

2. Charging of load capacitor.

3. Conduction overlap at the output when going from one state to another. This noise is an internal noise

and hence can be reduced by suitable design.

Fan-in

This indicates how many input terminals are there for the gate. This depends on the number of diodes for DTL

logic and the number of emitters for TTL logic. Normally fan-in is less than or equal to 15.

Fan-out

This indicates how many gates it can drive. This is governed by the output and input currents of an IC at logic

0 and 1.


Fan-out = Iout

(1) (min)——————— for logic 1.

Iin

(1) (max)

Fan-out = Iout

(0) (min)——————— for logic 0.

Iin

(0) (max)

Cost

The overall cost of an IC depends on the fabrication technique, packing, shielding, etc.

Operating Temperature Range

The operating range of temperature of an IC should be very wide. In general it is as follows:

a) Consumer and Industrial applications: 0 to 700 C

b) Military and Space applications: –550 C to +1250 C.

BUILDING BLOCKS OF A DIGITAL SYSTEM

Digital systems are broadly classified as

1. Combinational system

2. Sequential system

Combinational system This is based on the combinational logic where the output of the system depends

only on the inputs at that instant e.g., Binary adders, Decoder, Multiplexer, PLA, etc.

Sequential system This is based on sequential logic where the output of the system depends not only on

the input but also on the previous outputs. e.g. Flip-flops, Counters, Shift Registers.

Experiment 5.10

Study of Flip-flop

Aim To study the operation of the following flip-flops and verify their truth tables.

1. SR Flip-flop

2. JK Flip-flop

3. D Flip-flop

4. T Flip-flop

Equipment Required

Equipment Quantity


Chords

1

20


Components Required

Components Quantity

IC 74LS00

IC 74LS02

IC 74LS73

IC 74LS74

1

1

1

1

Circuit Diagram

SR Flip-flop Using NOR and NAND Gates

JK Flip-flop

D Flip-flop and D-F/F (Using JK-F/F)

T Flip-flop (Using D-F/F and JK-F/F)

Procedure

1. Connect the IC as per the configuration.

2. Give the inputs as per the truth table and verify the outputs.

3. Verify for all the flip-flops and then realise the same using logic gates.


Truth Table

SR Flip-flop (Using NAND Gate)

Clock S R Qn+1

↑

↑

↑

↑

0

0

1

1

0

1

0

1

Unused

1

0

Qn

SR Flip-flop (Using NOR Gate)

Clock S R Qn+1

↑

↑

↑

↑

0

0

1

1

0

1

0

1

Qn

0

1

Not used

JK Flip-flop

Clock J K Qn+1

↑

↑

↑

↑

0

0

1

1

0

1

0

1

Qn+1

0

1

Toggle

D Flip-flop

Clock D Qn+1

↑

↑

0

1

0

1

T Flip-flop

Clock T Qn+1

↑

↑

0

1

1

0

Result

The operations of the flip-flops are studied and their truth tables are verified.

Exercises

1. Define race around condition.

2. Explain how race around condition is overcome in a master-slave flip-flop.

3. Realise T flip-flop using other flip-flops.


Experiment 5.11

Study of Shift Registers

Aim To construct and study the operation of a 4 bit shift register in the following modes

1. Serial in serial out

2. Serial in parallel out

3. Parallel in serial out

4. Parallel in parallel out

Equipment Required

Equipment Quantity


Patch chords

1

20

Components Required

Components Quantity

IC 74LS00

IC 74LS74

1

1

Circuit Diagram

Procedure

Serial Mode

1. Connect the circuit as per the circuit diagram and pin configuration of the ICs.

2. Clear all the flip-flops by applying a low signal to the clear input.

3. Feed the data into the serial input one bit per clock pulse.

4. Observe the output at Q1, if the output is taken serially.

5. Observe the output at Q1, Q

2, Q

3, Q

4, if the output is taken parallely.


Parallel In Parallel Out

1. Connect the circuit as per the diagram and pin configuration of the ICs.

2. Clear all the flip-flops by applying a low signal to the clear input.

3. Make the serial input low.

4. Enable the preset and clock by applying a high signal.

5. Feed in the data at P1, P

2, P

3, and P

4.

6. Observe the outputs at Q1, Q

2, Q

3, and Q

4.

Parallel In Serial Out

1. Repeat the above steps till step No.5.

2. Disable the present input by connecting it to a low signal.

3. Apply clock pulses to obtain data serially at Q1.

Tabular Column

Serial Mode

Mode of Operation Clock Serial Input Q3 Q2 Q1 Q0

Serial in serial out

Serial in parallel out

0

1

2

3

4

0

1

2

3

4

0

1

0

0

0

0

1

1

1

1

0

1

0

0

0

0

1

1

1

1

0

0

1

0

0

0

0

1

1

1

0

0

0

1

0

0

0

0

1

1

0

0

0

0

1

0

0

0

0

1

Parallel Mode

Mode of Operation Clock P3 P2 P1 P0 Q3 Q2 Q1 Q0

Parallel in serial out

Parallel in parallel out

0

1

2

3

4

5

0

1

2

3

0

1

0

0

0

0

0

1

1

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

1

1

1

0

1

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

1

0

0

1

1

0

0

0

1

1

1

0

1

1

1

1

0

0

1

0

0

Result

The operations of the shift registers are studied for all the modes of operation.

Exercise

1. Discuss about synchronous and asynchronous mode of operation.

2. What is a universal shift register? Explain its operation with a neat circuit.


Mod-4 Counter

Clock Q2 Q1

0

1

2

3

4

0

0

1

1

0

0

1

0

1

0

Mod-3 Counter

Clock Q2 Q1

0

1

2

3

0

0

1

0

0

1

0

0

Mod-5 Counter

Clock Q3 Q2 Q1

0

1

2

3

4

5

0

0

0

0

1

0

0

0

1

1

0

0

0

1

0

1

0

0


Mod-8 Counter

Clock Q3 Q2 Q1

0

1

2

3

4

5

6

7

8

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

Modulo-10 Counter Using Feedback


Mod-10 Counter

Clock Q4 Q3 Q2 Q1

0

1

2

3

4

5

6

7

8

9

10

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

1

1

1

1

0

0

0

0

0

1

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

1

0

1

0

Experiment 5.12

Asynchronous Counter

Aim To construct a binary and modulo-n asynchronous counter.

1. Binary counter (4-bit).

2. Modulo-11 counter.

Equipment Required




Circuit Diagram

Binary Counter

Modulo-11 Counter

Procedure


2. Connect the clock input.

3. Observe the output and verify it with its count sequence.

Design Concept

1. Take the (n+1)th state.

2. Observe the output that are at ‘1’ in the (n+1)th state.


3. Combine all those outputs in a NAND gate and give the output of the gate to clear the terminals of flip-

flops.

4. When the (n+1)th state arrives, the output of NAND gate will be zero (low), which will clear all flip-flops.

5. Hence instead of (n+1)th state, we get the first state (0000).

Count Sequence

Binary Counter Modulo-11

Clock Outputs

Q3 Q2 Q1 Q0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16 (0)

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Clock Outputs

Q3 Q2 Q1 Q0

0

1

2

3

4

5

6

7

8

9

10

11 (0)

0

0

0

0

0

0

0

0

1

1

1

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

0

1

1

0

0

1

0

0

1

0

1

0

1

0

1

0

1

0

0

Exercise

1. Design a mod-9 counter.

2. Design a mod-5 counter.

3. Design an up-down counter.

SYNCHRONOUS COUNTERS

Decade Counter Using Feedback


Ring Counter

Clock Q4 Q3 Q2 Q1

0

1

2

3

4

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

0

0

0

0

1

Down Counter

Clock Q4 Q3 Q2 Q1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0


Up-down Counter

Pre-setable Counter

Applications of Synchronous Counter

1. Direct counting

2. Divide by N

3. Measurement of frequency and time

4. Waveform generation

5. ADC


Experiment 5.13

Synchronous Counter

Aim To design and test the count sequences of a synchronous counter.

Given sequence: 0, 7, 1, 6, 2, 5, 0, 7, ———— (repeating)

Equipment Required



Circuit Diagram

Procedure (Circuit Design)

1. Write the count sequence in binary.

2. For each flip-flop using excitation table, obtain the inputs for the transitions it has to make for each

applied clock pulse.

Excitation Table (J-K Flip-flop)

Qn Qn+1 J K

0

0

1

0

1

1

0

1

X

X

X

0

Maximum number is 7, [i.e., 23 = 8], so 3 binary bit of data is sufficient to design the counter.


Truth Table

Decimal Number Present State Next State

0

7

1

6

2

5

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

0

J1/K1 J2/K2 J3/K3 J1/K1 J2/K2 J3/K3

Using excitation table, write the logical table.

F/F 1 F/F 2 F/F 3 Decimal Number

J1 K1 J2 K2 J3 K3Initial

state

Final

state

1

X

X

0

1

X

X

0

1

X

X

1

1

X

1

X

X

0

X

0

X

0

1

X

1

X

1

X

1

X

X

1

X

1

X

1

0

7

1

6

2

5

7

1

6

2

5

0

Draw the K-map for the inputs and implement the circuit.

Note: A synchronous counter is one in which all flip-flops are clocked simultaneously.


Exercise

Design the following synchronous counters:

1. Count 3-bit odd number.

2. Count 3-bit even number.

3. Count mod-5 sequence.

4. Count 4-bit binary sequence.

Synchronous Sequential Circuit

Obtain the truth table and state diagram of the synchronous sequential circuit shown.

Circuit Diagram

State Transition Table

0

1

0

1

0

0

0

0

1

0

1

0

1

1

0

0

1

0

1

0

0

0

0

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

1

1

0

0

0

01nnnnn QyQQxKyQJyxQ

++==

State diagram is shown below

Experiment 5.14


Aim To design a synchronous sequential circuit for a given state transition diagram.


Procedure (Design)

1. Given the state transition diagram, form the truth table.

2. Fill in the inputs to be applied to the flip-flops in order to have transitions from a previous state to next

state of output of flip-flops using excitation table.

3. With inputs to the circuit and past outputs of flip-flops, obtain an expression for the flip-flop inputs.

4. Design the circuit from equations obtained.

State Transition Diagram Excitation Table (J-K Flip-flop)

Qn Qn+1 J K

0

0

1

1

0

1

0

1

0

1

X

X

X

X

1

0

Truth Table

x y Q0n Q1n Q0(n+1) Q1(n+1) J1 K1 J2 K2

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

1

1

1

1

1

1

1

1

1

1

1

X

X

X

X

0

0

1

X

1

X

X

0

X

0

0

0

0

0

1

1

1

1

0

0

1

1

0

1

0

1

1

1

1

1

0

0

0

0

1

1

X

X

X

X

0

0

0

X

0

X

X

1

X

1

1

1

1

1

0

0

0

0

0

0

1

1

0

1

0

1

0

0

0

0

1

1

1

1

0

0

X

X

X

X

1

1

1

X

1

X

X

0

X

0

1

1

1

1

1

1

1

1

0

0

1

1

0

1

0

1

0

0

0

0

0

0

0

0

0

0

X

X

X

X

1

1

0

X

0

X

X

1

X

1

Combination of inputs

and previous state

Next state from the

state diagram

From the excitation table

Obtain expressions for J1, J

2, K

1 and K

2 using K-map:


Circuit Diagram

Experiment 5.15


Aim To obtain the state diagram for the given synchronous sequential circuit.

Circuit Diagram


Design Procedure (Design)

1. Form a table with all combination of inputs to the circuit (x, y, etc.) and outputs of all flip-flops.

2. Write down the entries for the flip-flop inputs using the circuit equations.

3. Obtain the next states using the truth table of flip-flop.

4. Draw the state diagram.

Step I: Table with

combination of all

input and outputs

Step II: Entries for flip-flop inputs

Step III: Obtain the

next states using

truth table

x y Q1 Q2 J1 = Q1 K1 = x + Q2 J2 = Q2 K2 = y Q1 (n+1) Q2 (n+1)

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

1

1

1

0

0

0

0

1

1

1

1

1

0

0

0

0

0

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

1

State transition diagram:

Communication Circuits × 6.1

C h a p t e r 6

COMMUNICATION CIRCUITS

Experiment 6.1

Amplitude Modulation

Aim To construct an amplitude modulation circuit and to calculate the modulation index.

Equipment Required


CRO

Function Generator

Power supply

(0–20) MHz

(0–1) MHz

(0–30) V

1

2

1

Components Required


Transistor

Capacitor

Resistor

BC107

0.1 µF; 10 µF

22 kΩ, 10 kΩ, 1.2 kΩ

1

Circuit Diagram

figure (a)


Design

The design of amplitude modulation circuit is same as simple single stage RC coupled amplifier with function

generator (Vm

) replaced by its output resistance (50 Ω).

Procedure

1. Connections are made as shown in the figure (a).

2. Set the carrier signal to 3.2 V, 10 kHz using function generator.

3. Set the modulating signal frequency to 1 kHz and vary the amplitude around the carrier voltage.

4. Note down the maximum and minimum voltages from the CRO.

5. Calculate the modulation index using the formula, modulation index, %100VV

VVm

minmax

minmax×

+

−=

Model waveform (Observed on CRO)


Tabular Column

Vm(Volts) Vmax

(Volts)

Vmin

(Volts)m(%)

Experiment 6.2

Amplitude Demodulation

Aim To construct an amplitude demodulation circuit and to plot the wave form.

Equipment Required


CRO

AM kit

(0–20) MHz 1

1

Components Required


Diode

Capacitor

Resistor

IN4001

0.01 µF;10 µF

1 kΩ

1

Circuit Diagram

figure (a)

Procedure

1. Connections are made as shown in the figure (a).

2. Apply AM signal to the given circuit.

3. Observe the amplitude demodulated output on the CRO.

4. Compare the demodulated signal with original modulating signal. (Both must be same in all parameters).


Model Graph

Experiment 6.3

Frequency Modulation

Aim To construct the frequency modulation circuit and to calculate the modulation index.

Equipment Required


CRO/Spectrum analyser

Function generator

Power supply

(0–20) MHz

(0–1) MHz

(0–30) V

1

1

1

Components Required

Components Values Quantity

Capacitors

Resistors

Potentiometer

1 µF;

0.01 µF

10 µF

47 kΩ

4.7 kΩ

100 kΩ

150 Ω

100 kΩ

1

2

1

2

1

1

1

1


Circuit Diagram

Procedure

1. Connections are made as per circuit

diagram.

2. Without signal applied, measure

carrier signal at pin No 2 of IC 2206

3. Apply modulating AF signal at pin

No 7 of IC 2206

4. Observe frequency modulated

signal on CRO/spectrum analyser.

5. Calculate modulation index,

mf fm /)(δ=

where,

)(δ

= maximum frequency

deviation

fm

= modulating frequency

6. Calculate the bandwidth, BW = 2

(fm

+ δ)

Model Graph


Experiment 6.4

Frequency Demodulation

Aim To construct the frequency demodulation circuits and to observe waveform.

Equipment Required

Components Required


IC565

Capacitors

Resistors

10 µF

100 µF

470 pF

560 Ω

10 kΩ

1

1

1

1

2

1

Circuit Diagram

Procedure

1. Connections are made as per circuit diagram.

2. Check if PLL (IC565) is functioning or not by giving square wave to input and observe output.

3. Frequency of input signal (square wave) is varied till input and output are locked.

4. Now frequency modulated signal is fed as input and frequency demodulated signal (modulating signal) is

observed on CRO/Spectrum analyser.


Model Graph

Experiment 6.5

Pulse Position Modulator

Aim To study and implement PPM using IC555 and to observe waveform.

Equipment Required Components Required


CRO

Power supply

(0–20) MHz

+5 (fixed)

(0–5) V

1

1

1


TIMER IC

Resistor

Capacitor

555

10 kΩ

1 kΩ

0.01 µF

2

2

1

3

Circuit Diagram


Procedure


2. Vary the input (DC Voltage) from 0–5V at pin No 5 of first timer IC.

3. Observe the corresponding output waveform on the CRO at pin No 3 of second timer IC.

4. Plot the observed waveform for any one reading.

Model Graph


Experiment 6.6

Pulse Amplitude Modulation (PAM)

Aim To construct a pulse amplitude modulation and demodulation circuit and to observe the waveforms.

Equipment Required


CRO

Function Generator

PAM kit

(0–20) MHz

(0–1) MHz

1

2

1

Components Required


Transistor

Capacitor

Resistor

BC107/2N2222

1.7 µF

10 kΩ

22 kΩ

1

1

2

1

Circuit Diagram

Pulse Amplitude Modulation

Pulse Amplitude Demodulation


Procedure

Pulse amplitude modulation


2. Modulating signal is given to collector and carrier signal (pulse signal) of high frequency is given to

base of the transistor.

3. Output is taken at emitter and observe CRO.

Model Graph


Experiment 6.7

Pulse Width Modulation

Aim To study and implement pulse width modulation using IC555.

Equipment Required


CRO

Power supply

(0–20) MHz

(0–5) V

1

Components Required


Timer IC

Capacitor

Resistor

IC555

0.1 µF

47 kΩ

10 k Ω

1

1

1

1

Circuit Diagram

Procedure


2. Vary the control voltage (0–5) V and observe the corresponding change in output square waveform using

CRO.

3. Change in control voltage changes the width of the square wave.

4. Note down the TON

and TOFF

.

5. Plot the observed waveform.


Model Graph

Experiment 6.8

Pulse Width Modulation (PWM) &

Pulse Position Modulation (PPM)

Aim To construct and test a PWM and PPM circuit and to observe the waveforms.

Equipment Required


CRO

Function generator

Power supply

(0–20) MHz

(0–1) MHz

±5V

1

2

1


Components Required


PLL IC

EX-OR gate

Resistor

Capacitor

565

7486

390 kΩ

33 kΩ

10 kΩ

4.7 kΩ

5.6 kΩ

5 kΩ(pot)

0.1µF

0.01 µF

0.47 µF

0.0047 µF

1

1

1

1

1

2

1

2

3

2

1

1

Circuit Diagram


Procedure


2. Check the free running frequency of the PLL (IC565) and adjust the potentiometer to produce 15 kHz

at pin No 4.

3. Set the carrier signal (say 2Vpp

,15.9 kHz) which must be approximately in the middle of tracking range of

PLL (IC565).

4. Apply modulating signal (say 1.3 Vpp

, 300 Hz) at pin No 7.

5. Observe the PPM waveform in CRO as shown in the figure (a).

6. Observe the output of EX-OR gate (7486) using CRO adjust the frequency of the modulating signal to

obtain a stable PWM output.

Model Graph

figure (a)


Experiment 6.9

Amplitude Shift Keying (ASK) Modulator

Aim To study and implement ASK modulator and to observe the waveform.

Equipment Required

Equipments Range Quantity

CRO

Function generator

Power supply

(0–20) MHz

(0–1) MHz

(0–30) V

±12V

1

1

1

1

Components Required

Component Value Quantity

Op-amp

Transistor

Resistor

Capacitor

µA741

BC107

1 kΩ

10 kΩ (pot)

0.01µF

1

1

5

1

2

Circuit Diagram

Procedure


2. Set input signal (square wave) say 1V, 1 kHz using function generator.

3. Observe the output waveform on the CRO.

4. Plot the observed waveform on the graph.


Model Graph

Experiment 6.10

Amplitude Shift Keying Demodulator

Aim To study and implement ASK demodulator and to observe waveform.

Equipment Required


CRO

ASK modulator

Power supply

(0–20) MHz

± 5 V

(0–5) V

1

1

1

1

Components Required


Op-amp

Diode

Resistor

Capacitor

µA741

IN4001

1 kΩ

1µF

1

1

1

1


Circuit Diagram

Procedure


2. Give the FSK modulated signal as input the circuit.

3. Observe the output waveform on the CRO

4. Vary the Vref

(0–5 V) and observe the corresponding waveform on the CRO.

Experiment 6.11

Pseudo Random Binary Sequence Generator

Aim To study the functioning of a PRBS generator and to calculate the balance, run and correlation properties.



Clock generator

Power supply

(0–1) MHz

(0–5) V

1

1


D F/F

LED Resistor

EX-OR gate

NOT gate

7473

330 Ω

7486

7404

2

1

1

1

Circuit Diagram


1. Balance

2. Run property

3. Correlation property

Procedure


2. Observe the output sequence.

Experiment 6.12

Frequency Shift Keying (FSK) Modulator

Aim To implement and study FSK modulator circuit.



CRO

Function generator

Power supply

(0–20) MHz

(0–1) MHz

(0–30) V

1

1

1


Timer IC

PLL IC

Transistor

Resistor

Capacitor

XR2206

555

565

ΒC107

1 kΩ

10 kΩ

4.7 kΩ

100 kΩ

1nF

22 µF

0.01 µF

1

1

1

1

2

3

2

1

1

1

2

Circuit Diagram (Using PLL)


Using Timer 555

Procedure


2. Set the AF input (say 1Vpp

, 150 Hz) using function generator.

3. Observe the output on CRO.

4. Draw the observed waveform on the graph.

5. Identify the mark frequency and space frequency.

6. Find the mark frequency (fm

) and space frequency (fs).

7. Calculate modulation Index (MI) = ,2/

||

0f

ff sm −

where f0 = fundamental frequency of the input signal.

Using XR2206


Note: (XR2206): If voltage at pin No. 9 is less than 1volt, only resistor R2 is actuated. For voltage greater

than 2 V, resistor R1 is actuated. Thus the output signal frequency can be keyed between two levels f

1 and f

2.

Model Graph

Experiment 6.13

Frequency Shift Keying Demodulator

Aim To design and implement FSK demodulator and observe the waveform.


Equipment

CRO

FSK Modulator

Power supply


PLL IC

Op-amp

Resistor

Capacitor

565

µA741

10 kΩ

1 kΩ

33 kΩ

10 k(pot)

0.02 µF

0.01 µF

1

1

3

2

1

1

3

2


Circuit Diagram

Procedure


2. The FSK waveform (input signal) is given to pin No. 2

3. The FSK demodulated output is observed on the CRO.

Experiment 6.14

Pre Emphasis

Aim To construct and verify pre-emphasis network and plot the waveform.



CRO

Function generator

Power supply

(0–20) MHz

(0–1) MHz

(0–30) V

1

1

1


Transistor

Capacitors

Inductor

Resistors

BC107/2N2222

10 µF

0.1 µF

100pF

0.75 kH

100 kΩ

32 kΩ

2.5 kΩ

10 kΩ

75 kΩ

1

1

1

1

1

1

1

1

1

2


Circuit Diagram

Pre-emphasis (passive)

Pre-emphasis (active)

Procedure


2. Set input signal amplitude (say 1Vpp

) using function generator.

3. Vary the input signal frequency from 0Hz to 100 kHz in regular steps.

4. Note down the corresponding output voltage.


Tabular Column

Vi = 1V

PP

Frequency (Hz)Output voltage

(Vo, Volts)

Gain (dB)=20log (Vo/Vi)


Model Graph

Experiment 6.15

De-Emphasis

Aim To construct and verify de-emphasis network and to plot waveform.

Equipment Required


CRO

Function generator

(0–20) MHz

(0–100) kHz

1

1

Components Required


Capacitors

Resistors

1000 pF

75 kΩ

1

2

Circuit Diagram

Procedure


2. Set input signal amplitude say 1 Vpp

3. Vary the signal frequency from 0Hz to 100 kHz in regular steps.

4. Note down the corresponding output voltage.



Tabular Column

Vi = 1V

pp

Frequency (Hz) Output voltage (Vo, Volts) Gain (dB) = 20log (Vo/Vi)

Experiment 6.16

Digital Phase Detector

Aim To construct a digital phase measurement detector and to detect phase difference between two sinusoidal

waves and plot the waveforms and calculate phase angle.

Equipment Required


CRO

Function Generator

Power supply

Ammeter (dc)

(0–20) MHz

(0–1) MHz

± 12 V

(0-10 mA)

1

1

1

1

Components Required


Op-amp

Ex-OR gate

Transistor

Resistor

Potentiometer

Capacitor

µA741

IC7486

BC 107

1 kΩ

100 kΩ

0.01 µF

1

1

1

1

1

1


Circuit Diagram

Procedure


2. Set input signal (say 1 Vpp

, 1 kHz) using function generator.

3. Observe the square waves at the output (pin No 6) of both op-amps.

4. Vary the resistance and note down the corresponding current using DC ammeter.

5. Also observe the output waveform across the emitter resistance of the transistor.

6. Phase angle can be calculated using the formula,

φ = tan–1 [ω RC]

7. Plot the graph: Phase angle (φ) Vs Current (mA).

Tabular Columns

Resistance

(kΩΩΩΩ)

Current

(mA)

Phase angle

φφφφ = tan–1 (ωωωωRC)

Model Graph


Experiment 6.17

Mixer (Using Discrete Component)

Aim To implement and study the mixer circuit.

Equipment Required


CRO

Function generator

Power supply

(0–20) MHz

(0–1) MHz

(0–30) V

1

2

1


Components Required


Transistor

Resistors

Capacitor

BC107

10 kΩ

470 Ω

1 kΩ

0.0 µF

1 µF

1

4

1

1

2

1

Circuit Diagram

Procedure


2. Apply both the input signal to the base and emitter terminal of the transistor.

3. Observe the output waveform on the CRO.

Experiment 6.18

Mixer (Using IC)

Aim To construct and test a mixer circuit and study its working characteristics.

Equipment Required


CRO

Function generator

Power supply

(0–20) MHz

(0–1) MHz

±5V

1

1

1


Components Required


PLL

Resistor

Capacitor

ΙC565

33 kΩ

10 kΩ

1 kΩ

0.01 µF

10 µF

0.1 µF

1

1

1

1

2

1

1

Circuit Diagram

Procedure


2. Set fc = 100 kHz; f

s = 95 kHz and observe the output on the CRO. Note down the output frequency.

Tabular Column

fs (kHz) fc (kHz) Output Frequency (kHz)

Experiment 6.19

Auto Ranging

Aim To design a circuit to perform the auto ranging operation.


Equipment Required


Voltmeter

Power supply

(0–2) V

±15 V

(0–2) V

1

1

1

Components Required


Op-amp

LED

Resistors

µA741

330 Ω

10 kΩ (pot)

3

3

3

1

Circuit Diagram

Design

mV5V005.01.01.111

5,Point

mV50V05.01.11.111

5,Point

mV500V5.01.111.111

5,PointAt

==×=

==×=

==×=

C

B

A

VC

VB

VA


Procedure


2. A +5V supply is given to the voltage divider network which is connected to the inverting terminal of the

op amps.

3. A (0–2V) variable supply is given to the non-inverting terminal of the op amp through a potentiometer

(0–10kΩ).

4. Vary the resistance of the potentiometer and observe the LED glow.

5. Note down the range which each LED’s glows and tabulate the result.

Tabular Column

Voltage Range (mV) LED1 LED2 LED3

0

1

1

1

0

0

1

1

0

0

0

1

Experiment 6.20

Frequency Counter

Aim To design and implement a frequency counter using IC74121.

Equipment Required


Function generator

Power supply

(0-1) MHz

(0-30)V

1

1

Components Required


IC

AND gate

Resistors

Capacitor

OR gate

74121

7408

4.7 kΩ

1.5 kΩ

1µF

7432

1

2

1

1

1

1


Circuit Diagram

Design

T = 0.69 RC

T = 1sec and C = 1 µF

Therefore R = 1.5kΩ

Procedure


2. Counter display the frequency value of the signal.

Tabular Column

Frequency (Hz) Vo (Volt)

Experiment 6.21

Cross Over Network

Aim To design a cross-over network for a given frequency.


Equipment Required


CRO

Function generator

(0–20) MHz

(0–1) MHz

1

1

Components Required


Inductors (DIB)

Capacitor (DCB)

Resistors

Variable

Variable

1 kΩ

2

2

2

Circuit Diagram

Design

202;

2

1R

C

L

CLfo ==

π

Set fo = 1 kHz ; R

o = 1 kΩ = R

1 = R

2

Find L and C.

Procedure


2. Set the input signal say 1 Vpp

using function generator.

3. Vary the frequency from 10 Hz in a regular step.

4. Note down the corresponding output voltages across both woofer and tweeter terminals or CHI and CHII

of CRO.

5. Plot the graph: Gain (dB) vs. Frequency (Hz).


Tabular Column

Vi = 1 V

pp

Frequency (Hz) Output voltage (Vo) Gain (dB) = 20log (Vo/Vi)

Model Graph

Experiment 6.22

Directional Characteristics of

Loud Speaker and Microphone

Aim To study the directional characteristics of a loud speaker and microphone using sound level meter.

Equipment Required


CRO

Function generator

Sound level meter

Audio amplifier kit

Microphone

(0–20) MHz

(0–1) MHz

1

1

1

1

1

Block Diagram

Microprocessor 8085 × 8.1

C h a p t e r 8

MICROPROCESSOR 8085

INSTRUCTIONS TO USE YOUR MICROPROCESSOR KIT

Know Your Microprocessor

The Microprocessor (8085) is a 8 bit, 40 pin dual-in-line package IC. The CPU includes the 3 pairs of registers

B & C, D & E and H & L, which can be used as individual 8-bit register or paired 16-bit registers. Other internal

registers are stack pointer, status register (Flags) and temporary registers. 8085 has 16-bit address bus and 8-bit

data bus. It can address 216 address locations.

Use Your Microprocessor Kit

To enter data/program

1. Press MEM

2. Enter the required memory location address (on the address field).


3. Press Next

4. Enter the required data/program on the data/field program.

5. Enter the data/program on the immediate location address location changes to next location on

pressing Next

To run the program

1. Press Go

2. Enter the starting address of the program.

3. Press EXEC

4. If program is incorrect, address field displays Err.

To check the content register for result

1. Press REG followed by register name (say A, B, C,….) .

2. The content of that register will be displayed in data fields.

To check the content of the memory location

1. Press MEM

2. Enter the required memory address.

3. Press NEXT , content of the location is displayed in data field.

Supporting IC and Its Name

8279 : Keyboard/display interface controller

8253 : Programmable interval timer/counter

8251 : USART

8255 : Programmable Peripheral Interface (PPI)

8259 : Programmable Interrupt Controller (PIC)

6116 : RAM

2716 & 2816 : EPROM

Memory Mapping

Location Purpose

0000 Key-board Monitor

RDKBD → 03BA STA

UPDAD → 0440 : LSB 8EEF – Address field location

MSB SFFO – Address field location

UPDDT → 044C : STA 8FFI – data field display

OUTPUT → 0389

07FF Serial Monitor

0FFF User Expansion

1FFF

87FF

User Expansion ROM/RAM

8000 User portion RAM (Program/data location)

8FFF RAM for System manufacturer usage


MOV A B C D E H L M

A 7F 78 79 7A 7B 7C 7D 7E

B 47 40 41 42 43 44 45 46

C 4F 48 49 4A 4B 4C 4D 4E

D 57 50 51 52 53 54 55 56

E 5F 58 59 5A 5B 5C 5D 5E

H 67 60 61 62 63 64 65 66

L 6F 68 69 6A 6B 6C 6D 6E

M 77 70 71 72 73 74 75 76

MVI A B C D E H L M

3E 06 0E 16 1E 26 2E 36

PUSH B D H PSW

C5 D5 E5 F5

POP B D H PSW

C1 D1 E1 F1

XCHG

EB

XTHL

E3

1. Arithmetic Instruction

ADD A B C D E H L M

87 80 81 82 83 84 85 86

ADC A B C D E H L M

8F 88 89 8A 8B 8C 8D 8E

ADI ACI

C6 CE

SUB A B C D E H L M

97 90 91 92 93 94 95 96

SBB A B C D E H L M

9F 98 99 9A 9B 9C 9D 9E


SBI SUI

DE D6

DAD B D H SP DAA

09 19 29 39 27

2. Logical Instructions

ANA A B C D E H L M ANI

A7 A0 A1 A2 A3 A4 A5 A6 E6

ORA A B C D E H L M ORI

B7 B0 B1 B2 B3 B4 B5 B6 F6

XRA A B C D E H L M XRI

AF A8 A9 AA AB AC AD AE EE

3. Compare Instructions

CMP A B C D E H L M

BF B8 B9 BA BB BC BD BE

4. Compliment Instructions

CMA CMC

2F 3F

5. Jump Instructions

JC JM JMP JNC JNZ JP JPE JPO JZ

DA FA C3 D2 C2 F2 EA E2 CA

6. Load/Store Instructions

LXI B D H SP LDAX B D

01 11 21 31 0A 1A

LDA LHLD

3A 2A

STAX B D SHLD SPHL STA STC

02 12 22 F9 32 37


7. Interrupt Instructions

RST 0 1 2 3 4 5 6 7

C7 CF D7 DF E7 EF F7 FF

SIM RIM EI DI

30 20 FB F3

8. Bit Rotation Instructions

RLC RAL RRC RAR

07 17 0F 1F

9. Return Instructions

RET RZ RC RPE RM RNZ RNC RPO RP

C9 C8 D8 E8 F8 C0 D0 E0 F0

10. Increment/Decrement Instructions

INR A B C D E H L M

3C 04 0C 14 1C 24 2C 34

INX B D H SP

03 16 23 33

DCR A B C D E H L M DCX B D H SP

3D 05 0D 15 1D 25 2D 35 0B 1B 2B 3B

11. Halt Instructions

HLT

76

12. No Operation Instruction

NOP

00

13. Port Instructions

IN OUT

DB D3


14. Call Instructions

CALL CZ CC CPE CM CNZ CNC CPO CP CPI

CD CC DC EC FC C4 D4 E4 F4 FE

8085 PROGRAMMING

Practice Session - 1

1. Program to load register A, B, C, D with same constant.

Address Label Mnemonic Operand Hex Code Comment

8800 MVI A, FF 3E [A] ← [FF]H

8801 FF (FF)H is transferred to Accumulator

A-register

8802 MVI B, FF 06 [B] ← [FF]H

8803 FF (FF)H is transferred to B-register

8804 MVI C, FF 0E [C] ← [FF]H

8805 FF (FF)H is transferred to C-register

8806 MVI D, FF 16 [D] ← [FF]H

8807 FF (FF)H is transferred to D- register

8808 HLT 76 Halt the program

2. “MVI” instruction takes 2 bytes of memory whereas “MOV” instruction takes only 1 byte of memory.


8800 MVI A, FF 3E [A] ← [FF]H


8802 MOV B, A 47 [B] ← [A]

Content of A is transferred to

B-register

8803 MOV C, A 4F [C] ← [A]

Content of A is transferred toC- register

8804 MOV D, A 57 [D] ← [A]

8805 HLT 76 Content of A is transferred toD-register

*Square bracket “[B]” indicates the “content” of B-register


3. [FF]H : “FF” in Hexadecimal Code


8800 MVI A, FF 3E [A] ← [FF]


8802 MOV B, A 47 [B] ← [A]

Content of A is transferred to

B-register

8803 MOV C, B 48 [C] ← [B]

Content of B is transferred to

C- register

8804 MOV D, C 51 [D] ← [C]

Content of D is transferred to

C-register

8805 RST5 EF Reset

4. Four bytes of data are stored in consecutive data memory location of starting at address x. Write a program

to load E with [x], D with [x + 1], C with [x + 2] and A with [x + 3]

By Direct Addressing Mode


8800 LDA 8900 3A [A] ← [8900]H

8801

8802

00

89

Content of address [8900]H is loaded

to Accumulator

8803 MOV E, A 5F [E] ← [A]

8804

8805

LDA 8901 3A

01

8806 89

[A] ← [8901] H

Content of address [8901]H is loaded

to Accumulator

8807 MOV D, A 57 [D] ← [A]

8808

8809

LDA 8902 3A

02

880A 89

[A] ← [8902]H

Content of address (8902)H is loaded

to Accumulator

880B MOV C, A 4F [C] ← [A]

880C LDA 8903 3A

880D 03

880E 89

[A] ← [8903]H

Content of address (8903)H is loaded

to Accumulator

880F HLT 76 Halt the program


By Register Indirect Addressing Mode


8800 LXI H, 8900 21

8801 00

8802 89

Memory pointer is pointed to

[8900]H

[8900]H ← [M] ← [HL]

8803 MOV E, M 5E [E] ← [M]

8804 INX H 23 Next [HL] location

8805 MOV D, M 56 [D] ← [M]

8806 INX H 23 [D] ← [A]

8807 MOV C, M 4E [C] ← [M]

8808 INX H 23 [D] ← [A]

8809 MOV A, M 7E [A] ← [M]

880A HLT 76 Halt

Note: Direct addressing is simple but occupies large program memory location than indirect addressing. Indirect

addressing mode is more flexible but it takes more time for execution.

Program to move bytes of data to other memory location.

Direct Addressing Mode


8800

8801

8802

LDA 8900 3A

00

89

[A] ← [8900]

8803

8804

STA 8950 32

50

8805 89

[8950]H ← [A]

Content of Accumulator is stored in

memory address [8950]H

8806

8807

8808

LDA 8901 3A

01

89

[A] ← [8901]H

8809 STA 8951 32

890A 51

890B 89

Content of Accumulator is

stored in memory address

[8951]H.

890C HLT 76 Halt


Indirect Addressing Mode


8800 LXI H, 8900 21 [M] ← [HL] ⇐ [8900]H

8801 00 Memory location to store the data

8802 89

8803 LXI B, 8950 01

8804 50

8805 89

[BC]H ⇐ [8950]H

Memory location to store the result

8806 MOV A, M 7E [A] ← [[N] [L]]

8807 STAX B 02 [8950]H ⇐ [[B] [C]] ← [A]


8809 INX B 03 Next [BC] location

880A MOV A, M 7E [A] ← [M]

880B STAX B 02 [8951]H ⇐ [[B] [C]] ← [A]

880C HLT 76 Halt

STANDARD PROGRAMS

1. Program to interchange the data byte between two locations.


8800 LXI H,8900 21 [M] ← [HL] ⇐ [8900]H


8802 89

8803 LXI D, 8950 11 [DE] ⇐ [8950]H


8805 89

8806 MOV B, M 46 [B] ← [M]

8807 LDAX D 1A [8950]H ⇐ [DE]H ← [A]

8808 MOV M, A 77

8809 MOV A, B 78

880A STAX D 0A

880B HLT 76 Halt

Note: The examples given in this book uses 8800 as the starting memory location for programs and 8900 as

the starting memory location for data storage.


2. Program to exchange the data byte stored in register-D with register-H and data byte stored in register-E

with register-L.


8800 LHLD 8900 2A [L] ← [8900]H

8801 00 [H] ← [8901]H

8802 89

8803 MOV D, H 54 [D] ← [H]

8804 MOV E, L 5D [E] ← [L]

8805 LHLD 8902 2A [L] ← [8902]

8806 02 [D] ⇔ [H]

8807 89 [E] ⇔ [L]

8808 XCHG EB

8809 HLT 76

3. Program to exchange the data byte stored in register-D with register-H and data byte stored in register E

with register-L.


8800 LXI H, 8900 21 [M] ⇐ [HL] ← [8900]H

8801 00

8802 89

8803 MOV D, M 56 [D]H ← [M]


8805 MOV E, M 5E [E] ← [M]

8806 LHLD 8902 2A [L] ← [8902]

8807 02 [H] ← [8903]

8808 89

8809 XCHG EB [E] ⇔ [L] ; [D] ⇔ [H]

880A HLT 76 Halt


4. Program to add two 8 bit binary number (overflow considered)


8800 LXI H, 8900 21 [M] ← [HL]H ⇐ [8900]H

8801 00

8802 89

8803 MVI C, 00 0E

8804 00

[C] ← 00H: Carry (over flow)

indication

8805 MOV A, M 7E [A] ← [M]

8806 INX H 23 [HL] + 1

8807 ADD M 86 [A] ← [A] + [M]

8808 JNC LOOP1 02 If [CY] = 00: Go to 880B location

8809 0C If [CY] = 01: Go to 880C location

880A 88

880B INR C 0C [C] ← [C]+1

880C LOOP1 MOV M, A 77 [M] ← [A] : Value of Accumulate

transferred to memory [8903]H

880D INX H 23 Next [HL] location

880E MOV M, C 71 [M] ← [C]: Value of carry

indication transferred to memory

[8904]H

880F HLT 76 Halt

5. Program to add N 8 bit binary numbers (over flow considered)


8800 MVI B, N 06 [B] ← NH Counter for count number

of data to be added

8801 [N]

8802 LXI H, 8900 21 [M] ← [HL] ⇐ [8900]H

8803 00

8804 89

8805

8806

MVI C, 00 0E

00[C] ← 00H: Carry or overflow

indicator

8807 MOV A, C 79 [A] ← [C]

8808 ADD M 86 [A] ← [M]+[A]

8809 LOOP2 JNC LOOP1 02, OE, 88 If [CY] = 0 go to location [880D)H

880C INR C OC If [CY] = 01: go to location (880C)H

880D INX H 23 [C] ← [C]+1; [HL]+1

880E LOOP1 DCR B 05 [B] = [B] - 1


880F JNZ LOOP2 C2, 09, 88 If [Z] = 0 : go to location [8808]H

[Z] = 1 : go to location [8812]H

8812 MOV M, A 77 8902 ← [M] ← [A]

8813 INX H 23

8814 MOV M, C 71

8815 INX H 23 [HL]+1

8816 HLT 76 Halt

6. Program to add two 16-bit binary numbers


8800 LHLD 8900 2A [HL] ← [8900]

8801 00 [H] ← [8901]

8802 89

8803 XCHG B, H EB [E] → [H]

8804 4D [D] ← [L]

8805 LHLD 8902 2A [L] ← [8902]

8806 02 [H] ← [8903]H

8807 89 [L] ← [L]+[E]

8808 DAD B 19 [H] ← [H]+[D]+[CY]

8809 SHLD 8904 22 [8904] ← [L]

880A 04 [8905]H ← [H]

880B 89

880C HLT 76 Halt

Input data : [8900] ← [Data 1] LOB, [8901] ← [Data 1] HCB

7. Program to add two 8-bit BCD numbers


8800 LXI H, 8900 21 [M] ← [HL] ⇐ [8900]

8801 00

8802 89

8803 MOV A, M 7E [A] ← [M]

8804 INX H 23

8805 ADD M 86 [A] ← [A] + [M]

8806 DAA 27 If [A]<9:[A] ← [A]

If [A]>9:[A] ← [A]+6

8807 STA 8902 32

8808 02 [8902]H ⇐ [A]

8809 89

880A HLT 76 Halt


8. Subtraction of two 8-bit numbers


8800 MVI C, 00 0E [C] ⇐ [00]H ; Carry register

8801 00

8802 LXI H, 8900 21 M ← [HL] ⇐ [8900]H

8803 00

8804 89

8805 MOV B, M 46

8806 INX H 23

8807 MOV A, M 7E

[B] ← [M]

[8901] ← [HL] ← [HL]+1

[A] ← [M]

8808 SUB B 90 [A] ← [A]–[B]

8809 JNC LOOP1 D2 If [CY]=0: go to location [880F]

880A 0F If [CY]=1 go to location [880C]

880B 88

880C INR C 0C [C] ← [C]+1

880D CMA 2F [A] ← [A]

880E INR A 3C [A] ← [A]+1

880F LOOP1 INX H 23 [8902] ⇐ [HL] ← HL+1

8810 MOV M, A 77 [M] ← [A] Difference in 8902

8811 MOV A, C 79 [A] ← [C]

8812 INX H 23 [8903] ⇐ [HL] ← HL+1

8813 MOV M, A 77 [M] ← [A] Carry in 8903

8814 HLT 76 HALT

9. Program to subtract two BCD numbers


8800 LHLD 8900 2A [HL] ← [8900]H

8801 00 [+1] ← [8901]H

8802 89

8803 MVI A, (99)H 3E [A] ← [99]H

8804 (99)H

8805 SUB L 95 [A] ← [A]-[L]

8806 ADI (01)H C6 [A ]← [A]+[01]H

8807 (01)H

8808 DAA 27 Decimal Accumulator adjust

8809 ADD H 84 [A] ← [A]+[01]H

880A DAA 27

880B STA 8902 32 [8902]H ← [A]

880C 02

880D 89

880E HLT 76 Halt


10. Program to subtract two 16-bit numbers


8800 MVI C, 00 OE [C] ← [00]H

8801 00

8802 LHLD 8900 2A

8803 00 [HL] ← [8900]

8804 89

8805 XCHG EB [D] ⇔ [H]; [E] ⇔ [L]

8806 LHLD 8902 2A [HL]⇐ [8902]H

8807 02

8808 89

8809 CALL SUB CD Call "SUB" subroutine

880A 50

880B 88

880C DAD D 19 [HL] ← [HL]+[DE]

880D JC LOOP1 DA If [CY]=1: go to location [8814]H

880E 14 If [CY]=0: go to location [8810]H

880F 88

8810 CALL SUB CD Call "SUB" subroutine

8811 50

8812 88

8813 INR C OC [C] ← [C]+1

8814 LOOP1 SHLD 8904 22 [8904] ← [L]

8815 04 [8905] ⇐ [H]

8816 89

8817 MOV A, C 79 [A] ← [C]

8818 STA 8906 32 [8906] ← [H]

8819 06

881A 89

881B HLT 76 Halt

8850 SUB MOV A, H 7C [A] ← [H]

8851 CMA 2F [A] ← [A]

8852 MOV L, A 67 [L] ← [A]

8853 MOV A, H 7D [A] ← [H]

8854 CMA 2F [A] ← [A]

8855 MOV H, A 6F [H] ← [A]

8856 INX H 23 [HL] ← [HL]+1

8857 RET C9 Return to "SUB" called


11. Program to multiply two 8-bit binary numbers


8800 LXI H, 8900 21 [M] ← [HL] ← [8900]H

8801 00

8802 89

8803 MOV B, M 46 [B] ← [M]

8804 INX H 23 [HL] ← [HL]+1

8805 MOV C, M 4E [C] ← [M]

8806 XRA A AF [A] ← [00]H

8807 LOOP1 ADD C 81 [C] ← [C]+1

8808 DCR B 05 [B] ← [B]-1

8809 JNZ LOOP1 C2

880A 07 If [Z] = 0: goto location [8807]H

880B 88 If [Z] = 1: goto location [880C]H

880C STA 8902 32 [8902]H ⇐ [A]

880D 02

880E 89

880F HLT 76 Halt

12. Program to multiply two 8-bit binary numbers (Shifting and adding)


8800 LXI H, 8900 21 [M] ⇐ [HL] ← [8900]H

8801 00

8802 89

8803 MOV C, M 4E [C] ← [M]

8804 MVI B, 00 06 [B] ← 00H

8805 00

8806 MVI D, 08 16 [D] ← 08H: to count 8-bit

8807 08 [HL] ← [HL]+1

8808 INX H 23 [A] ← [M]

8809 MOV A, M 7E [HL] ← 0000H

880A LOOP2 RAR 1F Rotate the bit of Accumulator right

880B JNC LOOP1 D2 If [CY]= 0: go to location [8811]H

880C OF If [CY] = 1: go to location [8810]H

880D 88


880E DAD D 19 [HL]H ← [HL]H+[DE]H

880F LOOP1 XCHG EB [D] ⇔ [H]; [E] ⇔ [L]

8810 DAD H 29

8811 XCHG EB [D] ⇔ [H]; [E] ⇔ [L]

8812 DCR D 15 [D] ← [D] – 1

8813 JNZ LOOP2 C2

8814 0A If [Z]=0: go to location [8818]H

8815 88 If [Z]=1: go to location [881C]H

8816 SHLD 8FEF 22 Monitor program location for

address field display

8817 EF

8818 8F

8819 CALL UPDAD CD

881A 40

881B 04

Display routine for address field

881C HLT 76 Halt

13. Program to perform multiplication of two 16-bit binary number.

Address Label Mnemonics Operand Hexcode Comment

8800 LHLD 8900 2A [L] ← [8900]H

8801 00 [H] ← [8901]H

8802 89

8803 XCHG EB [L] ⇔ [E]

8804 LHLD 8902 2A [H] ⇔ [D]

8805 02 [L] ← [8902]H

8806 89 [H] ← [8903]H

8807 DCX H 2B [HL] ← [HL]-1

8808 LOOP1 DCX H 2B [HL] ← [HL]-1

8809 MOV A,E 7B [A] ← [E]

880A ADD E 83 [A] ← [A]+[E]

880B MOV E,A 5F [E] ← [A]

880C MOV A,D 7A [A] ← [D]

880D ADC D 8A [A] ← [A]+[D]+[CY]

880E MOV D,A 57 [D] ← [A]

880F MOV A,H 7C [A] ← [H]

8810 ORA L B5 [A] ← [A] OR [L]

8811 JNZ LOOP1 C2 If [z]=0: go to location [8808]

8812 08 If [z]=1: go to location [8814]


8813 88

8814 MOV A,D 7A [A] ←[D]

8815 STA 8FF0 32

8816 F0

8817 8F

8818 MOV A,E 7B

8819 STA 8FEF 32

881A EF

881B 8F

881C CALL UPDAD CD

881D 40

Address field display routine

881E 04

881F HLT 76 Halt

14. Program to perform division of two 8-bit binary numbers.


8800 LXI H, 8900 21 [M] ⇐ [HL] ← [8900]

8801 00

8802 89

8803 MOV A, M 7E [A] ← [M]

8804 INX H 23 [HL] ← [HL]+1

8805 MOV C, M 4E [C] ← [M]

8806 MVI B, 00 06 [B] ← 00

8807 00

8808 LOOP2 SUB C 91 [A] ← [A]–[C]

8809 JC LOOP1 DA If [CY] = 1: go to location [8810]

880A 10 If [CY] = 0: go to location [8800]

880B 88

880C INR B 04 [B] ← [B]+1

880D JMP LOOP2 C3 Go to location (8808)H

880E 08

880F 88

8810 LOOP1 MOV A, B 78 [A] ← [B]

8811 STA 8902 32 [8902] ⇐ [A]

8812 02

8813 89

8814 HLT 76 Halt


15. Program to find number of 1’s and 0’s in a given 8 bit binary number.


8800 MVI B, 00H 06 [B] ← [00]H: storing 1´s

8801 00

8802 MVI C, 00H 0E [C] ← [00]H: Storing 0's

8803 00

8804 MVI D, 08H 16 [D] ← [08]: Bit

8805 [08]H

8806 MVI A, XXH 3E

8807 XXH

[A] ← XH: XH is the number to be

evaluated

8808 LOOP3 RAR 1F Rotate right through carry

8809 JNC LOOP1 D2 If [CY]=0: go to location [8810]

880A 10 If [CY]=1: go to location [880C]

880B 88

880C INR B 04 [B] ← [B]+1

880D JMP LOOP2 C3 Go to location [8811]H

880E 11

880F 88

8810 LOOP1 INR C 0C [C] ← [C]+1

8811 LOOP2 DCR D 15 [D] ← [D]–1

8812 JNZ LOOP3 C2 If [Z]=0: go to location [8808]

8813 08 If [Z]=1: go to location [8815]

8814 88

8815 MOV A, B 78 [A] ← [B]

8816 STA 8850 32 [8850]H ⇐ [A]:1´s total

8817 50

8818 88

8819 MOV A, C 79 [A] ← [C]

881A STA 8851 32 [8851]H ⇐ [A]: 0’s total

881B 51

881C 88

881D HLT 76 Halt


16. Program to find the smallest to N 8-bit binary number


8800 LXI H,8900 21 [M] ← [HL] ⇐ [8900]H

8801 00

8802 89

8803 MOV B, M 46 [B] ← [M] Count in B-register

8804 DCR B 05 [B] ← [B]–1

8805 INX H 23 [8901] ⇐ [HL] ← [HL]+1

8806 MOV A, M 7E [A] ← [M] First data in Act

8807 LOOP2 INX H 23 [8902] ← [HL] ← [HL]+1

8808 CMP M BE Compare [M] with [A]

8809 JC LOOP1 DA If [CY]=1: go to location [880D]H

880A 0D If [CY]=0: go to location [880C]H

880B 88

880C MOV A,M 7E [A] ←[M]

880D LOOP1 DCR B 05 [B] ←[B]–1

880E JNZ LOOP2 C2 If [Z]=0: go to location [8807]H

880F 0 7 If [Z]=1: go to location [8811]H

8810 88

8811 STA 8FF1 32

8812 F1

8813 8F

Monitor program location for data

field display

8814 CALL 044C CD

8815 4C

8816 04

8817 HLT 76 Halt

Note: Largest number in a N 8-bit binary numbers can be obtained by replacing “JC” to “JNC”.


17. Program to obtain the descending order of N 8-bit binary numbers.


8800 LXI H, 8900 21 [M] ← [HL] ← [8900]

8801 00

8802 89

8803 MOV B, M 46 [B] ← [M]:Counter to count 8-bit

8804 DCR B 05 [B] ← [B]-1

8805 INX H 23` [8901] ← [HL] ← [HL]+1

8806 MOV A, M 7E [A] ← [M]

8807 LOOP2 INX H 23 [8902] ⇐ [HL] ← [HL]+1

8808 CMP M BE Compare [HL] with [A]

8809 JC LOOP1 DA If [CY]=1: go to location [880D]

880A OD If [CY]=0: go to location [880C]

880B 88

880C MOV A, M 7E [A] ← [M]

880D LOOP1 DCR B 05 [B] ← [B]-1

880E JNZ LOOP2 C2 If [Z]=0: go to location [8807]

880F 07 If [Z]=1: go to location [8812]

8810 88

8811 STA 8FF1 C2

8812 F1

8813 8F

8814 CALL 004C CD

8815 4C

8816 04

Monitor program location for data

field display

8817 HLT 76 Halt

To covert the above program for ascending order, replace “JC” by “JNC” .


18. Program to convert 8-bit binary number to gray code

Address Label Mnemonics Operand Hex Code Comment

8800 MVI A, [X]H 3E A ← XH: Value to be converted

8801 XH

8802 MOV B, A 47 [B] ← [A]

8803 RAR 1F Rotate right the Accumulator

8804 XRA B A8 [A] ← [A]"XRA"[B]

8805 STA 8FF1 32 Display routine

8806 F1

8807 8F

8808 CALL 044C CD

8809 4C

880A 04

880B HLT 76 Halt

19. Program to convert gray code to 8-bit binary number


8800 MVI A, XH 3E [A] ← XH : value to be converted

8801 XH

8802 MVI C, [07]H 0E [C] ← 07H

8803 07H

8804 LOOP1 MOV B, A 47 [B] ← [A]

8805 RAR 1F Rotate right the Accumulator

8806 XRA B A8 [A] ← [A] "XOR" [B]

8807 DCR C 0D [C] ← [C]–1

8808 JNZ LOOP1 C2 If [Z] = 0 : go to location [8804]

8809 04 If [Z] = 1 : go to location [880A]

880A 88

880B STA 8FF1 32 Display routine

880C F1

880D 8F

880E CALL 044C CD

880F 4C

8810 04

8811 76 Halt


20. Program to convert ASCII hex number into its binary equivalent


8800 LDA 8900 3A [A] ⇐ [8900]H

8801 00

8802 89

8803 CPI 40 FE Compare [40]H with [A]

8804 40


8806 13 If [CY] = 0: go to location [8808]

8807 88

8808 SUI 40 D6 [A] ← [A] – [40]H

8809 40

880A ADI 09 C6 [A] ← [A] + 09H

880B 09

880C LOOP2 STA 8FF1 32

880D F1

Monitor program for data field

display

880E 8F

880F CALL 044C CD

8810 4C

8811 04

8812 HLT 76

8813 LOOP1 SUI 30 D6 [A] ← [A]–[30]H

8814 30

8815 JMP LOOP2 C3 Go to location [880C]H

8816 0C

8817 88

ASCII codes 30 to 39 represents 0 to 9 in binary and 41 to 46 represent ‘A’ to ‘F’.

If the ASCII code is less than 40, then 30 is subtracted to get the binary equivalent.

If the ASCII code is greater than 40, then the equivalent number lies between ‘A’ and ‘F’.


21. Program to convert binary number into its ASCII equivalent.


8800 LDA 8900 3A [A] ⇐ [8900]

8801 00

8802 89

8803 MOV B, A 47 [B] ← [A]

8804 CALL ASCII CD Call subroutine "ASCII"

8805 16

8806 88

8807 STA 8901 32 [8901] ← [A]

8808 01

8809 89

880A MOV A, B 78 [A] ← [B]

880B RRC 0FRotate the content of Accumulator

right through carry

880C RRC 0F

880D RRC 0F

880E RRC 0F

880F CALL ASCII CD Call subroutine "ASCII"

8810 16

8811 88

8812 STA 8902 32 [8902] ← [A]

8813 02

8814 89

8815 HLT 76

8816 ASCII ANI [0F]H E6 "AND"[0F]H with [A]

8817 0F

8818 CPI [0A]H FE Compare [0A]H with [A]

8819 0A

881A JC LOOP1 DA If [CY] = 1: go to location [881F]H

881B 1F If [CY] = 0: go to location [881D]H

881C 88

881D ADI [07]H C6 [A] ← [A]+[07]H

881E 07

881F LOOP1 ADI 30H C6 [A] ← [A]+[30]H

8820 30

8821 RET C9 Return to subroutine called place

For binary numbers from 0 to 9, the ASCII code is 30 to 39 and for ‘A’ to ‘F’, the ASCII code is 41 to 46.

If the numbers are between 0 to 9, 30 must be added to the ASCII code.

If the numbers are between ‘A’ to ‘F’, 37 must be added.


22. Program to convert 2 digit BCD to its binary equivalent.


8800 LDA 8900 3A

8801 00

[A] ← [8900]H – BCD number

in 8900

8802 89

8803 MOV B, A 47 [B] ← [A]

8804 ANI 0FH E6 "AND" [0F]H with [A]

8805 0F

8806 MOV C, A 4F [C] ← [A]

8807 MOV A, B 18 [A] ← [B]

8808 ANI 0F E6 "AND" [F0]H with [A]

8809 F0

880A RRC 0F Rotate right without carry

880B RRC 0F

880C RRC 0F

880D RRC 0F

880E MOV B, A 47 [B] ← [A]

880F MVI D, 0A 16 [D] ← [0A]H

8810 0A Set a counter for multiply

8811 XRA A AF A ← AA+AA [X–OR]

8812 LOOP1 ADD B 80 [A] ← [A]+[B]

8813 DCR D 15 [D] ← [D]–1

8814 JNZ LOOP1 C2 If [Z] = 0: go to location [8812]

8815 12 If [Z] = 1: go to location [8817]H

8816 88

8817 ADD C 81 [A] ← [A]+[C]

8818 STA 8FF1 32 Display the binary equivalent

8819 F1

881A 8F

881B CALL 044C CD

881C 4C

881D 04

881E HLT 76 Halt


23. Program to convert binary numbers to its equivalent BCD.

8800 LXI H, 8900 21

8801 00

[M] ← [HL] ⇐ [8900]H - Binary

number in 8900

8802 89

8803 MOV A, M 7E [A] ← [M]

8804 MOV D, A 57 [D] ← [A]

8805 MVI B, 00H 06 [B] ← [00]H

8806 [00]H

8807 LOOP1 INR B 04 [B] ← [B]+1

8808 SUI 0AH D6 [A] ← [A]–[0A]H

8809 0AH

880A JNC LOOP1 D2 If [CY] = 0 : go to location [8807]

880B 07 If [CY] = 0 : go to location [880D]

880C 88

880D DCR B 05 B ← [B]–1

880E MOV E, B 58 [E] ← [B]

880F XRA A AF [A] ← [A][A]–[A] [A]

8810 LOOP2 ADI 0AH C6

8811 0AH

8812 DCR E 5F E ← [E]–1


8814 10 If [Z] = 1: go to location [8816]

8815 88

8816 MOV E, A 5F E ← [E]–1

8817 MOV A, D 7A [A] ← [D]

8818 SUB E 93 [A] ← [A]–[E]

8819 MOV C, A 4F [C] ← [A]

881A MOV A, B 78 [A] ← [B]

881B RLC 07 Rotate left

881C RLC 07

881D RLC 07

881E RLC 07

881F ORA C B1 [A] ← [C] "OR" [A]

8820 STA 8FF1 32 CURDT location

8821 F1

8822 8F

8823 CALL 044C CD

8824 4C

Display routine – UPDDT-Display

the BCD equivalent

8825 04

8826 HLT 76 Halt


24. Program to reverse a string


8800 LDA H, 8900 3A [A] ⇐ [8900]H – String in 8900 3A

8801 00

8802 89

8803 MOV B, A 47 [B] ← [A]

8804 MVI C, 08 0E [C] ← [08]H

8805 08H

8806 MVI D, 00 16 [D] ← [00]H

8807 00

8808 LOOP1 MOV A, B 78 [A] ← [B]

8809 RAL 17 Rotate left without carry

880A MOV B, A 47 [B] ← [A]

880B MOV A, D 7A [A] ← [D]

880C RAR 1F Rotate right without carry

880D MOV D, A 57 [D] ← [A]

880E DCR C 0D [C] ← [C]–1

880F JNZ LOOP1 C2 If [Z] = 0: go to location [8807]


8811 88

8812 MOV A, D 7A [A] ← [D]

8813 STA 8FF1 32

8814 F1

8815 8F

8816 CALL 044C CD

8817 4C

Data field display routine

– Reversed string displayed

8818 04

8819 HLT 76 Halt

25. (a) Program for generating Fibonacci series (upto (FF)H


8800 MVI A, NH 3E N : Number of values

8801 NH [D] ← [N]H

8802 MVI B, 00 06 [B] ← [00]H

8803 00H

8804 MVI C, 01 0E [C] ← [01]

8805 01H


8806 LXI H, 8900 21 [M] ← [HL] ⇐ [8900]H

8807 00

8808 89

8809 LOOP1 MOV A, B 78 [A] ← [B]

880A MOV M, A 77 [8900] ⇐ [M] ← [A]

880B ADD C 81 [A] ← [C]+[A]

880C MOV B, C 41 [B] ← [C]

880D MOV C, A 4F [C] ← [A]

880E INX H 23 [HL] ⇐ [HL]+1

880F DCR D 15 [D] ← [D]–1

8810 JNZ LOOP1 C2



8813 HLT 76 Halt

(b) Program to generate Fibonacci series maximum [FFFF]H


8800 LXI H, 8900 21 [M] ⇐ [HL] ← [8900]

8801 00

8802 89

8803 MOV A, M 7E [A] ← [M]

8804 INX H 23 [HL] ← [HL]+1

8805 MOV C, M 4E [C] ← [M]

8806 MVI B, [00]H 06 B ← [00]H

8807 00 [L] ← [A]

8808 MOV L, A 6F [H] ← [00]

8809 MVI H, [00]H 26

880A 00

880B LOOP2 DAD D 19 [HL]H ← [DE]H +[HL]H

880C MOV A, H 7C [A] ← [H]

880D CPI [FF]H FE Compare [FF]H with [A]

880E [FF]H

880F JC LOOP1 DA If [CY] = 1: go to location [8819]


8811 88

8812 MOV A, L 7D [A] ← [L]

8813 CPI [FF]H FE Compare [FF]H with [A]


8814 FF



8817 88

8818 HLT 76

8819 LOOP1 SHLD 8FEF 22

881A EF

881B 8F

881C PUSH H E5

881D PUSH D D5

881E CALL 0440 CD Delay monitor subroutine

881F 40

8820 04

8821 CALL DELAY CD Delay subroutine to be stored in

[882A]H Location

8822 2A

8823 88

8824 POP D D1

8825 POP H E1

8826 XCHG EB [H] ⇔ [D]

8827 JMP LOOP2 C3 [L] ⇔ [E]

8828 0B Go to location [880B]

8829 88

26. Program to solve the given Boolean expression

ZYXZYXZYXF ++=


880D MOV E, A 5F

880E MOV A, H 7C [Y] ⇐ [C] ← [A]

880F CMA 2F

8810 MOV L, A 6F [Z] ⇐ [L] ← [A]

8811 ANA E A3 YZ ⇐ [A] ← [A]"AND"[E]

8812 ANA B A0 XYZ ⇐ [A] ← [B]"AND"[A]

8813 STA 8903 32

8814 03

8815 89

8816 MOV A, L 70

8817 ANA D A2

8818 ANA C A1

8819 STA 8904 32

881A 04

881B 89

881C MOV H, M 66

881D ANA E A3

881E ANA D A2

881F STA 8905 32

8820 05

8821 89

8822 LXI H, 8903 21

8823 03

8824 89

8825 MOV A, M 7E

8826 INX H 23

8827 ORA M B6

8828 INX H 23

8829 ORA M B6

882A STA 8FF1 32

882B F1

882C 8F

882D CALL 044C CD

882E 4C

882F 04

8830 HLT 76 Halt


27. Program to find the factorial of a number.


8800 MVI A, XH 3E

8801 XH

[XX]H: Number whose factorial has

to be found [A] ← XH

8802 MVI B, [XX-2]H 06 [B] ← [XX–2]H

8803 [XX–2]H

8804 LOOP2 MOV C, B 48 [C] ← [B]

8805 MOV D, A 57 [D] ← [A]

8806 LOOP1 ADD D 82 [A] ← [D]+[A]

8807 DCR C OD [C] ← [C]–[1]H


8809 06 If [Z] = 1: go to location [880B]

880A 88

880B DCR B 05 [B] ← [B]–1

880C JNZ LOOP2 C2 If [Z] = 0: go to location [8804]H

880D 04 If [Z] = 1: go to location [880F]H

880E 88

880F STA 8FF1 32

8810 F1

8811 8F

8812 CALL 044C CD

8813 4C

Data field display monitor routine

8814 04

8815 HLT 76

28. Program to find the square root of a number.


8800 MVI C, 01H 0E [C] ← [01]H

8801 01

8802 LXI H, 8900 21

8803 00

[M] ← [HL] ⇐ [8900]-Number

in 8900H

8804 89

8805 LOOP2 MOV A, M 7E [A] ← [M]

8806 CALL ROOT CD CALL subroutine "ROOT"

8807 50

8808 88

8809 CMP C B9 Compare '[C]' with 'A'


880A JZ LOOP1 CA If [Z] = 0: go to location [8811]H

880B 11 If [Z] = 1: go to location [880D]H

880C 88

880D INR C 0C [C] ← [C]+1

880E JMP LOOP2 C3 Go to location [8805]H

880F 05

8810 88

8811 LOOP1 STA 8FF1 32

8812 F1

8813 8F

8814 CALL 044C CA

8815 4C

Data field display monitor routine

8816 04

8817 HLT 76 Halt

8850 ROOT MVI B, 00H 06 [B] ← [00]H

8851 00

8852 LOOP3 SUB C 91 [C] ← [C]–1

8853 INR B 04 [B] ← [B]+1

8854 CMP C B9 Compare [C] with [A]

8855 JNC LOOP3 D2 If [CY] = 0 : go to location [8852]H

8856 52 If [CY] = 1: go to location [8858]H

8857 88

8858 MOV A, B 78 [A] ← [B]

8859 RET C9 Return to "ROOT'

29. Program to find the square of a number


8800 MVI C, 01 0E [C] ← [01]H

8801 [01]H

8802 MOV B, C 41 [B] ← [C]

8803 MVI A, XH 3E [A] ← [XX]H

8804 XH

8805 LOOP3 SUB B 90 [A] ← [A]–[B]

8806 JZ LOOP1 CA If [Z] = 0: go to location [8809]H


8808 88

8809 JC LOOP2 DA If [CY] = 0 : go to location [880C]H


880A 16 If [Z] = 0: go to location [8816]H

880B 88

880C INR C 0C [C] ← [C]+1

880D INR B 04 [B] ← [B]+1

880E INR B 04 [B] ← [B]+1

880F JMP LOOP3 C3 Go to location [8805]H

8810 05

8811 88

8812 LOOP1 MOV A, C 19 [A] ← [C]

8813 STA 8900 32 [8900] ⇐ [A]

8814 00

8815 89

8816 LOOP2 HLT 76 Halt

30. Program to find the square of a number


8800 MVI C, 01 0E [C] ← [0]H

8801 [01]H

8802 LDA 8900 3A [A] ← [8900]H : Data location

8803 00

8804 89

8805 MOV B, A 47 [B] ← [A]

8806 MOV D, A 57 [D] ← [A]

8807 MVI A, 00H 3E [A] ← [00]H

8808 00H

8809 LOOP2 ADD B 80 [A] ← [A]+[B]

880A JNZ LOOP1 C2 If [Z] = 0: go to location [880E]H

880B 0E If [Z] = 1: go to location [880D]H

880C 88

880D INR C 0C [C] ← [C]+1

880E LOOP1 DCR D 15 [D] ← [D]–1

880F JNZ LOOP2 C2 If [Z] = 0: go to location [8809]H


8811 88

8812 STA 8901 32 [8901]H ⇐ [A]: result location

8813 01

8814 89

8815 MOV A, C 79 [A] ← [C] : Carry content

8816 STA 8902 32 [8902] ← [A]

8817 02

8818 89

8819 HLT 76 Halt


31. Program to find cube root of a number


8800 LXI H, 8900 21 [H] ⇐ [HL] ← [8900]

8801 00

8802 89

8803 MVI B, 01 06 [B] ← [01]H

8804 01

8805 LOOP2 CALL CUBE CD Call subroutine "CUBE"

8806 50

8807 88

8808 CMP M BE [A] ← Compare '[M]' with [A]

8809 JZ LOOP1 CA If [Z] = 1: go to location [8810]

880A 10

880B 88 If [Z] = 0: go to location [880C]

880C INR B 34 [B] ← [B]+1

880D JMP LOOP2 C3 Go to location [8805]

880E 05

880F 88

8810 LOOP1 MOV A, B 78 [A] ← [B]

8811 STA 8FF1 32

8812 F1

8813 8F

8814 CALL 044C CD

8815 4C

Display routine

8816 04

8817 HLT 76 Halt

8850 CUBE MOV C, B 48 [C] ← [B]H

8851 MVI A, [00]H 3E [A] ← [00]H

8852 00

8853 MOV D, C 51 [D] ← [C]

8854 ADD C 81 [A] ← [A]+[C]

8855 DCR D 15 [D] ← [D]-1

8856 JNZ LOOP1 C2 If [Z] = 0 : go to location [8810]

8857 10

8858 88 [Z] = 1: go to location [8859]

8859 MOV D, A 57 [D] ← [A]

885A MVI A, 00 3E [A] ← [00]H

885B 00


885C ADD D 82 [A] ← [D] + [A]

885D DCR C 0D [C] ← [C] – [1]

885E JNZ LOOP2 C2 If [Z] = 0; go to [8805]

885F 05 If [Z] = 1; go to [8861]

8860 88

8861 RET C9

32. Program to decimal count from 00 to 99 (using DAA)


8800 LOOP2 XRA A AF [A] ← [00]

8801 LOOP1 STA 8FF1 32 [8FFI] ← [A]

8802 F1

8803 8F

8804 PUSH PSW F5 [A] to stock location

8805 CALL 044C CD

8806 4C

8807 04

8808 CALL SUB CD CALL “delay routine from (8850)H”

8809 50

880A 88

880B POP PSW F1 [A] ← stock location

880C ADI 01H C6 [A] ← [A]+1

880D 01H

880E DAA 27 Decimal Accumulator adjust

880F CPI 9AH FE Compare [A] with 99

8810 [9A]H

8811 JC LOOP1 DA If [CY] = 1 go to location [8801]H

8812 01 If [CY] = 0 go to location [8814]H

8813 88

8814 JMP LOOP2 C3 go to location [8800]H

8815 00

8816 88


8850 SUB LXI D, [FFF]H 11

8851 [FF]H

8852 [FF]H

8853 LOOP3 DCX D 1B

8854 MOV A, D 7A

8855 ORA E B3

8856 JNZ LOOP3 C2

8857 53

Delay routine for a delay of [FFFF]H

8858 88

8859 RET C9

33. Port address:

CS Hex Address Port

A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 0 0 0 0

0

1

1

0

1

0

1

40

41

42

43

A

B

C

Control word register

HARDWARE EXPERIMENTS

Waveform Generation using DAC

Block Diagram

1. Square wave generation


8800 MVI A, [80]H 3E, [80]HControl register control

word

8802 OUT [43]H D3, [43]H

8804 LOOP1 MVI A, [00]H 3E, [00]H [A] ← [00]H

8806 OUT [40]H D3, [40]H Port A : output

8808 CALL DELAY [8850] CD, 50, 88 Call delay

880B MVI A, [FF]H 3E, [FF]H [A] ← [FF]H

880D OUT [40]H D3, [40]H Port A : output

880F CALL DELAY [8850] CD, 50, 88 Call delay

8812 JMP LOOP1 C3, 06, 88


2. Delay program


8850 DELAY PUSH PSW F5 Store the [A] → stock register

8851 LXI D, [FFFF]H 11 [DE] ← [FFFF]H

8852 [FF]H

8853 [FF]H

8854 LOOP2 DCX D IB [DE] ← [DE]–1

8855 MOV A, D 7A [A] ← [D]

8856 ORA E B3 [A] ← [A] “OR” [E]

8857 JNZ LOOP2 C2 If [Z] = 0: go to location [8854]H

8858 54 If [Z] = 1: go to location [885A]H

8859 88

885A POP PSW F1 Remove the [A]& [F] ← stock register

885B RET C9 Return to main program

3. Triangular wave generation


8800 MVI A, [80]H 3E

8801 [80]H

Control word in control word

register

8802 OUT [43]H D3

8803 [43]H

8804 MVI A, [00]H 3E [A] ← [00]H

8805 [00]H

8806 LOOP1 OUT [40]H D3 Port A: Output

8807 [40]H

8808 INR A 3C [A] ← [A]+1

8809 CPI [FF]H FE [A] ← Compare [A] with [FF]H

880A [FF]H

880B JNZ LOOP1 C2 If [Z] = 0 : go to location [8805]H

880C 06 If [Z] = 1 : go to location [880E]H

880D 88

880E LOOP2 OUT [40]H D3

880F [40]H

8810 DCR A 3D [A] ← [A]–1

8811 CPI [00]H FE

8812 [00]H

8813 JNZ LOOP2 C2 If [Z] = 0: go to location [880E]H


8814 OE If [Z] = 1: go to location [8816]H

8815 88

8816 JMP LOOP1 C3

8817 06

8818 88

4. Sawtooth waveform generation


8800 MVI A, [80]H 3E, [80]H

8802 OUT [43]H D3, [43]H

Control word : control word register

8804 LOOP2 MVI A, [00]H 3E, [00]H [A] ← [00]

8806 LOOP1 OUT [40]H 3E, [40]H Port A : output

8808 INR A 3C [A] ← [A]+1

8809 CPI [FF]H FE, [FF]H [A] ← compare [A] with [FF]H

880B JNZ LOOP1 C2, 06, 88 If [Z] = 0 : go to location [8806]H

880E OUT [40]H D3, [40]H If [Z] = 1 : go to location [880E]H

8810 JMP LOOP2 C3, 04, 88

5. Staircase wave generation


8800 MVI A, [80]H 3E, 80]H

8802 OUT [43]H D3, [43]H

Control word

8804 LOOP3 MVI A, [55]H 3E, [55]H [A] ← [55]H

8806 LOOP1 OUT [40]H D3, [40]H Port A : output

8808 CALL DELAY

[8850]

CD, 50, 88 Call delay subroutine

880B ADI [55]H C6, [55]H [A] ← [A]+[55]H

880D JNC LOOP1 D2, O6, 88 [CY]=0: go to location [8806]H

[CY]=1: go to location [8810]H

8810 MVI A,[FF]H 3E, FF [A] ← [FF]H

8812 LOOP2 SUI [55]H D6, [55] [A]H ← [A]–[55]H

8814 OUT [40]H D3, [40]H Port A : output

8816 CALL DELAY CD, 50, 88 Call delay subroutine

8819 CPI [00]H FE, [00]H [A] ← compare[A] with [00]H

881B JNZ LOOP2 C2, 12, 88 [Z] = 0: go to location [8812]H

[Z] = 1: go to location [881E]H

881E JMP LOOP3 C3, 04, 88 Go to location [8804]H


6. Trapezoidal waveform generation


8800 MVI A, [80]H 3E, [80]H

8802 OUT [43]H D3, [43]H

Control word

8804 MVI A, [00]H 3E, [00]H [A] ← [00]

8806 LOOP1 OUT [40]H D3, [40]H Port A : output

8808 INR A 3C [A] ← [A]–1

8809 CPI [FF]H FE, [FF]H [A] ← Compare [A] with [FF]H

880B JNZ LOOP1 C2, 06, 88 [Z] = 0: go to location [8806]H

[Z] = 1: go to location [880E]H

880E CALL DELAY CD, 50, 88 Call delay subroutine

8811 LOOP2 DCR A 3D [A] ← [A]–1

8812 OUT [40]H D3, [40]H Port A: output

8814 CPI [00]H FE, [00]H [A] ← Compare [A] with [00]H

8816 JNZ LOOP2 C2, 11, 88 [Z] = 0: go to location [8811]H

[Z] = 1: go to location [8820]H

8819 CALL DELAY CD, 50, 88 Call delay subroutine

882C JMP LOOP1 C3, 06, 88 Go to location [8806]H

7. Sinewave generation


8800 MVI A, [80]H 3E, [80]H

8802 OUT [43]H D3, [43]H

Control word

8804 LOOP2 MVI C, [48]H 0E, [48]H [C] ← [48]

8806 LXI H, 8900 21, 00, 89 [M] ⇐ [HL] ← [8900]H

8809 LOOP1 MOV A, M 7E [A] ← [M]

880A OUT [40]H D3, [40]H Port A : output

880C INX H 23 [HL] ← [HL]+1

880D DCR C 0D [C] ← [C]–1

880E JNZ LOOP1 C2, 09, 88 [Z] = 0: go to location [8809]H

[Z] = 1: go to location [8811]H

8811 JMP LOOP2 C3, 04, 88 Go to location [8804]H


2

[FF]]sin[1:datacodeHex H

θ+

θθθθ

(degree)sin θθθθ Address

0 0 [75]H 8900

5 0.087 [8A]H 8901

10

.

.

.

360º

Matrix Type Keyboard Interface

Block Diagram

Address Label Mnemonics Operand Hexcode Comment

8800 MVI A, [92]H 3E, [92]H

8802 OUT [43]H D3, [43]H

Control word

8804 BACK CALL KEY CD, 11, 88 Call "KEY" subroutine

8807 MOV A, C 79 [A]←[C]

8808 STA 8FF1 32, F1, 8F

880B CALL UPDDT C2, 4C, 04 Data field display routine

880E JMP BACK C4, 04, 88

8811 KEY MVI D, [02]H 16, [02]H [D] ← [02]H

8813 MVI C, [10]H 0E, [10]H [C] ← [10]H

8815 MVI B, [04]H 06, [04]H [B] ← [04]H

8817 REPT MOV A, B 78 [A] ← [B]

8818 OUT [42]H D3, [42]H Output

881A RRC OF Rotate right the [A] by a bit

881B MOV B,A 47 [B] ← [A]

881C IN [40]H DB, [40]H Input [A]

881E CPI [00]H FE, [00]H [A] ← Compare [00]H with [A]

8820 JNZ NXT

KEY

C2, 31, 88 If [Z] = 0: go to location [8831]

If [Z] = 1: go to location [8820]

8823 MOV A, C 79 [A] ← [C]

8824 SUI [08]H D6, [08]H [A] ← [A]–[08]H

2

[FF]sin][1:codeHex H

+


8826 MOV C, A 4F [C] ← [A]

8827 DCR D 15 [D] ← [D]–1

8828 MOV A, D 7A [A] ← [D]

8829 CPI [FF]H FE, [FF]H [A] ← Compare [A] with [FF]H

882B JNZ REPT C2, 17, 88 If [Z] = 0: go to location [8817]

[Z] =1: go to location

882E JMP KEY C2, 11, 88 Go to location on [8811]

8831 NXT KEY RRC 0F Rotation right [A] by a bit

8832 RC D8

8833 PUSH PSW F5 Stock register ← [A]

8834 MOV A, C 79 [A] ← [C]

8835 ADI [01]H C6, [01]H [A] ← [A]+[01]H

8837 MOV C, A 4F [C] ← [A]

8838 POP PSW FI [A] ← Stock register

8839 JMP NXT KEY C3, 31, 88 Go to location [8831]

Control of Stepper Motor

Block Diagram


8800 MVI A, [80]H 3E, [80]H

8802 OUT [43]H D3, [43]H

Control word

8804 MVI A, [88]H 3E, [88]H [A] ← [88]H

8806 BACK OUT [40]H D3, [40]H Port A → output

8808 CALL Delay C0, 50, 88 Call “delay” routine

880B RRC OF rotate the [A] right

880C JMP BACK C3, 06, 88 go to location 8806

8800 DELAY PUSH PSW F5 Stock register ← [A]

8851 LXI H, [0001] 21, 01, 00 [HL] ← [0001]H

8854 LOOP2 LXI D, FFFF 11, FF, FF [DE] ← [FFFF]H

8857 LOOP1 DCX D IB [DE] ← [DE] – 1

8858 MOV A, D 7A [A] ← [D]

8859 ORA E B3 [A] ← [A] “OR” [E]


885A JNZ LOOP1 C2, 57, 88 If [Z] = 0 : go to location 8857

885D DCX H 2B If [Z] = 1 : go to location 8850

885E MOV A, H 7C [HC] ← [HL] – 1

885F ORA L B5 [A] ← [A] “OR” [L]

8860 JNZ LOOP2 C2, 54, 88 If [Z] = 0 : go to location [8854]

If [Z] = 1 : go to location [8864]

8863 POP PSW F1 [A] ← stock register

8864 RET C9 Return

Note: To change the direction of stepper motor rotation, change the Mnemonic RRC (OF) to RLC (07).

Combined

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