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Block Diagram Overview PAN-XMC-ZYNQ+ is a Vita 42.3 compliant XMC module based on the Xilinx Zynq UltraScale+ MPSoC equipped with a slot for Front I/O AXM modules from Acromag. The Zynq UltraScale+ integrates a Quad-core ARM Cortex-A53 (up to 1.5 GHz) ba- sed Application Processing Unit ( APU), a Dual-core ARM Cortex-R5 (up to 600MHz) based Real-Time Processing Unit (RPU), a ARM Mali (up to 667 MHz) based Gra- phic Processing Unit (GPU) and an UltraScale+ Programmable Logic (PL) in a single device. It also includes on-chip memory, external memory interfaces, and a rich set of pe- ripheral connectivity interfaces. The first version of the board is equipped with a XCZU9EG-1FFVC900 device tightly coupled with 4GB of 64-bit + ECC of DDR4 Processing System (PS) memory running at up to 2400Mb/s. Also a private memory of 1GB 32-bit DDR4 is provided for the Programming Logic (PL) application. For I/O interfaces, the board uses XMC P4 and P6 connectors also an on-board AXM Front I/O Mezzanine Module slot compliant to the Acromag specification, al- lowing a wide range of applications. PanaTeQ May 2016 Version Key Features Vita 42.3 compliant XMC Xilinx Zynq UltraScale+ MPSoC SoC 4-Core ARM53 + 2-Core ARM R5 + GPU Mali-400 PCIe x4 Gen1 / PCIe x1 Gen2 4GB DDR4 72-bit PS Memory 1GB DDR4 32-bit PL Memory 2x 128MB NOR SPI eMMC 64GB , MRAM 512KB 2x 1000 BaseT, 2x USB 2.0 1x SATA, 1x Display Port 2x RS-232/422/485 AXM Front I/O Mezannine Slot 30x LVDS 4x GTH on AXM PAN-XMC-ZYNQ+ Xilinx Zynq UltraScale+ XMC with AXM Front I/O Slot www.panateq.com Typical Applications Video and Signal Real-Time Processing Multi-Axes Motor Controller Software Defined Radio (SDR) RADAR/LIDAR High Speed Data Networking AXM-A30 Two 16-bit 105MHz A/D channels Acromag’s AXM Modules AXM-D0x Digital Extension Modules QSPI NOR FLASH DDR4-2400 DDR4-2400 GETH PHY APU Quad-Core ARM Cortex-A53 Up to 1.5GHz SRAM 256KB RGMII GETH MAC1 SPI Master USB 2.0 ULP I2C GETH PHY RGMII XMC P4 Connector ETH1 DATA[15:0] DATA[31:16] QSPI NOR FLASH eMMC eMMC 64GB TERM RTC DDR4-2400 TERM AXM Connector Programmable Logic UltraScale+ Memory DDR4 Controller Xilinx Zynq UltraScale+ SoC XCZU6EG XCZU9EG XCZU15EG FFVB900 31x31 mm GETH MAC2 DDR4-2400 DDR4-2400 DATA[48:17] DATA[63:49] DDR4-2400 DATA[71:64] RPU Dual-Core ARM Cortex-R5 Up to 600MHz GPU ARM Mali-400 Up to 667MHz DATA[15:0] 30x LVDS 4x GTH 4x CLK ETH0 2x UART PCIe x1 Gen2 Display Port 2x SATA 3.1 NVRAM USB Hub USB0 USB1 RS-232 RS-422 RS-485 COM1 COM2 2x UART PCIe Gen1/Gen2 RC/EndPoint PCIe Gen2 Switch PCIe Lan0 XMC P5 Connector PCIe Lan1 PCIe Lan2 PCIe Lan3 XMC P6 Connector 1x SATA 3.1 8x GTH DDR4-2400 DATA[31:16]
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COM1COM2 PAN XMC ZYNQ+ Xilinx Zynq ….pdf · Block Diagram Overview PAN-XMC-ZYNQ+ is a Vita 42.3 compliant XMC module based on the Xilinx Zynq UltraScale+ MPSoC equipped with …

Aug 18, 2018

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Page 1: COM1COM2 PAN XMC ZYNQ+ Xilinx Zynq ….pdf · Block Diagram Overview PAN-XMC-ZYNQ+ is a Vita 42.3 compliant XMC module based on the Xilinx Zynq UltraScale+ MPSoC equipped with …

Block Diagram

Overview PAN-XMC-ZYNQ+ is a Vita 42.3 compliant XMC module based on the Xilinx Zynq

UltraScale+ MPSoC equipped with a slot for Front I/O AXM modules from Acromag.

The Zynq UltraScale+ integrates a Quad-core ARM Cortex-A53 (up to 1.5 GHz) ba-

sed Application Processing Unit (APU), a Dual-core ARM Cortex-R5 (up to 600MHz)

based Real-Time Processing Unit (RPU), a ARM Mali (up to 667 MHz) based Gra-

phic Processing Unit (GPU) and an UltraScale+ Programmable Logic (PL) in a

single device.

It also includes on-chip memory, external memory interfaces, and a rich set of pe-

ripheral connectivity interfaces.

The first version of the board is equipped with a XCZU9EG-1FFVC900 device

tightly coupled with 4GB of 64-bit + ECC of DDR4 Processing System (PS) memory

running at up to 2400Mb/s. Also a private memory of 1GB 32-bit DDR4 is provided

for the Programming Logic (PL) application.

For I/O interfaces, the board uses XMC P4 and P6 connectors also an on-board

AXM Front I/O Mezzanine Module slot compliant to the Acromag specification, al-

lowing a wide range of applications.

PanaTeQ May 2016 Version

Key Features Vita 42.3 compliant XMC

Xilinx Zynq UltraScale+ MPSoC

SoC 4-Core ARM53 + 2-Core ARM R5 + GPU Mali-400

PCIe x4 Gen1 / PCIe x1 Gen2

4GB DDR4 72-bit PS Memory

1GB DDR4 32-bit PL Memory

2x 128MB NOR SPI

eMMC 64GB , MRAM 512KB

2x 1000 BaseT, 2x USB 2.0

1x SATA, 1x Display Port

2x RS-232/422/485

AXM Front I/O Mezannine Slot

30x LVDS 4x GTH on AXM

PAN-XMC-ZYNQ+ Xilinx Zynq UltraScale+ XMC with AXM Front I/O Slot

www.panateq.com

Typical Applications

Video and Signal Real-Time Processing

Multi-Axes Motor Controller

Software Defined Radio (SDR)

RADAR/LIDAR

High Speed Data Networking

AXM-A30 Two 16-bit 105MHz A/D channels

Acromag’s AXM Modules

AXM-D0x Digital Extension Modules

QSPINOR FLASH

DDR4-2400

DDR4-2400

GETH PHY

APUQuad-Core

ARM Cortex-A53Up to 1.5GHz

SRAM256KB

RGMII

GETHMAC1

SPI Master

USB 2.0ULP

I2C

GETH PHY

RGMII

XMC P4 Connector

ETH1

DATA[15:0]

DATA[31:16] QSPINOR FLASH

eMMC eMMC64GB

TERM

RTC

DDR4-2400

TERMAXM

Connector

Programmable LogicUltraScale+

Memory DDR4Controller

Xilinx Zynq UltraScale+ SoCXCZU6EGXCZU9EG

XCZU15EG

FFVB900 31x31 mm

GETHMAC2

DDR4-2400

DDR4-2400

DATA[48:17]

DATA[63:49]

DDR4-2400 DATA[71:64]

RPUDual-Core

ARM Cortex-R5Up to 600MHz

GPU ARM Mali-400Up to 667MHz

DATA[15:0]

30x LVDS

4x GTH

4x CLK

ETH0

2x UART

PCIe x1 Gen2

Display Port

2x SATA 3.1

NVRAM

USB Hub

USB0 USB1

RS-232RS-422RS-485

COM1COM2

2x UART

PCIe Gen1/Gen2RC/EndPoint

PCIe Gen2Switch

PCIe Lan0

XMCP5 Connector

PCIe Lan1

PCIe Lan2

PCIe Lan3

XMCP6 Connector

1x SATA 3.1

8x GTH

DDR4-2400 DATA[31:16]

Page 2: COM1COM2 PAN XMC ZYNQ+ Xilinx Zynq ….pdf · Block Diagram Overview PAN-XMC-ZYNQ+ is a Vita 42.3 compliant XMC module based on the Xilinx Zynq UltraScale+ MPSoC equipped with …

Board Specifications XMC InterfacesXMC Interfaces

VITA 42.3 Specification compliant

XMC P5: 4 lanes PCIe Gen1 or 1 Lane PCIe Gen2

XMC P5: 4x SerDes GTH @16.3 Gb/s directly connected to ZynQ Programming Logique

XMC P4: 2x 1000BaseT, 2x USB 2.0, 2x RS-232/422/485 XMC P6: 1x SATA 3.1, 1x Video Display Port, 8x SerDes GTH

XMC P5: IPMI EEPROM, Temperatures, Voltages, JTAG

Xilinx Zynq UltraScale+ MPSoC (16nm Technology)Xilinx Zynq UltraScale+ MPSoC (16nm Technology)

Supported Devices:XVZU6EG-1FFVC900 / XCZU9EG-1FFVC900 / XCZU15EG-1FFVC900

Processing System : Quad-Core ARM A53, Dual-Core ARM R5, GPU Mali-400, 2x SATA, 2x USB, 4x GETH MACs

Programmable Logic: 214K LUTs (ZU6EG) / 274K LUTs (ZU9EG) / 341K LUTs (ZU15EG)

On-Chip Memories: 25.1Mb (ZU6EG) / 32Mb (ZU9EG) / 57.7Mb (ZU15EG)

DSP Slices: 1973 (ZU6EG) / 2520 (ZU9EG) / 3528 (ZU15EG)

SerDes: 24 full duplex, high performance, GTH multi-gigabit SerDes tranceivers @ up to 16.3 Gb/s

2x 10-bit, 1MSPS ADCs for System Monitoring

Supported by PanaTeQ’s FPGA Development Kit (PAN-FDK)

External MemoriesExternal Memories

4GB DDR4-2400 Processor System memory, 64-bits data, 8-bit ECC 1GB DDR4-2400 Programmable Logic memory, 32-bits data 2x 128MB of QSPI NOR Flash memory for booting FPGA Zynq and Firmware 512KB of SPI MRAM (NVRAM) eMMC for up to 64GB NAND Flash memory

Front I/O AXM SlotFront I/O AXM Slot

Fully compliant to Acromag’s AXM Mezzanine Module Specification. 4 high-performance GTH SerDes @16.3 Gb/s to/from FPGA Zynq 30 LVDS pairs to/from FPGA Zynq 2 clocks to FPGA Zynq 2 clocks from FPGA Zynq

Envionmental SpecificationsEnvionmental Specifications

Commercial Ruggudized 0-50C Conduction Cooled –40C to 70C at Thermal Interface

Pre-Ordering Information

PAN-XMC-ZYNQ+-A : XCZU9EG Commercial Ruggudized

PAN-XMC-ZYNQ+-A-CC : XCZU9EG Conduction Cooled

PanaTeQ Engineering At Your Service

Contact Information

[email protected]

Page 3: COM1COM2 PAN XMC ZYNQ+ Xilinx Zynq ….pdf · Block Diagram Overview PAN-XMC-ZYNQ+ is a Vita 42.3 compliant XMC module based on the Xilinx Zynq UltraScale+ MPSoC equipped with …

Xilinx Zynq UltraScale+ MPSoC Processing System Highlights

Applications processing unit (APU) with quad-core ARM® Cortex™-A53 processors:

Next-generation ARMv8 architecture supporting 32- or 64-bit data widths

Ideal for Linux and bare-metal SMP/AMP application systems

Real-time processing unit (RPU) with dual-core ARM Cortex-R5 processors:

Low-latency, highly deterministic performance APU offloading

New integrated hardened multimedia blocks:

Graphics processing unit (GPU) [ARM Mali™-400MP2]

4Kx2K 60fps video encoder/decoder (VCU) [in select devices]

4Kx2K 30fps DisplayPort interface

New integrated high-speed peripherals:

PCIe® Gen1 or Gen2 root complex and integrated Endpoint block in x1, x2, and x4 lanes

USB 3.0/2.0 with host, device, and OTG modes

Gigabit Ethernet with jumbo frames and precision time protocol

SATA 3.1 host

Dedicated quad transceivers up to 6Gb/s

General and boot peripherals:

CAN, I2C, QSPI, SD, eMMC, and NAND flash interfaces

GPIO, UART, and trace ports

6-port DDR controller with ECC, supporting x32 and x64 DDR3, DDR3L, LPDDR3, LPDDR4, DDR4

Integrated platform management unit (PMU) supporting multiple power domains

Integrated configuration security unit (CSU)

TrustZone support

Peripheral and memory protection

PanaTeQ Engineering At Your Service