Codelink Using Embedded Code for Verification Stimulus
jpk Codelink March 052
Copyright ©1999-2005, Mentor Graphics.
Functional Verification of ICs & ASICs
On average 5.6 engineers spend 11 weeks developing and 9 weeks running directed tests
They write 267 tests and import/reuse 113 which detect 106 design errors
Yet 59% of designs fail first silicon and a functional flaw is the cause 90% of the time
Source: Collett International 2005
jpk Codelink March 053
Copyright ©1999-2005, Mentor Graphics.
Complex Designs and the Verification Gap
* Source: SIA Roadmap 2001
Verification Gap
Design Gap
jpk Codelink March 054
Copyright ©1999-2005, Mentor Graphics.
Verification Methods
Directed Tests Coverage Driven Verification (CDV) Assertion-Based Verification (ABV)
jpk Codelink March 055
Copyright ©1999-2005, Mentor Graphics.
Directed Tests
Module being Verified
Stimulus Results Check
jpk Codelink March 056
Copyright ©1999-2005, Mentor Graphics.
Coverage Driven Verification
Module being Verified
Stimulus Results Check
jpk Codelink March 057
Copyright ©1999-2005, Mentor Graphics.
ModelSim Code Coverage Measures language coverage
— Have you executed each: Statement Branch Condition Expression Or Toggled each bit
— Impossible to relate to functional specifications or test plans
— Does not guarantee bug free
Best used at block level— Easier to exercise code aspects— Ensures blocks are tested &
ready for integration
Built-in ModelSim— Low overhead— Easy to use
jpk Codelink March 058
Copyright ©1999-2005, Mentor Graphics.
Assertion Based Verification
Module being Verified
Stimulus Results Check
jpk Codelink March 059
Copyright ©1999-2005, Mentor Graphics.
0-In Assertion Based Verification
System
Interconnect 0
AM
BA
Bus
DMA
DMA
RAM
RAM
RAM
RAM
EthernetController
SDRAMController
SD
RA
M
EncryptionEngine
PC
I Bus
PH
YPowerful formal verification that targets
Verification Hot Spots (80/20 Rule)
Powerful formal verification that targets Verification Hot Spots (80/20 Rule)
checker
Arbiter
Mu
ltiple
clock d
om
ain
sM
ultip
le clo
ck do
ma
ins
PCIBridge
μCμC
PCIBridge
Library of Standard Checkers— AMBA Bus Checker
Assertion Synthesis Finds Verification “Hot Spots”
— Focus on error prone areas
jpk Codelink March 0510
Copyright ©1999-2005, Mentor Graphics.
Verification Requires Stimulus
ABV and CDV require dynamic simulations and stimulus
— Directed Tests— Constrained Random Tests
For modules interacting with processors— Use embedded code to drive stimulus
Easy to create Realistic stimulus
jpk Codelink March 0511
Copyright ©1999-2005, Mentor Graphics.
Verification Strategy
Maximum Coverage, Minimum Simulation
Directed Tests— Basic coverage, corner conditions
Constrained Random Tests— Exercise unexpected combinations
Code as stimulus— Focus on typical system operation— Compliments ABV and CDV
jpk Codelink March 0512
Copyright ©1999-2005, Mentor Graphics.
Codelink Usage Model
Early in the design Cycle— Used as a bus functional model
Middle of design Cycle— Generates AMBA stimulus for block level verification
(BFM)— Can drive ABMA cycles as constrained random
stimulus— Use small programs as directed module tests
Late in the design Cycle— Replaces full-functional model in regression tests
where processor is present
jpk Codelink March 0513
Copyright ©1999-2005, Mentor Graphics.
Codelink AMBA BFM
Bool my_test(void) { unsigned char err;
WriteByte(0x80000008, 0xFF); WriteLong(0x80000100, 0x12340000);
while(ReadByte(0x80000204)) { err = ReadByte(0x80000208); if (err == 0x1F) return FALSE; }
return TRUE;}
jpk Codelink March 0514
Copyright ©1999-2005, Mentor Graphics.
Constrained Random AMBA Traffic
active = 80;idle = 20;
cr_struct[] = { { 10, 0x00000000, 0x0000FFFF, 4, {read_l, write_l}, {50, 50}}, { 30, 0x40000000, 0x40000FFF, 8, {read_b, write_l}, {80, 20}}, { 60, 0x80000000, 0x8003FFFF, 1, {read_b, write_b}, {35, 65}}};
Compile into CR generator Random Bus traffic is generated based on values in CR_struct Address ranges can may overlap Unlimited number of address ranges
Percent of time bus will be activePercent of time bus will be idle
Percent of time this address range will be accessedStart of Address RangeEnd of Address RangeBus Cycle AlignmentBus Cycles to DrivePercent of Cycles to Drive
jpk Codelink March 0515
Copyright ©1999-2005, Mentor Graphics.
Types of Code
Small functions as directed tests— Specific module function— If you are using ARM’s DSM you are already doing
this Diagnostics
— Exhaustively tests interfaces, some functionality Driver code
— Exhaustively tests functionality, some interface Application Code
— Tests typical operation
Different Types of Code have different coverage profiles
Different Types of Code have different coverage profiles
jpk Codelink March 0516
Copyright ©1999-2005, Mentor Graphics.
Improve Test Coverage with Software
Orthogonal view of design functionality— software is developed against the specification
without detailed knowledge of the hardware Real-world stimulus
— Boot code— Hardware diagnostics— Device drivers
Used on first silicon, why not pre-tapeout? It’s free stimulus (well, almost)
jpk Codelink March 0517
Copyright ©1999-2005, Mentor Graphics.
Manually Linking Software with Simulation
software Developer
Must convert software binary to memory image file No source-level debug Slow, ~ 1 to 10 instructions/sec
Standards:VHDL, Verilog, SystemVerilog, PSL, SystemC
TestbenchAutomation
Coverage-Driven
Verification
Integrated Debug
Environment
Assertion-Based
Verification
System-LevelDesign
Verification Engineer
jpk Codelink March 0518
Copyright ©1999-2005, Mentor Graphics.
Codelink Automates Software Testbenches
Codelink
Loads software binary Full source-level debug Significantly faster than full-functional model
Standards:VHDL, Verilog, SystemVerilog, PSL, SystemC
TestbenchAutomation
Coverage-Driven
Verification
Integrated Debug
Environment
Assertion-Based
Verification
System-LevelDesign
software Developer
jpk Codelink March 0519
Copyright ©1999-2005, Mentor Graphics.
Codelink Benefits
Increase verification coverage with minimal effort
Simple for hardware engineer to use
— Drive from ModelSim
— No New GUI
Code is reusable in later design phases
jpk Codelink March 0520
Copyright ©1999-2005, Mentor Graphics.
Codelink Setup
Instantiate Codelink ARM model
Invoke ModelSim, as usual
Point Codelink to the software object file
Specify code, data and stack memory ranges
Run ModelSim, as usual
jpk Codelink March 0521
Copyright ©1999-2005, Mentor Graphics.
Codelink SetupSpecify Memory Regions Driven from ModelSim
Locate software executable
jpk Codelink March 0522
Copyright ©1999-2005, Mentor Graphics.
Codelink Architecture
Clock-Cycle AccurateARM Processor Model
Fast Access Memory
Data Transfer & Steering
Synchronization & Control
Codelink
Fast Access Memory supports 100K cycles/second
Hardware I/O cycles run 1 to 10 cycles/second
jpk Codelink March 0523
Copyright ©1999-2005, Mentor Graphics.
Source-Level Software Debug
Source & assembly level debug
Register & variable inspection
Invoke minimized if debug is not required
jpk Codelink March 0524
Copyright ©1999-2005, Mentor Graphics.
Bus Cycles
LDR R5, [R9]; -- Read ASIC RegisterLDR R3, [R10+FLUX]; -- Get flux const.ADD R3, R3, R5; -- Add flux capacitanceAND R3, R3, [R10+MASK]; -- Mask out high bitsSUB R3, R3, [R10+DIFF]; -- Subtract differentialLDR R6, [R10+COSW]; -- Get Cosworth valueXOR R3, R3, R6 -- Apply Cosworth filterADD R9, R9, R4; -- Compute register offsetSTR R5, [R9]; -- Write Register
HW READ HW WRITEFETCH HW READ FETCH DATA READFETCH FETCH DATA READFETCH DATA READFETCH DATA READFETCH FETCHFETCHHW WRITE
jpk Codelink March 0526
Copyright ©1999-2005, Mentor Graphics.
Faster Simulation
Waveform View
Fetch I/O Fetch Read Fetch Fetch Read Fetch Read Fetch Read Fetch Fetch Fetch I/O I/O I/O
LDR R5, [R9]; -- Read ASIC RegisterLDR R3, [R10+FLUX]; -- Get flux const.ADD R3, R3, R5; -- Add flux capacitanceAND R3, R3, [R10+MASK]; -- Mask out high bitsSUB R3, R3, [R10+DIFF]; -- Subtract differentialLDR R6, [R10+COSW]; -- Get Cosworth valueXOR R3, R3, R6 -- Apply Cosworth filterADD R9, R9, R4; -- Compute register offsetSTR R5, [R9]; -- Write Register
jpk Codelink March 0527
Copyright ©1999-2005, Mentor Graphics.
Codelink Acceleration Factor
Codelink accelerates memory cycles Ratio of memory to simulation cycles varies across
phases of software execution
Load Registers Unload Registers Evaluate ResultsPropagate Values
Memory Intensive Memory Intensive Memory ExclusiveSimulation Intensive
10x to 100x 1x 10x to 100x 1,000x
Codelink Acceleration Factor
jpk Codelink March 0528
Copyright ©1999-2005, Mentor Graphics.
Codelink Summary
Improve chance of first silicon success
— Enhance coverage without writing more tests
Simple setup and fast execution
Source-level software debug
Verify software prior to tapeout