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TMH 3. John P Hayes, “ Computer Organization”, McGraw Hill • REFERENCE1. P Pal Chaudhry, ‘ Computer Organization & Design’,
PHI 2. William Stalling, “ Computer Organization”, PHI 3. Patterson, Computer Organisation and Design,
Elsevier Pub. 2009
Why Study CO
• To understand why an algorithm is infeasible, or to understand why the implementation of a feasible algorithm is running too slowly.
• if you want to write compilers, you must understand the hardware environment within which the compiler will function.
• To design peripheral equipment or the software that drives peripheral equipment, you must know every detail of how a particular computer deals with its input/output (I/O)
• Computer organization addresses issues such as control signals (how the computer is controlled), signaling methods, and memory types.
• It encompasses all physical aspects of computer systems. It helps us to answer the question: How does a computer work?
Computer Architecture
• Structure and behavior of the computer system• Logical aspects of system implementation as seen by
the programmer. • Computer architecture includes many elements such as
instruction sets and formats, operation codes, data types, the number and types of registers, addressing modes, main memory access methods, and various I/O mechanisms.
• The architecture of a system directly affects the logical execution of programs.
• Studying computer architecture helps us to answer the question: How do I design a computer?
Architecture & Organization
• Architecture is those attributes visible to the programmer– Instruction set, number of bits used for data representation, I/O
mechanisms, addressing techniques.
– e.g. Is there a multiply instruction?
• Organization is how features are implemented. – Refers to the operational units and their interconnections that
realize the architectural specifications
– Control signals, interfaces, memory technology.
– e.g. Is there a hardware multiply unit or is it done by repeatedaddition?
• First Generation (1945 - 1955)– Programs and data located in same memory– Assembly language was used to write programs– Vacuum Tube Technology for performing basic
processing – Mercury delay line memory was used– Type writers as I/O devices
• Second Generation (1955 – 1965)– Transistor replaced vacuum tubes– Magnetic core memories and magnetic
storage devices were more widely used– High level language such as FORTRAN was
developed– Compilers were developed– Separate I/O processors were developed
along with CPU– IBM became major manufacturer
History of Computer
• Third Generation ( 1965-1975)– Many transistors on a single chip (IC) enabled lower cost , faster
processors and memory elements– IC memories replaced magnetic core memories– Introduction of micro-programming , parallelism , pipelining– Effective time sharing in operating system– Development of Cache & Virtual memory
• Fourth Generation (1975-1996)– Still advancement in IC technology (VLSI) that is Very Large Scale
Integration– Microprocessor concept - Motorola, Texas Instruments were the major
companies– Parallelism, Pipelining , Cache , Virtual Memories evolved to produce
The Von Neumann ModelThe Input Unit provides instructions and data to the system, which are subsequently stored in the Memory Unit . The instructions and data are processed by the Arithmetic and Logic Unit (ALU) under the direction of the Control Unit . The results are sent to the Output Unit . The ALU and control unit are frequently referred to collectively as the central processing unit (CPU)
The stored program is the most important aspect of the Von Neumann model. A program is stored in the computer’s memory along with the data to be processed.
The System Bus ModelThis model partitions a computer system into three subunits: CPU, Memory, and Input/Output (I/O). This refinement of the von Neumann model combines the ALU and the control unit into one functional unit, the CPU. The input and output units are also combined into a single I/O unit.
Most important to the system bus model, the communications among the components are by means of a shared pathway called the system bus , which is made up of the data bus (which carries the information being transmitted), the address bus (which identifies where the information is being sent), and the control bus (which describes aspects of how the information is being sent, and in what manner).
• Combinational and sequential circuits can be used to create simple digital systems.
• These are the low-level building blocks of a digital computer.• Registers + Operations performed on the data stored in them = Digital Module• Modules are interconnected with common data and control paths to form a digital
computer system
• Simple digital systems are frequently characterized in terms of– the registers they contain, and– the operations that they perform.
• Typically,– What operations are performed on the data in the registers– What information is passed between registers
MICROOPERATIONS (1)Register Transfer Language
• The operations on the data in registers are called microoperations.
• The functions built into registers are examples of microoperations– Shift
– Load– Clear
– Increment– …
• The result of the operation may replace the previous binary information of a register or may be transferred to another register.
• Micro-operations are the basis for microprocessors. An instruction is fetched from memory, decoded and executed by performing a sequence of microoperations.
• A microprocessor performs the micro-operations in order to realize the instruction.
MICROOPERATION
An elementary operation performed (during one clock pulse), on the information stored in one or more registers
-Information stored in these registers-Can be binary, BCD, Alphanumeric characters or cont rol info
- Microoperations set
•Set of allowable microoperations provided by the orga nization of the computer
•Depend on the type of information encountered
- Control signals that initiate the sequence of micr ooperations(to perform the functions)
• Definition of the (internal) organization of a comp uter
Register Transfer Language
ORGANIZATION OF A DIGITAL SYSTEMRegister Transfer Language
The microoperations performed on the information sto red in registers depend on the type of data that reside in the registers. The binary information commonly found in registers of digital computers can be classified into three c ategories:
1. Numerical data such as binary numbers or binary-c oded decimal numbers used in arithmetic computations.
2. Nonnumerical data such as alphanumeric characters or other binary-coded symbols used for special applications.
3. Instruction codes, addresses, and other control i nformation used to specify the data-processing requirements in the system.
• The same clock controls the circuits that generate the control functionand the destination register
• Registers are assumed to use positive-edge-triggered flip-flops
Simultaneous Register Transfers
• 1- When signal P is asserted, the contents of B are copied intoboth registers A and C. Note that the order in which the statement is written does not matter. If the transfer from B to C was written first, the result would be the same
• 2 - two registers are loaded simultaneously from differentsources.
1 2
Illegal Simultaneous Transfers
• Example of an illegal operation, since A must be loaded with two different values simultaneously.
BASIC SYMBOLS FOR REGISTER TRANSFERS
Capital letters Denotes a register MAR, R2& numerals
Parentheses () Denotes a part of a register R2(0- 7), R2(L)
Arrow ←←←← Denotes transfer of information R2 ←←←← R1
Colon : Denotes termination of control function P:Comma , Separates two micro-operations A ←←←← B, B ←←←← A
There are occasions when a destination register rec eives information from two sources, but evidently not at the same time.
Consider the two statements:
T1: C ���� A
T5 : C ���� B
The connection of two source registers to the same destination register cannot be done directly, but requires a mu ltiplexer circuit to select between two possible paths.
For registers with four bits each, we need a quadru ple 2-to-1 line multiplex, in order to select either register A or register B. When T5 = 1, register B is selected, but when T1 = 1, regis ter A is selected (because T5 must be O when T1 is 1).
The multiplexer and the load input of register C ar e enabled every time T1 or T5 occurs. This causes a transfer of inf ormation from the selected source register into the destination regis ter.
CONNECTING REGISTRSRegister Transfer
Connecting Registers with Multiplexers
P: A ���� BQ: A ���� CR: B ���� DS: C ���� AT: D ���� CU: D ���� B
The multiplexer selects one of the four registers as the source register. Control lines for the mux are driven by external circuitry. The data is made available to all registers, but only one actually loads the data. Again, external hardware generates load signals for the four registers such that no more than one isactive at any given time.
CONNECTING REGISTRSRegister Transfer
• In a digital system with many registers, it is impractical to have data and control lines to directly allow each register to be loaded with the contents of every possible other registers
• To completely connect n registers � n(n-1) lines
• O(n2) cost– This is not a realistic approach to use in a large digital system
• Instead, take a different approach
• Have one centralized set of circuits for data transfer – the bus
• Have control circuits to select which register is the source, and which is the destination
• The transfer of information from a bus into one of many destination registers can be accomplished by connecting the bus lines to the inputs of all destination registers and activating the load control of the particular destination register selected.
• The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the statement. When bus is included in the statement we write:
BUS � C, R1� BUS (however it is R1� C)
Tri State Bus Buffers
• A three-state gate is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate.
• The third state is called high impedance state• The high impedance state behaves like an open circuit which
means that the output is disconnected and does not have a logic significance.
Normal Input A
Control Input C
Output Y=A if C=1
High-impedance if C=0
Bus and Memory Transfers: Three-State Bus Buffers cont.
A
C=1
B A B
A
C=0
B A B
Buffer
Open Circuit
Connecting registers with 3-state buffers
2x4
decoder
s1s0
0123
Select
Enable E
A0
B0
C0
D0
Bus line for bit 0
• To construct a common bus for 4 registers of n bits each using 3-state buffers, we need n circuits with four buffers in each, as follows:
• External circuitry enables at most one of the tri-state buffers to pass its data through to the inputs of the registers. The data is made available to all registers, but only one actually loads the data. The load signals for the four registers are exactly the same as in the previous example. This makes sense since the registers only know that they are to read in data from the bus. They don’t care how the data got onto the bus in the first place.
• The primary advantage of using buffers rather than multiplexers is the reduced current load on the circuit.
BUS TRANSFER IN RTLBus and Memory Transfers
• Depending on whether the bus is to be mentioned explicitly or not, register transfer can be indicated as either
or
• In the former case the bus is implicit, but in the latter, it isexplicitly indicated
R2 ← ← ← ← R1
BUS ← ← ← ← R1, R2 ←←←← BUS
MEMORY (RAM)Bus and Memory Transfers
• Memory (RAM) can be thought as a sequential circuits containing some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the following– n data input lines
– n data output lines– k address lines
– A Read control line– A Write control line
data input lines
data output lines
n
n
kaddress lines
Read
Write
RAMunit
MEMORY TRANSFERBus and Memory Transfers
• Collectively, the memory is viewed at the register level as a device, M.
• Since it contains multiple locations, we must specify which address in memory we will be using
• This is done by indexing memory references
• Memory is usually accessed in computer systems by putting the desired address in a special register, the Memory Address Register (MAR, or AR)
• When memory is accessed, the contents of the MAR get sent to the memory unit’s address lines
s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1= x ⊕ y ⊕ cn-1 = (x ⊕ y) ⊕ cn-1
x
y
cn-1x
y
cn-1
cn s
c = xy s = xy’ + x’y= x ⊕ y
xy c
s
xy
cn-1
S
cn
Full Adder
0 0 0 00 1 0 11 0 0 11 1 1 0
x y c s
x y cn-1 cn s0
0
10
0
1
11
0
1
01
1
0
10
Binary Adder
• The binary adder is constructed with full-adder circuits connected in cascade, with the output carry from one full-adder connected to the input carry of the next full-adder
• n-bit binary adder requires n full adders
B3 A3 B2 A2 B1 A1 B0 A0
C0C1C2C3
C4 S3 S2 S1 S0
Full adder Full adder Full adder Full adder
Binary Adder Subtractor
B3 A3 B2 A2 B1 A1 B0 A0
C0C1C2C3
C4 S3 S2 S1 S0
Full adder Full adder Full adder Full adder
• Operations can be combined into one common circuit by including an EXOR gate with each full adder. If M=0 B⊕0=B adds, If M=1 B⊕1=B’and C0=1 subtracts
• These operations consider each bit separately and treat them as binary variables
• Example: Exclusive orP: R1 � R1 ⊕ R2
• Special symbols will be adopted for the logic microoperations OR, AND and COMPLEMENT, to distinguish them from the corresponding symbols to express boolean functionsV is used for OR
Λ is used for AND
LOGIC MICROOPERATIONSLogic Microoperations
• Specify binary operations on the strings of bits in registers– Logic microoperations are bit-wise operations, i.e., they work on the
individual bits of data– useful for bit manipulations on binary data – useful for making logical decisions based on the bit value
• There are, in principle, 16 different logic functions that can be defined over two binary input variables
• However, most systems only implement four of these– AND (∧), OR (∨), XOR (⊕), Complement/NOT
• The others can be created from combination of these
• An left arithmetic shift operation must be checked for the overflow
0
VBefore the shift, if the leftmost twobits differ, the shift will result in anoverflow
• In a RTL, the following notation is used– ashl for an arithmetic shift left– ashr for an arithmetic shift right– Examples:
• R2 ← ashr R2• R3 ← ashl R3
signbit
SHIFT MICROOPERATIONS
• Example: Assume R1=11001110, then:
– Arithmetic shift right once : R1 = 11100111
– Arithmetic shift right twice : R1 = 11110011
– Arithmetic shift left once : R1 = 10011100
– Arithmetic shift left twice : R1 = 00111000
– Logical shift right once : R1 = 01100111
– Logical shift left once : R1 = 10011100
– Circular shift right once : R1 = 01100111
– Circular shift left once : R1 = 10011101
HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS
Shift Microoperations
S
01
H0MUX
S
01
H1MUX
S
01
H2MUX
S
01
H3MUX
Select0 for shift right (down) 1 for shift left (up)Serial
input (I R)
A0
A1
A2
A3
Serialinput (I L)
ARITHMETIC LOGIC SHIFT UNIT
• Instead of having individual registers performing the microoperations directly, computer systems employ a number of storage registers connected to a common operational unit called an Arithmetic Logic Unit (ALU )
S3 S2 S1 S0 Cin Operation Function0 0 0 0 0 F = A Transfer A0 0 0 0 1 F = A + 1 Increment A0 0 0 1 0 F = A + B Addition0 0 0 1 1 F = A + B + 1 Add with carry0 0 1 0 0 F = A + B’ Subtract with borrow0 0 1 0 1 F = A + B’+ 1 Subtraction0 0 1 1 0 F = A - 1 Decrement A0 0 1 1 1 F = A TransferA0 1 0 0 X F = A ∧∧∧∧ B AND0 1 0 1 X F = A ∨ ∨ ∨ ∨ B OR0 1 1 0 X F = A ⊕⊕⊕⊕ B XOR0 1 1 1 X F = A’ Complement A1 0 X X X F = shr A Shift right A into F1 1 X X X F = shl A Shift left A into F
Shift Microoperations
ArithmeticCircuit
LogicCircuit
C
C 4 x 1MUX
Select
0123
F
S3S2S1S0
BA
i
A
D
A
E
shrshl
i+1 i
ii
i+1i-1
i
i BUSES
Computer Buses
– A bus is a common electrical pathway between multiple devices.• Can be internal to the CPU to transport data to and from the ALU.
• Can be external to the CPU, to connect it to memory or to I/O devices.
– Early PCs had a single external bus or system bus .
– Modern PCs have a special-purpose bus between the CPU and memory and (at least) one other bus for the I/O devices.
• Bus lines (parallel)– Data– Address– Control – Power
• Bus lines (serial)– Data, address, and control are sequentially sent down
single wire– There may be additional control lines– Power
Data Bus
• Carries data– Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of performance– 8, 16, 32, 64 bit
134
Address bus
• Identify the source or destination of data• e.g. CPU needs to read an instruction
(data) from a given location in memory• Bus width determines maximum memory
capacity of system– e.g. 8080 has 16 bit address bus giving 64k
address space
135
Control Bus
• Control and timing information– Memory read/write signal– I/O read/write signal– Transfer ACK– Bus Request– Bus Grant– Interrupt request– Interrupt Acknowledge– Clock signals– Reset
• Time multiplexed– Shared lines– Address valid or data valid control line– Advantage - fewer lines
– Disadvantages• More complex control• Degradation of performance
Bus Width
• Bus width refers to the data and address bus widths. System performance improves with a wider data bus as we can move more bytes in parallel. We increase the addressing capacity of the system by adding more address lines.
• Wider the bus the better the data transfer rate or the wider the addressable memory space
• The address bus determines the system memory addressing capacity. A system with n address lines can directly address 2n memory words. In byte-addressable memories, that means 2n bytes
• Co-ordination of events on bus• Synchronous – a bus clock provides
synchronization of all bus operations• Asynchronous – donot use a common bus
clock signal; instead, these buses use handshaking to complete an operation by using additional synchronization signals
Synchronous Bus Timing
• Events determined by clock signals• Control Bus includes clock line• A single 1-0 cycle is a bus cycle• All devices can read clock line• Usually sync on leading/rising edge• Usually a single cycle for an event• Analogy – Orchestra conductor with baton• Usually stricter in terms of its timing
• Devices must have certain tolerances to provide responses to signal stimuli
• More flexible allowing slower devices to communicate on same bus with faster devices.
• Performance of faster devices, however, is limited to speed of bus
Asynchronous Bus Operation
• In asynchronous buses, there is no clock signal. Instead, they use four-way handshaking to perform a bus transaction. This handshaking is facilitated by two synchronization signals: master synchronization (MSYN) and slave synchronization (SSYN). We can summarize the operation as follows:1. Typically, the master places all the required data to initiate a
bus transaction and asserts the master synchronization signal MSYN.
2. Asserting MSYN indicates that the slave can receive the data and initiate the necessary actions on its part. When the slave is ready with its reply, it asserts SSYN.
3. The master receives the reply and then removes the MSYN signal to indicate receipt. For example, in a memory read transaction, the CPU reads the data supplied by the memory.
4. Finally, in response to the master deasserting MSYN, the slave removes its own synchronization signal SSYN to terminate the bus transaction.
Asynchronous Timing – Read• The master places the address and
command information on the bus.
• Then it indicates to all devices that it has done so by activating the Master-ready line.
• This causes all devices on the bus to decode the address.
• The selected slave performs the required operation and informs the processor it has done so by activating the Slave-ready line.
• The master waits for Slave-ready to become asserted before it removes its signals from the bus.
• In the case of a read operation, it also strobes the data into its input buffer.
Asynchronous Timing – Read• The master places the address and
command information on the bus.
• Then it indicates to all devices that it has done so by activating the Master-ready line.
• This causes all devices on the bus to decode the address.
• The selected slave performs the required operation and informs the processor it has done so by activating the Slave-ready line.
• The master waits for Slave-ready to become asserted before it removes its signals from the bus.
• In the case of a read operation, it also strobes the data into its input buffer.
• In this case, the master places the output data on the data lines at the same time that it transmits the address and command information.
• The selected slave strobes the data into its output buffer when it receives the Master-ready signal and indicates that it has done so by setting the S1ave-ready signal to 1.
• The remainder of the cycle is identical to the input operation.
Synchronous OR Asynchronous?
• Asynchronous buses allow more flexibility in timing.
• In synchronous buses, all timing must be a multiple of the bus clock. For example, if memory requires slightly more time than the default amount, we have to add a complete bus cycle
• The main advantage of asynchronous buses is that they eliminate this dependence on the bus clock.
• However, synchronous buses are easier to implement, as they donot use handshaking.
Bus Arbitration
– I/O chips have to become bus master to read and write memory and to cause interrupts.
– If two or more devices want to become bus master at the same time, a bus arbitrationmechanism is needed.
– Arbitration mechanisms can be centralized or decentralized.
Static Vs Dynamic Arbitration
• In static bus arbitration, bus allocation among the masters is done in a predetermined way. For example, we might use a roundrobin allocation that rotates the bus among the masters. The main advantage of a static mechanism is that it is easy to implement. However, since bus allocation follows a predetermined pattern rather than the actual need, a master may be given the bus even if it does not need it. This kind of allocation leads to inefficient use of the bus.
• In dynamic bus arbitration, bus allocation is done in response to a request from a bus master. To implement dynamic arbitration, each master should have a bus request and grant lines. A bus master uses the bus request line to let others know that it needs the bus to perform a bus transaction. Before it can initiate the bus transaction, it should receive permission to use the bus via the bus grant line. Dynamic arbitration consists of bus allocation and release policies.
• In the centralized scheme, a central arbiter receives bus requests from all masters. The arbiter, using the bus allocation policy in effect, determines which bus request should be granted. This decision is conveyed through the bus grant lines. Once the transaction is over, the master holding the bus would release the bus; the release policy determines the actual release mechanism.
• In the distributed implementation, arbitration hardware is distributed among the masters. A distributed algorithm is used to determine the master that should get the bus.
Bus Arbitration
Bus Allocation Policies
• Fixed Priority Policies– Each master is assigned a unique fixed priority. When multiple masters
request the bus, the highest priority master will get to use the bus• Rotating Priority Policies
– Priority of a master is not fixed. For example, priority of a master can be a function of the time waiting to get the bus. Thus, the longer a master waits, the higher the priority
• Fair Policies– Does not allow starvation– Some examples of fairness are :
• All bus requests in a predefined window must be satisfied before granting requests from the next window
• A bus request should not be pending for more than M milliseconds
• Hybrid Policies– Combination of Priority and Fairness– Also called Combined Policies– E.g. – PCI Bus
Bus Release Policies
• Non-Preemptive – In these policies, the current bus master voluntarily releases the bus
• Transaction-Based Release : A bus master holding the bus releases the bus when its current transaction is finished
• Demand Based Release : the current master releases the bus only if there is a request from another bus master; otherwise, it continues to use the bus. Typically, this check is done at the completion of each transaction
– A potential disadvantage of the non-preemptive policies is that a bus master may hold the bus for a longtime, depending on the transaction type. For example, long block transfers can hold the bus for extended periods of time.
• Preemptive– Preemptive policies force the current master to release the bus without
Centralized Bus Arbitration – Daisy Chaining Daisy Chain Method
• When the central arbiter receives a bus request, it sends out a bus grant signal to the first master in the chain.
• The bus grant signals are chained through the masters Each master can pass the incoming bus grant signal to its neighbor in the chain if it does not want to use the bus.
• If a master wants to use the bus, it grabs the bus grant signal and will not pass it on to its neighbor. This master can then use the bus for its bus transaction.
• Bus release is done by the release policy in effect.
• Daisy chaining is simple to implement and requires only three control lines independent of the number of hosts.
• Disadvantages– It implements a fixed priority policy– The bus arbitration time varies and is proportional to the number of masters– This scheme is not fault tolerant
Centralized Arbitration - Polling Polling
• In response to the bus request from one or more devices, the controller polls them (in a predesignedpriority order) and selects the highest priority device among them and grants the bus to it. Only one bus grant line is shown. But, only the selected device will be activated as bus master (i.e., accepts the bus grant). All the other devices will ignore it.
• The arbiter is connected to each master by separate bus request and grant lines
• When a master wants the bus, it sends its request through its own bus request line. Once the arbiter receives the bus requests from the masters, it uses the allocation policy to determine which master should get the bus next.
• Since the bus requests are received on separate lines, the arbiter can implement a variety of allocation policies: a rotating priority policy, a fair policy, or even a hybrid policy.
• It provides short, constant arbitration times and allows flexible priority assignment so that fairness can be ensured. In addition, it provides good fault tolerance. If a master fails, the arbiter can ignore it and continue to serve the other masters
• This implementation is complex. The number of control signals isproportional to the number of masters.
Decentralized Arbitration
– Decentralized bus arbitration is also possible.• A computer could have 16 prioritized bus request
lines. When a device wants to use the bus, it assert its request line.
• All devices monitor all request lines, so at the end of each bus cycle, each device knows whether it was the highest priority requester.
• This method avoids the necessity of an arbiter, but requires more bus lines.
• Another decentralized scheme equivalent to the daisy chain arbitration minus the arbiter is shown on the following slide.
Show the Block Diagram of the H/w that implements the following register transfer statement
yT2 : R2�R1 , R1�R2
Problem 4.2
The o/p of 4 registers R0, R1, R2 and R3 are connec ted through 4-to-1 line multiplexers to I/p of a fifth register R5. All the registers are 8 bit long. The required tran sfers are dictated by 4 timing variables T o through T 3 as follows
The timing variables are mutually exclusive, I.e., only one variable is equal to 1 at a time. Give a block diag ram for the h/w implementation of the register transfers. Inclu de the connections necessary from the four timing variable s to the selection I/p of the multiplexers and to the load I /p of register R5
Represent the following conditional control statement by two register transfer statements with control functions
If (P=1) then (R1�R2) else if (Q=1) then (R1�R3)
P : R1����R2P’Q : R1����R3
Problem 4.4
• Change the bus system in shown to be able to transfer information from any register to any other register? Specifically show the connections needed to provide a path from the o/p of register C to the I/p of register A
S1
S0
4-line Common
bus
4X1
MUX3
3 2 1 0
3 2 1 0
Register D
D3 D2 D1 D0
4X1
MUX3
3 2 1 0
4X1
MUX3
3 2 1 0
4X1
MUX3
3 2 1 0
D2 C2 B2 A2 D0 C0 B0 A0D1 C1 B1 A1D3 C3 B3 A3
3 2 1 0
Register C
C3 C2 C1 C0
3 2 1 0
Register B
B3 B2 B1 B0
3 2 1 0
Register A
A3 A2 A1 A0
Solution
• In this question we use S1 S0 to select the source register (With S1 being HSB), and use S3 S2 to select among the four registers available (with S3 being the HSB).
Problem 4.5
• Draw a bus system similar to that shown but use three state buffers and a decoder instead of the multiplexers.
• A digital computer has a common bus system for 16 registers of 32 bit each. The bus is constructed with multiplexers.a) How many selection I/p are there in each multiplexer?
b) What size of multiplexers are needed?
c) How many multiplexers are there in the bus?
Solutiona) 4 Selection lines to select one of the 16 register sb) 16 x 1 Multiplexersc) 32 Multiplexers, one for each bit of the register s.
Problem 4.7
The following transfer statements specify a memory. Explain the memory operation in each case?
a) R2 � M[AR]b) M[AR] � R3c) R5 � M[R5]
Solution
a) R2 ���� M[AR] – This statement would transfer the contents of Memor y
word that has the address specified by AR into R2 register.
b) M[AR] ���� R3– WRITE the value in register R3 into the Memory Word
that has the address specified in AR.
c) R5����M[R5]– It will firstly READ the Memory Word specified by R 5
and then transfer the value into the same register R5, this is mostly used in Indirect Addressing.
Consider the following register transfer statements for two 4 bit registers R1 and R2
xT : R1 � R1 + R2x’T : R1 � R2
Draw BD for the h/w implementation. Use BD for the the two 4 bit registers, a 4-bit adder and a quadruple 2-to-1 line mux that selects the I/p to R1. Show how the control variables x and T select the I/p of the mux and the load I/p of the register.
Solution
Problem 4.11
• Using a 4 bit counter with parallel load and a 4 bit adder, draw a BD to implement the following
x: R1 � R1 + R2x’y : R1 � R1 + 1
Where R1 is a counter with parallel load and R2 is a 4 bit register
Design an arithmetic ckt with one selection var S and two n-bit data I/p A and B. the ckt generates the following 4 arith operations in conjunction with the I/p carry Cin. Draw the logic diagram for the first two stages.
D = A + B + 1 (Subtract)D = A – 1 (Decrement)1
D = A + 1 (Increment)D = A + B (Add)0
Cin = 1Cin = 0S
Solution Problem 4-16
Derive a Combinational ckt that selects and generates any of the 16 logic functions
Draw a digital ckt that performs the 4 logic operations of EX-OR, EX-NOR, NOR and NAND. Use two selection var. show the logic diag of one typical stage.
Problem 4-18
Register A holds the value 11011001, determine the B operand and the logic microperation to be performed in order to change the value in A to
(a) 01101101 (b) 11111101
Problem 4-19
The 8-bit registers AR, BR, CR and DR initially have the values 11110010, 11111111, 10111001 and 11101010 respectively.
Determine the 8-bit values in each register after the execution of the following microoperations.
• An 8-bit register holds the value 10011100. What is the register value after an arithmetic shift right? Starting from the initial no. 10011100 determine the register value after an arithmetic shift left, and state whether there is an overflow.
Problem 4-21
Starting from an initial value of R=11011101, determine the sequence of binary values in R after a logical shift left, followed by a circular shift right followed by a logical shift right and a circular shift left.
Problem 4-22
What is the value of o/p H if I/p A = 1001, S=1, IR= 1 and IL = 0?
S01
H0MUX
S01
H1MUX
S01
H2MUX
S01
H3MUX
Select 0 for shift right (down) 1 for shift left (up)
Serialinput (I R)
A0
A1
A2
A3
Serialinput (I L)
Problem 4-23
What is wrong with the following Microoperations1. xT: AR � AR, AR � 0
• The range is effectively determined by the number of digits i n the exponent.
• The precision is determined by the number of digits in the fraction.– More bits for significand gives more accuracy– More bits for exponent increases range
• For Binary (–1)sign x significand x 2 exponent
Modeling the Real Number System
• Floating-point numbers can be used to model the rea l-number system of mathematics, although there are some important differences.
• The real line is divided up into seven regions:1. Large negative numbers less than −0.999 × 10 99.2. Negative numbers between −0.999 × 10 99 and −0.100 × 10−99.3. Small negative numbers with magnitudes less than −0.100 × 10 −99.4. Zero.5. Small positive numbers with magnitudes less than 0.100 × 10 −99.6. Positive numbers between 0.100×10 −99 and 0.999 × 1099.7. Large positive numbers greater than 0.999 × 10 99.
• Overflow regions:– Due to finite nature of representation in computers , overflow
(Region 1&7) and Underflow (Regions 3 & 5) cannot b e expressed
• Underflow:– Underflow errors are less serious than overflow err ors
– Underflow can be approximated to zero
Rounding
• It is quite possible for the result of a calculatio n to be one of the other numbers, even though it is in region 2 or 6.– For example, +0.100 × 10 3 divided by 3 cannot be expressed
exactly.
• The obvious thing to do is to use the nearest numbe r that can be expressed.
• This process is called rounding .
Relative Error
• The “space” between adjacent expressible numbers in regions 2 and 6 is not constant.
• The separation between +0.998 × 10 99 and +0.999×1099 is very different than that between +0.998 × 10 0 and +0.999 × 100
• However, when separation between a number and its s uccessor is expressed as a percentage of that number, there is no systematicvariation throughout region 2 or 6.
• The relative error introduced by rounding is approximately the same for small numbers as large numbers.
Effects of Changes in the System
• Changing the number of digits in the fraction or ex ponent shifts the boundaries of regions 2 and 6 and changes the numbe r of expressible points in them.
• Increasing the number of digits in the fraction inc reases the density of points and therefore improves the accura cy of approximations.
• Increasing the number of digits in the exponent inc reases the size of regions 2 and 6 by shrinking regions 1, 3, 5, an d 7.
• A floating point number is said to be normalized if the most significant digit of the mantissa is nonzero
• For example the decimal number 350 is normalized bu t 00035 is not.
• Regardless of where the position of the radix point is assumed to be in the mantissa, the number is normalized onl y if its leftmost digit is nonzero.
• Example:(2.0) x 10-9 Normalized
(0.2) x 10-8 Not-normalized(20.0) x 10-10 Not-normalized
Floating-Point for Binary Numbers
• Floating point:– Computer arithmetic that represents numbers in whic h
binary point is not fixed• Example: (1.0) x 2 -1
– Opposite of fixed-point notation:• Example: 123.456
• Computers support floating-point arithmetic • The fractional point is called the “binary point”
Binary Normalized Form
• Why Normalized form? – Simplifies exchange of data
– Simplifies floating-point algorithms
– Increase accuracy of numbers
• Format:
(1.xxxxxx) x 2 yyyyy
• How can we convert to normalized form– need a base that can exactly be decreased or incre ased
by the number of bits to be shifted
• Normalized numbers are generally preferable to unnormalized numbers, because there is only one normalized form, whereas there are many unnormalized forms.
Floating Point Number Representation
Decimal Value:V = M * R E
Where: M= MantissaE= ExponentR= Radix (10)
Example (decimal):1234.5678
Exponent MantissaSign Value Sign Value0 4 0 0.12345678
Make a fractional number, counting the number of sh ifts:+ .100111 ==> 4 shifts
Exponent MantissaSign Value Sign Value0 100 0 1001111
Or for a 16-bit number with a sign, 5-bit exponent, 10-bit mantissa:
0 00100 1001111000
Floating Point Number Representation Single Precision Floating Point (FP) Numbers
• Current computer systems dictate that FP numbers mu st fit in 32-or 64-bit registers.
• 32-bit or single precision FP numbers are organized as follows:(-1)s x Fraction x 2 E
seee eeee emmm mmmm mmmm mmmm mmmm mmmm
• where s is the sign of the number, e represents the biased exponent (8 bits) and m represents the mantissa or significand (23 bits)
• 32-bit values range in magnitude from 10 -38 to 1038.
31 30 . . . 23 22 . . . 0
s exponent Significand (Mantissa/Fraction)
Double Precision Floating Point Numbers
• 64 bit double precision floating point numbers(Value represented in two 32-bit words) are organized as follows:– The MSB is the sign bit – The next 11 bits are the exponent – The remaining 20+32=52 bits are the significand
• The range in magnitude is from 10 -308 to 10 308
• The growth of significand and exponent is a compromise between accuracy and range.
31 30 . . . 20 19 . . . 0
s exponent Significand (Mantissa/Fraction)
Significand (Mantissa/Fraction) Continued
Biased Exponent
• Exponents can be both positive ad negative giving r ise to a need of sign bit in exponents.– eg. Exponents ranging from – 50 to 49 need 2 digits f or the
value and one bit for the sign.
• Biased Exponent eliminates the need for sign by adding a positive quantity to the exponent so that it is alw ays positive– Adding 50 to our example exponent makes the range a s 0 to
99, value requiring 2 digits and no sign bit needed .
• 1985 by William Kahan (Berkley)• Found virtually in every computer since 1980• Until 1980, every computer manufacturer had their o wn FP format• Some of the format did incorrect arithmetic• IEEE Standard permits FP data to be exchanged among different