CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2003 TopicA: Flow Analysis José Nelson Amaral.

CMPUT 229 - Computer Organization and Architecture I

1

CMPUT229 - Fall 2003

TopicA: Flow AnalysisJosé Nelson Amaral


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Reading Material

The concepts necessary for flow analysis, such as basic blocks,control flow graphs, and data dependence graphs are presentedin several compiler textbooks (most of these books are available in the UofA library). For instance:

Randy Allen, Ken Kennedy, Optimizing Compilers for Modern Architectures: A Dependence-based Approach, Morgan Kauffman, 2001.

Andrew W. Appel : Modern Compiler Implementation in C

A. Aho, R. Sethi and J. Ullman, Compilers: Principles, Techniques and Tools (The Dragon Book), Addison Wesley, 1988

M. Wolfe, High Performance Compilers of Parallel Computing, Addison Wesley, 1995

S. Muchnick, Advanced Compiler Design and Implementation, Morgan Kaufman, 1997

Section 6.4 (pp. 476) of Patterson-Hennessy has a brief discussion of data dependences.


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Analysing Code

Given the code for Panic in the previous slide. What is thebest way to analyse it?

Compilers use the notion of a basic block. A basic block isa sequence of instructions with the following property:

Whenever one instruction of the basic block isexecuted, all the instructions in the basic blockmust be executed.

I.e., only the first instruction of a basic block can be the targetof a jump or branch, and only the last instruction in a basicblock can be a jump or a branch.


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Finding Basic Blocks

Given a sequence of assembly code, compilers can findthe leaders of basic blocks using a very simple set of rules:

The first instruction of a basic block is the leader of the basic block.

(i) The first instruction in the program is a leader.

(ii) Any statement that is the target of a branch statement is a leader (in general these instructions have an associated label).

(iii) Any instruction that immediately follows a branch or return instruction is a leader.


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Identify the leadersException Handler:

DisplayData = 0xbfff0008DisplayStatus = 0xbfff000c.kdata

Pmess: .asciiz “Panic: “.ktext # Panic prints a message and quits

Panic: la $a1, PmessPRead1: lb $a2, ($a1) # read letter to print

beq $a2, $zero, PRead2 # done when we find a nullPWait1: lw $a3, DisplayStatus # Read the status of the display

bge $a3, $zero, PWait1 # keep reading until it is readysw $a2, DisplayData # output characteraddi $a1, $a1, 1 # advance characterj PRead1

PRead2: lb $a2, ($a0) # Print message pointed by $a0beq $a2, $zero, Pcontinue # done when we find a null

PWait2: lw $a3, DisplayStatus # Read the status of the displaybge $a3, $zero, PWait2 # keep reading until it is readysw $a2, DisplayData # output characteraddi $a0, $a0, 1 # advance characterj PRead2

Pcontinue: li $v0, 0 # clear re-entrance flagsw $v0, flagli $v0, 13 # the quit_now syscallsyscall


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Basic Block Formation Rule

Once we know the leaders, the basic block formation followsa simple rule:

A basic block is formed by a leader and all the instructionsthat come after the leader up to but not including the nextleader.

Panic: la $a1, PmessB1

PRead1: lb $a2, ($a1)beq $a2, $zero, PRead2

B2

PWait1: lw $a3, DisplayStatusbge $a3, $zero, PWait1

B3

sw $a2, DisplayDataaddi $a1, $a1, 1j PRead1

B4

PRead2: lb $a2, ($a0)beq $a2, $zero, Pcontinue

B5


B6


B7

Pcontinue: li $v0, 0sw $v0, flagli $v0, 13syscall

B8

Now that we have the basicblocks, we can connect them using two simple rules:

(1) connect Bi to Bj if there is a branch or jump from the last instruction of Bi to the first instruction of Bj.

(2) connect Bi to Bj if both:

(i) Bj immediately follows Bi, and

(ii) Bi does not end with an unconditional jump

Panic: la $a1, PmessB1

PRead1: lb $a2, ($a1)beq $a2, $zero, PRead2

B2


B3


B4

PRead2: lb $a2, ($a0)beq $a2, $zero, Pcontinue

B5

PWait2: lw $a3, DisplayStatusbge $a3, $zero, Wait2

B6


B7

Pcontinue: li $v0, 0sw $v0, flagli $v0, 13syscall

B8

B1

B2

B3B5

B4B6

B7

B8

The graph that connects the basicblocks in this way is called theControl Flow Graph for the program.


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Apply the basic blockformation algorithmthat you just learnedto the matrix multiplicationcode from Topic 7.

MIPS assembly:li $t1, 32 # t1 32li $s0, 0 # i 0

L1: li $s1, 0 # j 0L2: mtc1 $zero, $f4

mtc1 $zero, $f5li $s2, 0 # k 0

L3: sll $t2, $s0, 5 # $t2 32 iaddu $t2, $t2, $s2 # $t2 32 i + k

sll $t2, $t2, 3 # $t2 (32 i + k) 8 addu $t2, $a1, $t2 # $t2 Addr(y[i][k])l.d $f16, 0($t2) # $f16 y[i]

[k]sll $t2, $s2, 5 # $t2 32 kaddu $t2, $t2, $s1 # $t2 32 i + j

sll $t2, $t2, 3 # $t2 (32 k + j) 8 addu $t2, $a2, $t2 # $t2 Addr(z[k][j])l.d $f18, 0($t2) # $f16 z[k]

[j]mul.d $f16, $f18, $f16 # $f16 y[i][k]z[k][j]add.d $f4, $f4, $f16addiu $s2, $s2, 1 # k k+1bne $s2, $t1, L3sll $t2, $s0, 5 # $t2 32 iaddu $t2, $t2, $s1 # $t2 32 i + j

sll $t2, $t2, 3 # $t2 (32 i + j) 8 addu $t2, $a0, $t2 # $t2 Addr(x[i][j])swc1 $f4, 0($t2) # x[i][j] $f4swc1 $f5, 4($t2)addiu $s1, $s1, 1 # j j+1bne $s1, $t1, L2addiu $s0, $s0, 1 # i i+1bne $s0, $t1, L1•••


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L1: li $s1, 0 # j 0L2: mtc1 $zero, $f4








Apply the basic blockformation algorithmthat you just learnedto the matrix multiplicationcode from Topic 7.

B0

B2

B3

B4

B5

B1


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L1: li $s1, 0 # j 0L2: mtc1 $zero, $f4








Build a Control FlowGraph for this code.

B0

B1

B2

B3

B4

B0

B2

B3

B4

B5

B1

B5


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Superscalar Pipelined Machines

COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED


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Data Dependencies

We say that there is a data dependence between two instructionsif is is not possible to invert the order of execution of the two instructions without producing wrong results.

l.d $f18, 0($t2) # $f16 z[k][j]mul.d $f16, $f18, $f16 # $f16 y[i][k]z[k][j]

When the first instruction computes a value that the secondinstruction uses, we say that there is a flow dependencefrom the first to the second instruction.

For instance, in the sequence of instructions above, thevalue of $f18 is computed by the load and used by the multiply instruction. Therefore there is a flow dependencefrom the load to the store.


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Data Flow Graphs

Compilers often have to take into consideration the dependencesbetween instructions.

In its data flow analysis, compilers typically build a data flow graphalso called a data dependence graph for each basic block of the program.

A data flow graph is a directed graph with one node for each instruction in the basic block.

An edge (vi, vj) in the data flow graph indicates thatthere is a flow dependence from vi to vj.


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Build a Data DependenceGraph for Basic Block B3

MIPS assembly: a li $t1, 32 # t1 32 b li $s0, 0 # i 0L1: c li $s1, 0 # j 0L2: d mtc1 $zero, $f4 e mtc1 $zero, $f5 f li $s2, 0 # k 0L3: g sll $t2, $s0, 5 # $t2 32 i h addu $t2, $t2, $s2 # $t2 32 i + k i sll $t2, $t2, 3 # $t2 (32 i + k) 8 j addu $t2, $a1, $t2 # $t2 Addr(y[i][k]) k l.d $f16, 0($t2) # $f16 y[i][k] l sll $t2, $s2, 5 # $t2 32 k m addu $t2, $t2, $s1 # $t2 32 i + j n sll $t2, $t2, 3 # $t2 (32 k + j) 8 o addu $t2, $a2, $t2 # $t2 Addr(z[k][j]) p l.d $f18, 0($t2) # $f16 z[k][j] q mul.d $f16, $f18, $f16 # $f16 y[i][k]z[k][j] r add.d $f4, $f4, $f16 s addiu $s2, $s2, 1 # k k+1 t bne $s2, $t1, L3 u sll $t2, $s0, 5 # $t2 32 i v addu $t2, $t2, $s1 # $t2 32 i + j w sll $t2, $t2, 3 # $t2 (32 i + j) 8 x addu $t2, $a0, $t2 # $t2 Addr(x[i][j]) y swc1 $f4, 0($t2) # x[i][j] $f4 z swc1 $f5, 4($t2) a1 addiu $s1, $s1, 1 # j j+1 b1 bne $s1, $t1, L2 c1 addiu $s0, $s0, 1 # i i+1 c2 bne $s0, $t1, L1

•••

B0

B2

B3

B4

B5

B1

Build a Data DependenceGraph for Basic Block B3

s0

g

h

s2

i

j

a1

k

l

m

s1

n

o

a2

MIPS assembly: a li $t1, 32 # t1 32 b li $s0, 0 # i 0L1: c li $s1, 0 # j 0L2: d mtc1 $zero, $f4 e mtc1 $zero, $f5 f li $s2, 0 # k 0L3: g sll $t2, $s0, 5 # $t2 32 i h addu $t2, $t2, $s2 # $t2 32 i + k i sll $t2, $t2, 3 # $t2 (32 i + k) 8 j addu $t2, $a1, $t2 # $t2 Addr(y[i][k]) k l.d $f16, 0($t2) # $f16 y[i][k] l sll $t2, $s2, 5 # $t2 32 k m addu $t2, $t2, $s1 # $t2 32 i + j n sll $t2, $t2, 3 # $t2 (32 k + j) 8 o addu $t2, $a2, $t2 # $t2 Addr(z[k][j]) p l.d $f18, 0($t2) # $f16 z[k][j] q mul.d $f16, $f18, $f16 # $f16 y[i][k]z[k][j] r add.d $f4, $f4, $f16 s addiu $s2, $s2, 1 # k k+1 t bne $s2, $t1, L3 u sll $t2, $s0, 5 # $t2 32 i v addu $t2, $t2, $s1 # $t2 32 i + j w sll $t2, $t2, 3 # $t2 (32 i + j) 8 x addu $t2, $a0, $t2 # $t2 Addr(x[i][j]) y swc1 $f4, 0($t2) # x[i][j] $f4 z swc1 $f5, 4($t2) a1 addiu $s1, $s1, 1 # j j+1 b1 bne $s1, $t1, L2 c1 addiu $s0, $s0, 1 # i i+1 c2 bne $s0, $t1, L1

•••

B0

B2

B3

B4

B5

B1

p

q

r

f4

s

t1

t

s2 f4

Analysing the DDG on the left, it seems thatinstructions g-h-i-j-k could be executed

at the same time as l-m-n-o-p.

But in the assembly code above,it seems that there is a conflict with the

use of register $t2. How compilersdeal with a situation like this?

Using pseudo-registers.

MIPS assembly: a li $t1, 32 # t1 32 b li $s0, 0 # i 0L1: c li $s1, 0 # j 0L2: d mtc1 $zero, $f4 e mtc1 $zero, $f5 f li $s2, 0 # k 0L3: g sll $p2, $s0, 5 h addu $p3, $p2, $s2 i sll $p4, $p3, 3 j addu $p5, $a1, $p4 k l.d $f16, 0($p5) l sll $p6, $s2, 5 m addu $p7, $p6, $s1 n sll $p8, $p7, 3 o addu $p9, $a2, $p8 p l.d $f18, 0($p9) q mul.d $pf17, $f18, $f16 r add.d $f4, $f4, $pf17 s addiu $p10, $s2, 1 t bne $p10, $t1, L3 u sll $t2, $s0, 5 # $t2 32 i v addu $t2, $t2, $s1 # $t2 32 i + j w sll $t2, $t2, 3 # $t2 (32 i + j) 8 x addu $t2, $a0, $t2 # $t2 Addr(x[i][j]) y swc1 $f4, 0($t2) # x[i][j] $f4 z swc1 $f5, 4($t2) a1 addiu $s1, $s1, 1 # j j+1 b1 bne $s1, $t1, L2 c1 addiu $s0, $s0, 1 # i i+1 c2 bne $s0, $t1, L1

•••

B0

B2

B3

B4

B5

B1

s0

g

h

s2

i

j

a1

k

l

m

s1

n

o

a2

p

q

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f4

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t1

t

s2 f4

Compilers rename the registers, generatinga code with pseudo-registers.

For the first code generation, they assumethat there is an ilimited number of

pseudo-registers.


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Value of Flow Analysis

Although flow analysis was developed for code analysis duringcompilation, it is of great value while coding and debugging programs.

Often, the analysis of the control flow and data flow in a programwill elicit subtle bugs that might be otherwise difficult to uncover.

Control flow analysis is specially helpful for the analysis of assembly code in which the control structure of the code isnot as evident as in higher level languages.


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Definition: Let G = (N, E, s, f) denote a flowgraph, where: N: set of vertices

E: set of edges s: starting node.

f: sink node and let a N, b N.

Domination Relation

1. a dominates b, if every path from s to b contains a.

2. b post-dominates a, if every path from a to f contains b.


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S

Domination relation:{ (1, 1), (1, 2), (1, 3), (1,4) … (2, 3), (2, 4), … (2, 10)}

Dominator Sets:DOM(1) = {1}DOM(2) = {1, 2}DOM(3) = {1, 2, 3}DOM(10) = {1, 2, 10)

An Example


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Dominance Intuition

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SImagine a source of lightat the start node, and thatthe edges are optical fibers

To find which nodes are dominated by a given node, place an opaque barrier at that node and observe which nodes became dark.


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Dominance Intuition

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SThe start node dominates all nodes in the flowgraph.


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Dominance Intuition

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Which nodes are dominatedby node 3?


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Dominance Intuition

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6 7

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Node 3 dominates nodes3, 4, 5, 6, 7, 8, and 9.



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Dominance Intuition

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6 7

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Node 7 only dominatesitself.


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Live Values

When allocating registers for a basic block, a compiler needs tocompute which values are live at the entrance of a basic block.

We say that a value is live at any point of a program if there isa possibility that the value will be used in the program.

lw $t8, 0($t6)addu $t6, $t6, 12sw $t8, 0($t9)lw $t7, -8($t6)addu $t9, $t9, 12sw $t7, -8($t9)lw $t8, -4($t6)sw $t8, -4($t9)

Which registers contain a live value in the following basic block?

Registers $t6 and $t9contain live values.

CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2003 TopicA: Flow Analysis José Nelson Amaral.

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