CMPT 334 Computer Organization Midterm I Review. March 10 Monday during class hours close book cheat sheet (one side of the printing paper) Calculator.

CMPT 334 Computer OrganizationMidterm I Review

•March 10 Monday•during class hours

•close book•cheat sheet (one side of the printing

paper)•Calculator is allowed.•MIPS register convention, instruction

formats and operation code will be provided.

•Two questions on Chapter 1

Defining (Speed) Performance• To maximize performance, need to minimize execution

time

performanceX = 1 / execution_timeX

If X is n times faster than Y, then

performanceX execution_timeY -------------------- = --------------------- = nperformanceY execution_timeX

Decreasing response time almost always improves throughput

Relative Performance Example• If computer A runs a program in 10 seconds and

computer B runs the same program in 15 seconds, how much faster is A than B?

We know that A is n times faster than B if

performanceA execution_timeB -------------------- = --------------------- = nperformanceB execution_timeA

15 ------ = 1.510

The performance ratio is

So A is 1.5 times faster than B

CPU Clocking•Operation of digital hardware governed by

a constant-rate clock

Clock (cycles)

Data transferand computation

Update state

Clock period

Clock period: duration of a clock cycle e.g., 250ps = 0.25ns = 250×10–12s

Clock frequency (rate): cycles per second e.g., 4.0GHz = 4000MHz = 4.0×109Hz

Instruction Count and CPI

•Instruction Count for a program▫Determined by program, ISA and compiler

•Average cycles per instruction▫Determined by CPU hardware▫If different instructions have different CPI

Average CPI affected by instruction mix

Rate Clock

CPICount nInstructio

Time Cycle ClockCPICount nInstructioTime CPU

nInstructio per CyclesCount nInstructioCycles Clock

Using the Performance Equation

• Computers A and B implement the same ISA. Computer A has a clock cycle time of 250 ps and an effective CPI of 2.0 for some program and computer B has a clock cycle time of 500 ps and an effective CPI of 1.2 for the same program. Which computer is faster and by how much?

Each computer executes the same number of instructions, I, so

CPU timeA = I x 2.0 x 250 ps = 500 x I ps

CPU timeB = I x 1.2 x 500 ps = 600 x I ps

Clearly, A is faster … by the ratio of execution timesperformanceA execution_timeB 600 x I ps

------------------- = --------------------- = ---------------- = 1.2performanceB execution_timeA 500 x I ps

Amdahl’s Law•Improving an aspect of a computer and

expecting a proportional improvement in overall performance

2080

20 n

Can’t be done!

unaffectedaffected

improved Tfactor timprovemen

TT

Example: multiply accounts for 80s/100s How much improvement in multiply performance to

get 5× overall?

Corollary: make the common case fast

•Amdah’s Law, together with the CPU performance equation, is a handy tool for evaluation potential enhancements.

unaffectedaffected

improved Tfactor timprovemen

TT

Rate Clock

CPICount nInstructio

Time Cycle ClockCPICount nInstructioTime CPU

nInstructio per CyclesCount nInstructioCycles Clock

MIPS as a Performance Metric•MIPS: Millions of Instructions Per Second

▫Faster computers have a higher MIPS rating.▫Doesn’t account for

Differences in ISAs between computers Differences in complexity between instructions

66

6

10CPI

rate Clock

10rate Clock

CPIcount nInstructiocount nInstructio

10time Execution

count nInstructioMIPS

We cannot compare computers with different instruction sets using MIPS.

•4 short questions regarding 2’s complement representation

Unsigned Binary Integers

•The value of ith digit d is ▫d * Basei

▫i starts at 0 and increases from right to left Example

0000 0000 0000 0000 0000 0000 0000 10112

= 0 + … + 1×23 + 0×22 +1×21 +1×20

= 0 + … + 8 + 0 + 2 + 1 = 1110

•lease significant bit: the rightmost bit•most significant bit: the leftmost bit

Unsigned Binary Integers•Given an n-bit number

00

11

2n2n

1n1n 2x2x2x2xx

Using 32 bits 0 to +4,294,967,295 Range: 0 to +2n – 1

These positive numbers are called unsigned numbers.

Hexadecimal•Base 16

▫Compact representation of bit strings▫4 bits per hex digit

0 0000 4 0100 8 1000 c 1100

1 0001 5 0101 9 1001 d 1101

2 0010 6 0110 a 1010 e 1110

3 0011 7 0111 b 1011 f 1111

Example: eca8 6420 1110 1100 1010 1000 0110 0100 0010 0000

2s-Complement Representation•Given an n-bit number

00

11

2n2n

1n1n 2x2x2x2xx

Example 1111 1111 1111 1111 1111 1111 1111 11002

= –1×231 + 1×230 + … + 1×22 +0×21 +0×20

= –2,147,483,648 + 2,147,483,644 = –410

Range: –2n – 1 to +2n – 1 – 1 Using 32 bits

–2,147,483,648 to +2,147,483,647 Most-negative: 1000 0000 … 0000 Most-positive: 0111 1111 … 1111

2s-Complement Signed Integers•Every computer today uses two’s

complement binary representation for signed numbers.

•Bit 31 is sign bit▫1 for negative numbers▫0 for non-negative numbers

•231 can’t be represented•Non-negative numbers have the same

unsigned and 2s-complement representation•Some specific numbers

▫ 0: 0000 0000 … 0000▫–1: 1111 1111 … 1111

Signed Negation•Complement and add 1

▫Complement means 1 → 0, 0 → 1

x1x

11111...111xx 2

Example: negate +2 +2 = 0000 0000 … 00102

–2 = 1111 1111 … 11012 + 1 = 1111 1111 … 11102

2’sc binary decimal

1000 -8

1001 -7

1010 -6

1011 -5

1100 -4

1101 -3

1110 -2

1111 -1

0000 0

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

23 - 1 =

-(23 - 1) =

-23 =

1010

complement all the bits

1011

and add a 1

complement all the bits

0101

and add a 1

0110

Sign Extension

•Representing a number using more bits▫Preserve the numeric value

•In MIPS instruction set▫lb, lh: extend signed loaded byte/halfword

•Replicate the sign bit to the left▫c.f. unsigned values: extend with 0s

•Examples: 8-bit to 16-bit▫+2: 0000 0010 => 0000 0000 0000 0010▫–2: 1111 1110 => 1111 1111 1111 1110

•1 - 2 short question(s) related to instruction format▫R▫I▫J

Machine Language – Arithmetic Instruction

MIPS Instruction Fields

•op•rs•rt•rd•shamt• funct

op rs rt rd shamt funct

6 bits 5 bits 5 bits 5 bits

5 bits

6 bits

= 32 bits

opcode indicating operation to be performed

address of the first register source operand

address of the second register source operand

the register destination address

shift amount (for shift instructions), 00000 for now

function code that selects the specific variant of the operation specified in the opcode field (extends opcode)

MIPS I-format Instructions

•Immediate arithmetic and load/store instructions▫rs: source register number▫rt: destination register number▫Constant: –215 to +215 – 1▫Address: offset added to base address in rs

•Example: ▫addi $s1, $s2, 100▫8 18 17 100

op rs rt constant or address

6 bits 5 bits 5 bits 16 bits

•Design Principle 4: Good design demands good compromises▫The similarity of the binary representations of

related instructions simplifies hardware design.

▫Different formats complicate decoding, but allow 32-bit instructions uniformly First three fields are the same in R-type and

I-type Formats are distinguished by the first field

• Instructions:bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1

• Machine Formats:

• How is the branch destination address specified?

Assembling Branches

op rs rt 16 bit number I format

5 16 17 ????

4 16 17 ????

Specifying Branch Destinations

• Could use a “base” register and add to it the 16-bit offset▫which register?

Instruction Address Register (PC = program counter) - its use is automatically implied by branch

PC gets updated (PC+4) during the Fetch cycle so that it holds the address of the next instruction

▫ limits the branch distance to -215 to +215-1 instr’s from the (instruction after the) branch but most branches are local

anyway

bne $s0,$s1,Lbl1

add $s3,$s0,$s1

...Lbl1:

Could specify the memory address - but that would require a 32 bit field

PC

• Assembly code bne $s0, $s1, Lbl1

add $s3, $s0, $s1Lbl1: ...

• Machine Format of bne:

Assembling Branches Example

op rs rt 16 bit offset I format

5 16 17

Remember After the bne instruction is fetched, the PC is updated so

that it is addressing the add instruction (PC = PC + 4). The offset (plus 2 low-order zeros) is sign-extended and

added to the (updated) PC

0x0001

• Instruction: j Lbl #go to Lbl

• Machine Format:

Assembling Jumps

op 26-bit address J format

2 ????

How is the jump destination address specified? As an absolute address formed by

- concatenating 00 as the 2 low-order bits to create a 28 bit address

- concatenating the upper 4 bits of the current PC (now PC+4)

Target Addressing Example•Loop code from earlier example

▫Assume Loop at location 80000

Loop: sll $t1, $s3, 2 80000 0 0 19 9 2 0

add $t1, $t1, $s6 80004 0 9 22 9 0 32

lw $t0, 0($t1) 80008 35 9 8 0

bne $t0, $s5, Exit 80012 5 8 21 2

addi $s3, $s3, 1 80016 8 19 19 1

j Loop 80020 2 20000

Exit: … 80024

•3-4 questions on assembly language programming▫Convert from C/C++ to ASM▫Given the assembly code, describe what it

does•Best ways to study

▫Homework▫Examples in lecture slides▫Notes

Review: MIPS Instructions, so far

Category Instr OpC Example Meaning

Arithmetic

(R & I format)

add 0 & 20 add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract 0 & 22 sub $s1, $s2, $s3 $s1 = $s2 - $s3

add immediate 8 addi $s1, $s2, 4 $s1 = $s2 + 4

shift left logical 0 & 00 sll $s1, $s2, 4 $s1 = $s2 << 4

shift right logical

0 & 02 srl $s1, $s2, 4 $s1 = $s2 >> 4 (fill with zeros)

shift right arithmetic

0 & 03 sra $s1, $s2, 4 $s1 = $s2 >> 4 (fill with sign bit)

and 0 & 24 and $s1, $s2, $s3 $s1 = $s2 & $s3

or 0 & 25 or $s1, $s2, $s3 $s1 = $s2 | $s3

nor 0 & 27 nor $s1, $s2, $s3 $s1 = not ($s2 | $s3)

and immediate c and $s1, $s2, ff00 $s1 = $s2 & 0xff00

or immediate d or $s1, $s2, ff00 $s1 = $s2 | 0xff00

Review: MIPS Instructions, so far

Category Instr OpC Example Meaning

Datatransfer(I format)

load word 23 lw $s1, 100($s2) $s1 = Memory($s2+100)

store word 2b sw $s1, 100($s2) Memory($s2+100) = $s1

load byte 20 lb $s1, 101($s2) $s1 = Memory($s2+101)

store byte 28 sb $s1, 101($s2) Memory($s2+101) = $s1

load half 21 lh $s1, 101($s2) $s1 = Memory($s2+102)

store half 29 sh $s1, 101($s2) Memory($s2+102) = $s1

Cond. branch

(I & R format)

br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L

br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L

set on less than immediate

a slti $s1, $s2, 100 if ($s2<100) $s1=1; else $s1=0

set on less than

0 & 2a slt $s1, $s2, $s3 if ($s2<$s3) $s1=1; else $s1=0

Uncond. jump

jump 2 j 2500 go to 10000

jump register 0 & 08 jr $t1 go to $t1